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armv8/fsl-lsch3: Fix platform clock calculation
Platform clock is half of platform PLL. There is an additional divisor in place. Clean up code copied from powerpc. Signed-off-by: York Sun <yorksun@freescale.com>
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@ -86,6 +86,8 @@ void get_sys_info(struct sys_info *sys_info)
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sys_info->freq_systembus *= (in_le32(&gur->rcwsr[0]) >>
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sys_info->freq_systembus *= (in_le32(&gur->rcwsr[0]) >>
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FSL_CHASSIS3_RCWSR0_SYS_PLL_RAT_SHIFT) &
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FSL_CHASSIS3_RCWSR0_SYS_PLL_RAT_SHIFT) &
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FSL_CHASSIS3_RCWSR0_SYS_PLL_RAT_MASK;
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FSL_CHASSIS3_RCWSR0_SYS_PLL_RAT_MASK;
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/* Platform clock is half of platform PLL */
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sys_info->freq_systembus /= 2;
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sys_info->freq_ddrbus *= (in_le32(&gur->rcwsr[0]) >>
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sys_info->freq_ddrbus *= (in_le32(&gur->rcwsr[0]) >>
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FSL_CHASSIS3_RCWSR0_MEM_PLL_RAT_SHIFT) &
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FSL_CHASSIS3_RCWSR0_MEM_PLL_RAT_SHIFT) &
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FSL_CHASSIS3_RCWSR0_MEM_PLL_RAT_MASK;
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FSL_CHASSIS3_RCWSR0_MEM_PLL_RAT_MASK;
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@ -102,10 +104,7 @@ void get_sys_info(struct sys_info *sys_info)
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offsetof(struct ccsr_clk_cluster_group,
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offsetof(struct ccsr_clk_cluster_group,
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pllngsr[i%3].gsr));
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pllngsr[i%3].gsr));
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ratio[i] = (in_le32(offset) >> 1) & 0x3f;
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ratio[i] = (in_le32(offset) >> 1) & 0x3f;
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if (ratio[i] > 4)
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freq_c_pll[i] = sysclk * ratio[i];
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freq_c_pll[i] = sysclk * ratio[i];
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else
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freq_c_pll[i] = sys_info->freq_systembus * ratio[i];
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}
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}
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for_each_cpu(i, cpu, cpu_numcores(), cpu_mask()) {
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for_each_cpu(i, cpu, cpu_numcores(), cpu_mask()) {
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