ARM: tegra: use apb_misc.h in more places

Tegra's "APB misc" register region contains various miscellaneous
registers and the Tegra pinmux registers. Some code that touches the
misc registers currently uses struct pmux_tri_ctlr, which is intended to
be a definition of pinmux registers, rather than struct apb_misc_pp_ctrl,
which is intended to be a definition of the miscellaneous registers.
Convert all such code to use struct apb_misc_pp_ctrl, since struct
pmux_tri_ctlr goes away in the next patch.

This requires adding a missing field definition to struct
apb_misc_pp_ctrl, and moving the header into a more common location.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
This commit is contained in:
Stephen Warren 2014-03-21 12:28:53 -06:00 committed by Tom Warren
parent 07bbd48b47
commit 19ed7b4ecf
5 changed files with 16 additions and 8 deletions

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@ -13,16 +13,18 @@
#include <asm/arch/clock.h> #include <asm/arch/clock.h>
#include <asm/arch/pinmux.h> #include <asm/arch/pinmux.h>
#include <asm/arch/tegra.h> #include <asm/arch/tegra.h>
#include <asm/arch-tegra/apb_misc.h>
#include <asm/arch-tegra/board.h> #include <asm/arch-tegra/board.h>
#include <asm/arch/spl.h> #include <asm/arch/spl.h>
#include "cpu.h" #include "cpu.h"
void spl_board_init(void) void spl_board_init(void)
{ {
struct pmux_tri_ctlr *pmt = (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE; struct apb_misc_pp_ctlr *apb_misc =
(struct apb_misc_pp_ctlr *)NV_PA_APB_MISC_BASE;
/* enable JTAG */ /* enable JTAG */
writel(0xC0, &pmt->pmt_cfg_ctl); writel(0xC0, &apb_misc->cfg_ctl);
board_init_uart_f(); board_init_uart_f();

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@ -8,7 +8,7 @@
#include <fdtdec.h> #include <fdtdec.h>
#include <asm/io.h> #include <asm/io.h>
#include <asm/arch-tegra/ap.h> #include <asm/arch-tegra/ap.h>
#include <asm/arch/apb_misc.h> #include <asm/arch-tegra/apb_misc.h>
#include <asm/arch/clock.h> #include <asm/arch/clock.h>
#include <asm/arch/emc.h> #include <asm/arch/emc.h>
#include <asm/arch/tegra.h> #include <asm/arch/tegra.h>

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@ -15,6 +15,7 @@
#include <asm/arch/sdram_param.h> #include <asm/arch/sdram_param.h>
#include <asm/arch/tegra.h> #include <asm/arch/tegra.h>
#include <asm/arch-tegra/ap.h> #include <asm/arch-tegra/ap.h>
#include <asm/arch-tegra/apb_misc.h>
#include <asm/arch-tegra/clk_rst.h> #include <asm/arch-tegra/clk_rst.h>
#include <asm/arch-tegra/pmc.h> #include <asm/arch-tegra/pmc.h>
#include <asm/arch-tegra/fuse.h> #include <asm/arch-tegra/fuse.h>
@ -122,7 +123,8 @@ int warmboot_save_sdram_params(void)
{ {
u32 ram_code; u32 ram_code;
struct sdram_params sdram; struct sdram_params sdram;
struct pmux_tri_ctlr *pmt = (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE; struct apb_misc_pp_ctlr *apb_misc =
(struct apb_misc_pp_ctlr *)NV_PA_APB_MISC_BASE;
struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE; struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
struct apb_misc_gp_ctlr *gp = struct apb_misc_gp_ctlr *gp =
(struct apb_misc_gp_ctlr *)NV_PA_APB_MISC_GP_BASE; (struct apb_misc_gp_ctlr *)NV_PA_APB_MISC_GP_BASE;
@ -135,8 +137,8 @@ int warmboot_save_sdram_params(void)
union fbio_spare_reg fbio_spare; union fbio_spare_reg fbio_spare;
/* get ram code that is used as index to array sdram_params in BCT */ /* get ram code that is used as index to array sdram_params in BCT */
ram_code = (readl(&pmt->pmt_strap_opt_a) >> ram_code = (readl(&apb_misc->strapping_opt_a) >>
STRAP_OPT_A_RAM_CODE_SHIFT) & 3; STRAP_OPT_A_RAM_CODE_SHIFT) & 3;
memcpy(&sdram, memcpy(&sdram,
(char *)((struct sdram_params *)SDRAM_PARAMS_BASE + ram_code), (char *)((struct sdram_params *)SDRAM_PARAMS_BASE + ram_code),
sizeof(sdram)); sizeof(sdram));

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@ -12,6 +12,7 @@
#include <asm/arch/pinmux.h> #include <asm/arch/pinmux.h>
#include <asm/arch/tegra.h> #include <asm/arch/tegra.h>
#include <asm/arch-tegra/ap.h> #include <asm/arch-tegra/ap.h>
#include <asm/arch-tegra/apb_misc.h>
#include <asm/arch-tegra/clk_rst.h> #include <asm/arch-tegra/clk_rst.h>
#include <asm/arch-tegra/pmc.h> #include <asm/arch-tegra/pmc.h>
#include <asm/arch-tegra/warmboot.h> #include <asm/arch-tegra/warmboot.h>
@ -21,7 +22,8 @@
void wb_start(void) void wb_start(void)
{ {
struct pmux_tri_ctlr *pmt = (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE; struct apb_misc_pp_ctlr *apb_misc =
(struct apb_misc_pp_ctlr *)NV_PA_APB_MISC_BASE;
struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE; struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
struct flow_ctlr *flow = (struct flow_ctlr *)NV_PA_FLOW_BASE; struct flow_ctlr *flow = (struct flow_ctlr *)NV_PA_FLOW_BASE;
struct clk_rst_ctlr *clkrst = struct clk_rst_ctlr *clkrst =
@ -33,7 +35,7 @@ void wb_start(void)
u32 reg; u32 reg;
/* enable JTAG & TBE */ /* enable JTAG & TBE */
writel(CONFIG_CTL_TBE | CONFIG_CTL_JTAG, &pmt->pmt_cfg_ctl); writel(CONFIG_CTL_TBE | CONFIG_CTL_JTAG, &apb_misc->cfg_ctl);
/* Are we running where we're supposed to be? */ /* Are we running where we're supposed to be? */
asm volatile ( asm volatile (

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@ -11,6 +11,8 @@
struct apb_misc_pp_ctlr { struct apb_misc_pp_ctlr {
u32 reserved0[2]; u32 reserved0[2];
u32 strapping_opt_a;/* 0x08: APB_MISC_PP_STRAPPING_OPT_A */ u32 strapping_opt_a;/* 0x08: APB_MISC_PP_STRAPPING_OPT_A */
u32 reserved1[6]; /* 0x0c .. 0x20 */
u32 cfg_ctl; /* 0x24 */
}; };
/* bit fields definitions for APB_MISC_PP_STRAPPING_OPT_A register */ /* bit fields definitions for APB_MISC_PP_STRAPPING_OPT_A register */