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ARM: tegra: use apb_misc.h in more places
Tegra's "APB misc" register region contains various miscellaneous registers and the Tegra pinmux registers. Some code that touches the misc registers currently uses struct pmux_tri_ctlr, which is intended to be a definition of pinmux registers, rather than struct apb_misc_pp_ctrl, which is intended to be a definition of the miscellaneous registers. Convert all such code to use struct apb_misc_pp_ctrl, since struct pmux_tri_ctlr goes away in the next patch. This requires adding a missing field definition to struct apb_misc_pp_ctrl, and moving the header into a more common location. Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
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07bbd48b47
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@ -13,16 +13,18 @@
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#include <asm/arch/clock.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/pinmux.h>
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#include <asm/arch/pinmux.h>
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#include <asm/arch/tegra.h>
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#include <asm/arch/tegra.h>
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#include <asm/arch-tegra/apb_misc.h>
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#include <asm/arch-tegra/board.h>
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#include <asm/arch-tegra/board.h>
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#include <asm/arch/spl.h>
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#include <asm/arch/spl.h>
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#include "cpu.h"
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#include "cpu.h"
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void spl_board_init(void)
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void spl_board_init(void)
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{
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{
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struct pmux_tri_ctlr *pmt = (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
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struct apb_misc_pp_ctlr *apb_misc =
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(struct apb_misc_pp_ctlr *)NV_PA_APB_MISC_BASE;
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/* enable JTAG */
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/* enable JTAG */
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writel(0xC0, &pmt->pmt_cfg_ctl);
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writel(0xC0, &apb_misc->cfg_ctl);
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board_init_uart_f();
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board_init_uart_f();
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@ -8,7 +8,7 @@
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#include <fdtdec.h>
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#include <fdtdec.h>
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#include <asm/io.h>
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#include <asm/io.h>
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#include <asm/arch-tegra/ap.h>
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#include <asm/arch-tegra/ap.h>
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#include <asm/arch/apb_misc.h>
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#include <asm/arch-tegra/apb_misc.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/emc.h>
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#include <asm/arch/emc.h>
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#include <asm/arch/tegra.h>
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#include <asm/arch/tegra.h>
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@ -15,6 +15,7 @@
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#include <asm/arch/sdram_param.h>
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#include <asm/arch/sdram_param.h>
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#include <asm/arch/tegra.h>
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#include <asm/arch/tegra.h>
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#include <asm/arch-tegra/ap.h>
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#include <asm/arch-tegra/ap.h>
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#include <asm/arch-tegra/apb_misc.h>
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#include <asm/arch-tegra/clk_rst.h>
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#include <asm/arch-tegra/clk_rst.h>
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#include <asm/arch-tegra/pmc.h>
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#include <asm/arch-tegra/pmc.h>
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#include <asm/arch-tegra/fuse.h>
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#include <asm/arch-tegra/fuse.h>
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@ -122,7 +123,8 @@ int warmboot_save_sdram_params(void)
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{
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{
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u32 ram_code;
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u32 ram_code;
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struct sdram_params sdram;
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struct sdram_params sdram;
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struct pmux_tri_ctlr *pmt = (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
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struct apb_misc_pp_ctlr *apb_misc =
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(struct apb_misc_pp_ctlr *)NV_PA_APB_MISC_BASE;
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struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
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struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
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struct apb_misc_gp_ctlr *gp =
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struct apb_misc_gp_ctlr *gp =
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(struct apb_misc_gp_ctlr *)NV_PA_APB_MISC_GP_BASE;
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(struct apb_misc_gp_ctlr *)NV_PA_APB_MISC_GP_BASE;
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@ -135,8 +137,8 @@ int warmboot_save_sdram_params(void)
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union fbio_spare_reg fbio_spare;
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union fbio_spare_reg fbio_spare;
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/* get ram code that is used as index to array sdram_params in BCT */
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/* get ram code that is used as index to array sdram_params in BCT */
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ram_code = (readl(&pmt->pmt_strap_opt_a) >>
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ram_code = (readl(&apb_misc->strapping_opt_a) >>
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STRAP_OPT_A_RAM_CODE_SHIFT) & 3;
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STRAP_OPT_A_RAM_CODE_SHIFT) & 3;
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memcpy(&sdram,
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memcpy(&sdram,
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(char *)((struct sdram_params *)SDRAM_PARAMS_BASE + ram_code),
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(char *)((struct sdram_params *)SDRAM_PARAMS_BASE + ram_code),
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sizeof(sdram));
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sizeof(sdram));
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@ -12,6 +12,7 @@
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#include <asm/arch/pinmux.h>
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#include <asm/arch/pinmux.h>
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#include <asm/arch/tegra.h>
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#include <asm/arch/tegra.h>
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#include <asm/arch-tegra/ap.h>
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#include <asm/arch-tegra/ap.h>
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#include <asm/arch-tegra/apb_misc.h>
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#include <asm/arch-tegra/clk_rst.h>
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#include <asm/arch-tegra/clk_rst.h>
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#include <asm/arch-tegra/pmc.h>
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#include <asm/arch-tegra/pmc.h>
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#include <asm/arch-tegra/warmboot.h>
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#include <asm/arch-tegra/warmboot.h>
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@ -21,7 +22,8 @@
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void wb_start(void)
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void wb_start(void)
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{
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{
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struct pmux_tri_ctlr *pmt = (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
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struct apb_misc_pp_ctlr *apb_misc =
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(struct apb_misc_pp_ctlr *)NV_PA_APB_MISC_BASE;
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struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
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struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
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struct flow_ctlr *flow = (struct flow_ctlr *)NV_PA_FLOW_BASE;
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struct flow_ctlr *flow = (struct flow_ctlr *)NV_PA_FLOW_BASE;
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struct clk_rst_ctlr *clkrst =
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struct clk_rst_ctlr *clkrst =
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@ -33,7 +35,7 @@ void wb_start(void)
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u32 reg;
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u32 reg;
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/* enable JTAG & TBE */
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/* enable JTAG & TBE */
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writel(CONFIG_CTL_TBE | CONFIG_CTL_JTAG, &pmt->pmt_cfg_ctl);
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writel(CONFIG_CTL_TBE | CONFIG_CTL_JTAG, &apb_misc->cfg_ctl);
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/* Are we running where we're supposed to be? */
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/* Are we running where we're supposed to be? */
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asm volatile (
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asm volatile (
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@ -11,6 +11,8 @@
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struct apb_misc_pp_ctlr {
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struct apb_misc_pp_ctlr {
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u32 reserved0[2];
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u32 reserved0[2];
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u32 strapping_opt_a;/* 0x08: APB_MISC_PP_STRAPPING_OPT_A */
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u32 strapping_opt_a;/* 0x08: APB_MISC_PP_STRAPPING_OPT_A */
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u32 reserved1[6]; /* 0x0c .. 0x20 */
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u32 cfg_ctl; /* 0x24 */
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};
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};
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/* bit fields definitions for APB_MISC_PP_STRAPPING_OPT_A register */
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/* bit fields definitions for APB_MISC_PP_STRAPPING_OPT_A register */
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