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Merge branch 'master' of git://git.denx.de/u-boot-spi

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This commit is contained in:
Tom Rini 2016-09-22 11:36:45 -04:00
commit 19d051a2b7
16 changed files with 188 additions and 208 deletions
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1
configs/mx6sxsabreauto_defconfig
View File

@ -23,6 +23,7 @@ CONFIG_CMD_EXT4=y
CONFIG_CMD_EXT4_WRITE=y CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y CONFIG_CMD_FS_GENERIC=y
CONFIG_FSL_QSPI=y
CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_BAR=y CONFIG_SPI_FLASH_BAR=y
CONFIG_SPI_FLASH_STMICRO=y CONFIG_SPI_FLASH_STMICRO=y

4
configs/mx6ul_14x14_evk_defconfig
View File

@ -32,4 +32,8 @@ CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y CONFIG_CMD_FS_GENERIC=y
CONFIG_USB=y CONFIG_USB=y
CONFIG_USB_STORAGE=y CONFIG_USB_STORAGE=y
CONFIG_FSL_QSPI=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_BAR=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_OF_LIBFDT=y CONFIG_OF_LIBFDT=y

4
configs/mx6ul_9x9_evk_defconfig
View File

@ -32,4 +32,8 @@ CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y CONFIG_CMD_FS_GENERIC=y
CONFIG_USB=y CONFIG_USB=y
CONFIG_USB_STORAGE=y CONFIG_USB_STORAGE=y
CONFIG_FSL_QSPI=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_BAR=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_OF_LIBFDT=y CONFIG_OF_LIBFDT=y

5
drivers/mtd/spi/sandbox.c
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@ -292,10 +292,7 @@ static int sandbox_sf_process_cmd(struct sandbox_spi_flash *sbsf, const u8 *rx,
sbsf->data->nr_sectors; sbsf->data->nr_sectors;
} else if (sbsf->cmd == CMD_ERASE_4K && (flags & SECT_4K)) { } else if (sbsf->cmd == CMD_ERASE_4K && (flags & SECT_4K)) {
sbsf->erase_size = 4 << 10; sbsf->erase_size = 4 << 10;
} else if (sbsf->cmd == CMD_ERASE_32K && (flags & SECT_32K)) { } else if (sbsf->cmd == CMD_ERASE_64K && !(flags & SECT_4K)) {
sbsf->erase_size = 32 << 10;
} else if (sbsf->cmd == CMD_ERASE_64K &&
!(flags & (SECT_4K | SECT_32K))) {
sbsf->erase_size = 64 << 10; sbsf->erase_size = 64 << 10;
} else { } else {
debug(" cmd unknown: %#x\n", sbsf->cmd); debug(" cmd unknown: %#x\n", sbsf->cmd);

41
drivers/mtd/spi/sf_internal.h
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@ -20,34 +20,6 @@ enum spi_dual_flash {
SF_DUAL_PARALLEL_FLASH = BIT(1), SF_DUAL_PARALLEL_FLASH = BIT(1),
}; };
/* Enum list - Full read commands */
enum spi_read_cmds {
ARRAY_SLOW = BIT(0),
ARRAY_FAST = BIT(1),
DUAL_OUTPUT_FAST = BIT(2),
QUAD_OUTPUT_FAST = BIT(3),
DUAL_IO_FAST = BIT(4),
QUAD_IO_FAST = BIT(5),
};
/* Normal - Extended - Full command set */
#define RD_NORM (ARRAY_SLOW | ARRAY_FAST)
#define RD_EXTN (RD_NORM | DUAL_OUTPUT_FAST | DUAL_IO_FAST)
#define RD_FULL (RD_EXTN | QUAD_OUTPUT_FAST | QUAD_IO_FAST)
/* sf param flags */
enum {
#ifndef CONFIG_SPI_FLASH_USE_4K_SECTORS
SECT_4K = 0,
#else
SECT_4K = BIT(0),
#endif
SECT_32K = BIT(1),
E_FSR = BIT(2),
SST_WR = BIT(3),
WR_QPP = BIT(4),
};
enum spi_nor_option_flags { enum spi_nor_option_flags {
SNOR_F_SST_WR = BIT(0), SNOR_F_SST_WR = BIT(0),
SNOR_F_USE_FSR = BIT(1), SNOR_F_USE_FSR = BIT(1),
@ -67,7 +39,6 @@ enum spi_nor_option_flags {
/* Erase commands */ /* Erase commands */
#define CMD_ERASE_4K 0x20 #define CMD_ERASE_4K 0x20
#define CMD_ERASE_32K 0x52
#define CMD_ERASE_CHIP 0xc7 #define CMD_ERASE_CHIP 0xc7
#define CMD_ERASE_64K 0xd8 #define CMD_ERASE_64K 0xd8
@ -141,7 +112,6 @@ int sst_write_bp(struct spi_flash *flash, u32 offset, size_t len,
* @sector_size: Isn't necessarily a sector size from vendor, * @sector_size: Isn't necessarily a sector size from vendor,
* the size listed here is what works with CMD_ERASE_64K * the size listed here is what works with CMD_ERASE_64K
* @nr_sectors: No.of sectors on this device * @nr_sectors: No.of sectors on this device
* @e_rd_cmd: Enum list for read commands
* @flags: Important param, for flash specific behaviour * @flags: Important param, for flash specific behaviour
*/ */
struct spi_flash_params { struct spi_flash_params {
@ -150,8 +120,17 @@ struct spi_flash_params {
u16 ext_jedec; u16 ext_jedec;
u32 sector_size; u32 sector_size;
u32 nr_sectors; u32 nr_sectors;
u8 e_rd_cmd;
u16 flags; u16 flags;
#define SECT_4K BIT(0)
#define E_FSR BIT(1)
#define SST_WR BIT(2)
#define WR_QPP BIT(3)
#define RD_QUAD BIT(4)
#define RD_DUAL BIT(5)
#define RD_QUADIO BIT(6)
#define RD_DUALIO BIT(7)
#define RD_FULL (RD_QUAD | RD_DUAL | RD_QUADIO | RD_DUALIO)
}; };
extern const struct spi_flash_params spi_flash_params_table[]; extern const struct spi_flash_params spi_flash_params_table[];

200
drivers/mtd/spi/sf_params.c
View File

@ -15,122 +15,122 @@
/* SPI/QSPI flash device params structure */ /* SPI/QSPI flash device params structure */
const struct spi_flash_params spi_flash_params_table[] = { const struct spi_flash_params spi_flash_params_table[] = {
#ifdef CONFIG_SPI_FLASH_ATMEL /* ATMEL */ #ifdef CONFIG_SPI_FLASH_ATMEL /* ATMEL */
{"AT45DB011D", 0x1f2200, 0x0, 64 * 1024, 4, RD_NORM, SECT_4K}, {"AT45DB011D", 0x1f2200, 0x0, 64 * 1024, 4, SECT_4K},
{"AT45DB021D", 0x1f2300, 0x0, 64 * 1024, 8, RD_NORM, SECT_4K}, {"AT45DB021D", 0x1f2300, 0x0, 64 * 1024, 8, SECT_4K},
{"AT45DB041D", 0x1f2400, 0x0, 64 * 1024, 8, RD_NORM, SECT_4K}, {"AT45DB041D", 0x1f2400, 0x0, 64 * 1024, 8, SECT_4K},
{"AT45DB081D", 0x1f2500, 0x0, 64 * 1024, 16, RD_NORM, SECT_4K}, {"AT45DB081D", 0x1f2500, 0x0, 64 * 1024, 16, SECT_4K},
{"AT45DB161D", 0x1f2600, 0x0, 64 * 1024, 32, RD_NORM, SECT_4K}, {"AT45DB161D", 0x1f2600, 0x0, 64 * 1024, 32, SECT_4K},
{"AT45DB321D", 0x1f2700, 0x0, 64 * 1024, 64, RD_NORM, SECT_4K}, {"AT45DB321D", 0x1f2700, 0x0, 64 * 1024, 64, SECT_4K},
{"AT45DB641D", 0x1f2800, 0x0, 64 * 1024, 128, RD_NORM, SECT_4K}, {"AT45DB641D", 0x1f2800, 0x0, 64 * 1024, 128, SECT_4K},
{"AT25DF321A", 0x1f4701, 0x0, 64 * 1024, 64, RD_NORM, SECT_4K}, {"AT25DF321A", 0x1f4701, 0x0, 64 * 1024, 64, SECT_4K},
{"AT25DF321", 0x1f4700, 0x0, 64 * 1024, 64, RD_NORM, SECT_4K}, {"AT25DF321", 0x1f4700, 0x0, 64 * 1024, 64, SECT_4K},
{"AT26DF081A", 0x1f4501, 0x0, 64 * 1024, 16, RD_NORM, SECT_4K}, {"AT26DF081A", 0x1f4501, 0x0, 64 * 1024, 16, SECT_4K},
#endif #endif
#ifdef CONFIG_SPI_FLASH_EON /* EON */ #ifdef CONFIG_SPI_FLASH_EON /* EON */
{"EN25Q32B", 0x1c3016, 0x0, 64 * 1024, 64, RD_NORM, 0}, {"EN25Q32B", 0x1c3016, 0x0, 64 * 1024, 64, 0},
{"EN25Q64", 0x1c3017, 0x0, 64 * 1024, 128, RD_NORM, SECT_4K}, {"EN25Q64", 0x1c3017, 0x0, 64 * 1024, 128, SECT_4K},
{"EN25Q128B", 0x1c3018, 0x0, 64 * 1024, 256, RD_NORM, 0}, {"EN25Q128B", 0x1c3018, 0x0, 64 * 1024, 256, 0},
{"EN25S64", 0x1c3817, 0x0, 64 * 1024, 128, RD_NORM, 0}, {"EN25S64", 0x1c3817, 0x0, 64 * 1024, 128, 0},
#endif #endif
#ifdef CONFIG_SPI_FLASH_GIGADEVICE /* GIGADEVICE */ #ifdef CONFIG_SPI_FLASH_GIGADEVICE /* GIGADEVICE */
{"GD25Q64B", 0xc84017, 0x0, 64 * 1024, 128, RD_NORM, SECT_4K}, {"GD25Q64B", 0xc84017, 0x0, 64 * 1024, 128, SECT_4K},
{"GD25LQ32", 0xc86016, 0x0, 64 * 1024, 64, RD_NORM, SECT_4K}, {"GD25LQ32", 0xc86016, 0x0, 64 * 1024, 64, SECT_4K},
#endif #endif
#ifdef CONFIG_SPI_FLASH_ISSI /* ISSI */ #ifdef CONFIG_SPI_FLASH_ISSI /* ISSI */
{"IS25LP032", 0x9d6016, 0x0, 64 * 1024, 64, RD_NORM, 0}, {"IS25LP032", 0x9d6016, 0x0, 64 * 1024, 64, 0},
{"IS25LP064", 0x9d6017, 0x0, 64 * 1024, 128, RD_NORM, 0}, {"IS25LP064", 0x9d6017, 0x0, 64 * 1024, 128, 0},
{"IS25LP128", 0x9d6018, 0x0, 64 * 1024, 256, RD_NORM, 0}, {"IS25LP128", 0x9d6018, 0x0, 64 * 1024, 256, 0},
#endif #endif
#ifdef CONFIG_SPI_FLASH_MACRONIX /* MACRONIX */ #ifdef CONFIG_SPI_FLASH_MACRONIX /* MACRONIX */
{"MX25L2006E", 0xc22012, 0x0, 64 * 1024, 4, RD_NORM, 0}, {"MX25L2006E", 0xc22012, 0x0, 64 * 1024, 4, 0},
{"MX25L4005", 0xc22013, 0x0, 64 * 1024, 8, RD_NORM, 0}, {"MX25L4005", 0xc22013, 0x0, 64 * 1024, 8, 0},
{"MX25L8005", 0xc22014, 0x0, 64 * 1024, 16, RD_NORM, 0}, {"MX25L8005", 0xc22014, 0x0, 64 * 1024, 16, 0},
{"MX25L1605D", 0xc22015, 0x0, 64 * 1024, 32, RD_NORM, 0}, {"MX25L1605D", 0xc22015, 0x0, 64 * 1024, 32, 0},
{"MX25L3205D", 0xc22016, 0x0, 64 * 1024, 64, RD_NORM, 0}, {"MX25L3205D", 0xc22016, 0x0, 64 * 1024, 64, 0},
{"MX25L6405D", 0xc22017, 0x0, 64 * 1024, 128, RD_NORM, 0}, {"MX25L6405D", 0xc22017, 0x0, 64 * 1024, 128, 0},
{"MX25L12805", 0xc22018, 0x0, 64 * 1024, 256, RD_FULL, WR_QPP}, {"MX25L12805", 0xc22018, 0x0, 64 * 1024, 256, RD_FULL | WR_QPP},
{"MX25L25635F", 0xc22019, 0x0, 64 * 1024, 512, RD_FULL, WR_QPP}, {"MX25L25635F", 0xc22019, 0x0, 64 * 1024, 512, RD_FULL | WR_QPP},
{"MX25L51235F", 0xc2201a, 0x0, 64 * 1024, 1024, RD_FULL, WR_QPP}, {"MX25L51235F", 0xc2201a, 0x0, 64 * 1024, 1024, RD_FULL | WR_QPP},
{"MX25L12855E", 0xc22618, 0x0, 64 * 1024, 256, RD_FULL, WR_QPP}, {"MX25L12855E", 0xc22618, 0x0, 64 * 1024, 256, RD_FULL | WR_QPP},
#endif #endif
#ifdef CONFIG_SPI_FLASH_SPANSION /* SPANSION */ #ifdef CONFIG_SPI_FLASH_SPANSION /* SPANSION */
{"S25FL008A", 0x010213, 0x0, 64 * 1024, 16, RD_NORM, 0}, {"S25FL008A", 0x010213, 0x0, 64 * 1024, 16, 0},
{"S25FL016A", 0x010214, 0x0, 64 * 1024, 32, RD_NORM, 0}, {"S25FL016A", 0x010214, 0x0, 64 * 1024, 32, 0},
{"S25FL032A", 0x010215, 0x0, 64 * 1024, 64, RD_NORM, 0}, {"S25FL032A", 0x010215, 0x0, 64 * 1024, 64, 0},
{"S25FL064A", 0x010216, 0x0, 64 * 1024, 128, RD_NORM, 0}, {"S25FL064A", 0x010216, 0x0, 64 * 1024, 128, 0},
{"S25FL116K", 0x014015, 0x0, 64 * 1024, 128, RD_NORM, 0}, {"S25FL116K", 0x014015, 0x0, 64 * 1024, 128, 0},
{"S25FL164K", 0x014017, 0x0140, 64 * 1024, 128, RD_NORM, 0}, {"S25FL164K", 0x014017, 0x0140, 64 * 1024, 128, 0},
{"S25FL128P_256K", 0x012018, 0x0300, 256 * 1024, 64, RD_FULL, WR_QPP}, {"S25FL128P_256K", 0x012018, 0x0300, 256 * 1024, 64, RD_FULL | WR_QPP},
{"S25FL128P_64K", 0x012018, 0x0301, 64 * 1024, 256, RD_FULL, WR_QPP}, {"S25FL128P_64K", 0x012018, 0x0301, 64 * 1024, 256, RD_FULL | WR_QPP},
{"S25FL032P", 0x010215, 0x4d00, 64 * 1024, 64, RD_FULL, WR_QPP}, {"S25FL032P", 0x010215, 0x4d00, 64 * 1024, 64, RD_FULL | WR_QPP},
{"S25FL064P", 0x010216, 0x4d00, 64 * 1024, 128, RD_FULL, WR_QPP}, {"S25FL064P", 0x010216, 0x4d00, 64 * 1024, 128, RD_FULL | WR_QPP},
{"S25FL128S_256K", 0x012018, 0x4d00, 256 * 1024, 64, RD_FULL, WR_QPP}, {"S25FL128S_256K", 0x012018, 0x4d00, 256 * 1024, 64, RD_FULL | WR_QPP},
{"S25FL128S_64K", 0x012018, 0x4d01, 64 * 1024, 256, RD_FULL, WR_QPP}, {"S25FL128S_64K", 0x012018, 0x4d01, 64 * 1024, 256, RD_FULL | WR_QPP},
{"S25FL256S_256K", 0x010219, 0x4d00, 256 * 1024, 128, RD_FULL, WR_QPP}, {"S25FL256S_256K", 0x010219, 0x4d00, 256 * 1024, 128, RD_FULL | WR_QPP},
{"S25FL256S_64K", 0x010219, 0x4d01, 64 * 1024, 512, RD_FULL, WR_QPP}, {"S25FL256S_64K", 0x010219, 0x4d01, 64 * 1024, 512, RD_FULL | WR_QPP},
{"S25FS512S", 0x010220, 0x4D00, 128 * 1024, 512, RD_FULL, WR_QPP}, {"S25FS512S", 0x010220, 0x4D00, 128 * 1024, 512, RD_FULL | WR_QPP},
{"S25FL512S_256K", 0x010220, 0x4d00, 256 * 1024, 256, RD_FULL, WR_QPP}, {"S25FL512S_256K", 0x010220, 0x4d00, 256 * 1024, 256, RD_FULL | WR_QPP},
{"S25FL512S_64K", 0x010220, 0x4d01, 64 * 1024, 1024, RD_FULL, WR_QPP}, {"S25FL512S_64K", 0x010220, 0x4d01, 64 * 1024, 1024, RD_FULL | WR_QPP},
{"S25FL512S_512K", 0x010220, 0x4f00, 256 * 1024, 256, RD_FULL, WR_QPP}, {"S25FL512S_512K", 0x010220, 0x4f00, 256 * 1024, 256, RD_FULL | WR_QPP},
#endif #endif
#ifdef CONFIG_SPI_FLASH_STMICRO /* STMICRO */ #ifdef CONFIG_SPI_FLASH_STMICRO /* STMICRO */
{"M25P10", 0x202011, 0x0, 32 * 1024, 4, RD_NORM, 0}, {"M25P10", 0x202011, 0x0, 32 * 1024, 4, 0},
{"M25P20", 0x202012, 0x0, 64 * 1024, 4, RD_NORM, 0}, {"M25P20", 0x202012, 0x0, 64 * 1024, 4, 0},
{"M25P40", 0x202013, 0x0, 64 * 1024, 8, RD_NORM, 0}, {"M25P40", 0x202013, 0x0, 64 * 1024, 8, 0},
{"M25P80", 0x202014, 0x0, 64 * 1024, 16, RD_NORM, 0}, {"M25P80", 0x202014, 0x0, 64 * 1024, 16, 0},
{"M25P16", 0x202015, 0x0, 64 * 1024, 32, RD_NORM, 0}, {"M25P16", 0x202015, 0x0, 64 * 1024, 32, 0},
{"M25PE16", 0x208015, 0x1000, 64 * 1024, 32, RD_NORM, 0}, {"M25PE16", 0x208015, 0x1000, 64 * 1024, 32, 0},
{"M25PX16", 0x207115, 0x1000, 64 * 1024, 32, RD_EXTN, 0}, {"M25PX16", 0x207115, 0x1000, 64 * 1024, 32, RD_QUAD | RD_DUAL},
{"M25P32", 0x202016, 0x0, 64 * 1024, 64, RD_NORM, 0}, {"M25P32", 0x202016, 0x0, 64 * 1024, 64, 0},
{"M25P64", 0x202017, 0x0, 64 * 1024, 128, RD_NORM, 0}, {"M25P64", 0x202017, 0x0, 64 * 1024, 128, 0},
{"M25P128", 0x202018, 0x0, 256 * 1024, 64, RD_NORM, 0}, {"M25P128", 0x202018, 0x0, 256 * 1024, 64, 0},
{"M25PX64", 0x207117, 0x0, 64 * 1024, 128, RD_NORM, SECT_4K}, {"M25PX64", 0x207117, 0x0, 64 * 1024, 128, SECT_4K},
{"N25Q016A", 0x20bb15, 0x0, 64 * 1024, 32, RD_NORM, SECT_4K}, {"N25Q016A", 0x20bb15, 0x0, 64 * 1024, 32, SECT_4K},
{"N25Q32", 0x20ba16, 0x0, 64 * 1024, 64, RD_FULL, WR_QPP | SECT_4K}, {"N25Q32", 0x20ba16, 0x0, 64 * 1024, 64, RD_FULL | WR_QPP | SECT_4K},
{"N25Q32A", 0x20bb16, 0x0, 64 * 1024, 64, RD_FULL, WR_QPP | SECT_4K}, {"N25Q32A", 0x20bb16, 0x0, 64 * 1024, 64, RD_FULL | WR_QPP | SECT_4K},
{"N25Q64", 0x20ba17, 0x0, 64 * 1024, 128, RD_FULL, WR_QPP | SECT_4K}, {"N25Q64", 0x20ba17, 0x0, 64 * 1024, 128, RD_FULL | WR_QPP | SECT_4K},
{"N25Q64A", 0x20bb17, 0x0, 64 * 1024, 128, RD_FULL, WR_QPP | SECT_4K}, {"N25Q64A", 0x20bb17, 0x0, 64 * 1024, 128, RD_FULL | WR_QPP | SECT_4K},
{"N25Q128", 0x20ba18, 0x0, 64 * 1024, 256, RD_FULL, WR_QPP}, {"N25Q128", 0x20ba18, 0x0, 64 * 1024, 256, RD_FULL | WR_QPP},
{"N25Q128A", 0x20bb18, 0x0, 64 * 1024, 256, RD_FULL, WR_QPP}, {"N25Q128A", 0x20bb18, 0x0, 64 * 1024, 256, RD_FULL | WR_QPP},
{"N25Q256", 0x20ba19, 0x0, 64 * 1024, 512, RD_FULL, WR_QPP | SECT_4K}, {"N25Q256", 0x20ba19, 0x0, 64 * 1024, 512, RD_FULL | WR_QPP | SECT_4K},
{"N25Q256A", 0x20bb19, 0x0, 64 * 1024, 512, RD_FULL, WR_QPP | SECT_4K}, {"N25Q256A", 0x20bb19, 0x0, 64 * 1024, 512, RD_FULL | WR_QPP | SECT_4K},
{"N25Q512", 0x20ba20, 0x0, 64 * 1024, 1024, RD_FULL, WR_QPP | E_FSR | SECT_4K}, {"N25Q512", 0x20ba20, 0x0, 64 * 1024, 1024, RD_FULL | WR_QPP | E_FSR | SECT_4K},
{"N25Q512A", 0x20bb20, 0x0, 64 * 1024, 1024, RD_FULL, WR_QPP | E_FSR | SECT_4K}, {"N25Q512A", 0x20bb20, 0x0, 64 * 1024, 1024, RD_FULL | WR_QPP | E_FSR | SECT_4K},
{"N25Q1024", 0x20ba21, 0x0, 64 * 1024, 2048, RD_FULL, WR_QPP | E_FSR | SECT_4K}, {"N25Q1024", 0x20ba21, 0x0, 64 * 1024, 2048, RD_FULL | WR_QPP | E_FSR | SECT_4K},
{"N25Q1024A", 0x20bb21, 0x0, 64 * 1024, 2048, RD_FULL, WR_QPP | E_FSR | SECT_4K}, {"N25Q1024A", 0x20bb21, 0x0, 64 * 1024, 2048, RD_FULL | WR_QPP | E_FSR | SECT_4K},
#endif #endif
#ifdef CONFIG_SPI_FLASH_SST /* SST */ #ifdef CONFIG_SPI_FLASH_SST /* SST */
{"SST25VF040B", 0xbf258d, 0x0, 64 * 1024, 8, RD_NORM, SECT_4K | SST_WR}, {"SST25VF040B", 0xbf258d, 0x0, 64 * 1024, 8, SECT_4K | SST_WR},
{"SST25VF080B", 0xbf258e, 0x0, 64 * 1024, 16, RD_NORM, SECT_4K | SST_WR}, {"SST25VF080B", 0xbf258e, 0x0, 64 * 1024, 16, SECT_4K | SST_WR},
{"SST25VF016B", 0xbf2541, 0x0, 64 * 1024, 32, RD_NORM, SECT_4K | SST_WR}, {"SST25VF016B", 0xbf2541, 0x0, 64 * 1024, 32, SECT_4K | SST_WR},
{"SST25VF032B", 0xbf254a, 0x0, 64 * 1024, 64, RD_NORM, SECT_4K | SST_WR}, {"SST25VF032B", 0xbf254a, 0x0, 64 * 1024, 64, SECT_4K | SST_WR},
{"SST25VF064C", 0xbf254b, 0x0, 64 * 1024, 128, RD_NORM, SECT_4K}, {"SST25VF064C", 0xbf254b, 0x0, 64 * 1024, 128, SECT_4K},
{"SST25WF512", 0xbf2501, 0x0, 64 * 1024, 1, RD_NORM, SECT_4K | SST_WR}, {"SST25WF512", 0xbf2501, 0x0, 64 * 1024, 1, SECT_4K | SST_WR},
{"SST25WF010", 0xbf2502, 0x0, 64 * 1024, 2, RD_NORM, SECT_4K | SST_WR}, {"SST25WF010", 0xbf2502, 0x0, 64 * 1024, 2, SECT_4K | SST_WR},
{"SST25WF020", 0xbf2503, 0x0, 64 * 1024, 4, RD_NORM, SECT_4K | SST_WR}, {"SST25WF020", 0xbf2503, 0x0, 64 * 1024, 4, SECT_4K | SST_WR},
{"SST25WF040", 0xbf2504, 0x0, 64 * 1024, 8, RD_NORM, SECT_4K | SST_WR}, {"SST25WF040", 0xbf2504, 0x0, 64 * 1024, 8, SECT_4K | SST_WR},
{"SST25WF040B", 0x621613, 0x0, 64 * 1024, 8, RD_NORM, SECT_4K}, {"SST25WF040B", 0x621613, 0x0, 64 * 1024, 8, SECT_4K},
{"SST25WF080", 0xbf2505, 0x0, 64 * 1024, 16, RD_NORM, SECT_4K | SST_WR}, {"SST25WF080", 0xbf2505, 0x0, 64 * 1024, 16, SECT_4K | SST_WR},
#endif #endif
#ifdef CONFIG_SPI_FLASH_WINBOND /* WINBOND */ #ifdef CONFIG_SPI_FLASH_WINBOND /* WINBOND */
{"W25P80", 0xef2014, 0x0, 64 * 1024, 16, RD_NORM, 0}, {"W25P80", 0xef2014, 0x0, 64 * 1024, 16, 0},
{"W25P16", 0xef2015, 0x0, 64 * 1024, 32, RD_NORM, 0}, {"W25P16", 0xef2015, 0x0, 64 * 1024, 32, 0},
{"W25P32", 0xef2016, 0x0, 64 * 1024, 64, RD_NORM, 0}, {"W25P32", 0xef2016, 0x0, 64 * 1024, 64, 0},
{"W25X40", 0xef3013, 0x0, 64 * 1024, 8, RD_NORM, SECT_4K}, {"W25X40", 0xef3013, 0x0, 64 * 1024, 8, SECT_4K},
{"W25X16", 0xef3015, 0x0, 64 * 1024, 32, RD_NORM, SECT_4K}, {"W25X16", 0xef3015, 0x0, 64 * 1024, 32, SECT_4K},
{"W25X32", 0xef3016, 0x0, 64 * 1024, 64, RD_NORM, SECT_4K}, {"W25X32", 0xef3016, 0x0, 64 * 1024, 64, SECT_4K},
{"W25X64", 0xef3017, 0x0, 64 * 1024, 128, RD_NORM, SECT_4K}, {"W25X64", 0xef3017, 0x0, 64 * 1024, 128, SECT_4K},
{"W25Q80BL", 0xef4014, 0x0, 64 * 1024, 16, RD_FULL, WR_QPP | SECT_4K}, {"W25Q80BL", 0xef4014, 0x0, 64 * 1024, 16, RD_FULL | WR_QPP | SECT_4K},
{"W25Q16CL", 0xef4015, 0x0, 64 * 1024, 32, RD_FULL, WR_QPP | SECT_4K}, {"W25Q16CL", 0xef4015, 0x0, 64 * 1024, 32, RD_FULL | WR_QPP | SECT_4K},
{"W25Q32BV", 0xef4016, 0x0, 64 * 1024, 64, RD_FULL, WR_QPP | SECT_4K}, {"W25Q32BV", 0xef4016, 0x0, 64 * 1024, 64, RD_FULL | WR_QPP | SECT_4K},
{"W25Q64CV", 0xef4017, 0x0, 64 * 1024, 128, RD_FULL, WR_QPP | SECT_4K}, {"W25Q64CV", 0xef4017, 0x0, 64 * 1024, 128, RD_FULL | WR_QPP | SECT_4K},
{"W25Q128BV", 0xef4018, 0x0, 64 * 1024, 256, RD_FULL, WR_QPP | SECT_4K}, {"W25Q128BV", 0xef4018, 0x0, 64 * 1024, 256, RD_FULL | WR_QPP | SECT_4K},
{"W25Q256", 0xef4019, 0x0, 64 * 1024, 512, RD_FULL, WR_QPP | SECT_4K}, {"W25Q256", 0xef4019, 0x0, 64 * 1024, 512, RD_FULL | WR_QPP | SECT_4K},
{"W25Q80BW", 0xef5014, 0x0, 64 * 1024, 16, RD_FULL, WR_QPP | SECT_4K}, {"W25Q80BW", 0xef5014, 0x0, 64 * 1024, 16, RD_FULL | WR_QPP | SECT_4K},
{"W25Q16DW", 0xef6015, 0x0, 64 * 1024, 32, RD_FULL, WR_QPP | SECT_4K}, {"W25Q16DW", 0xef6015, 0x0, 64 * 1024, 32, RD_FULL | WR_QPP | SECT_4K},
{"W25Q32DW", 0xef6016, 0x0, 64 * 1024, 64, RD_FULL, WR_QPP | SECT_4K}, {"W25Q32DW", 0xef6016, 0x0, 64 * 1024, 64, RD_FULL | WR_QPP | SECT_4K},
{"W25Q64DW", 0xef6017, 0x0, 64 * 1024, 128, RD_FULL, WR_QPP | SECT_4K}, {"W25Q64DW", 0xef6017, 0x0, 64 * 1024, 128, RD_FULL | WR_QPP | SECT_4K},
{"W25Q128FW", 0xef6018, 0x0, 64 * 1024, 256, RD_FULL, WR_QPP | SECT_4K}, {"W25Q128FW", 0xef6018, 0x0, 64 * 1024, 256, RD_FULL | WR_QPP | SECT_4K},
#endif #endif
{}, /* Empty entry to terminate the list */ {}, /* Empty entry to terminate the list */
/* /*

36
drivers/mtd/spi/spi_flash.c
View File

@ -1013,15 +1013,8 @@ int spi_flash_scan(struct spi_flash *flash)
struct spi_slave *spi = flash->spi; struct spi_slave *spi = flash->spi;
const struct spi_flash_params *params; const struct spi_flash_params *params;
u16 jedec, ext_jedec; u16 jedec, ext_jedec;
u8 cmd, idcode[5]; u8 idcode[5];
int ret; int ret;
static u8 spi_read_cmds_array[] = {
CMD_READ_ARRAY_SLOW,
CMD_READ_ARRAY_FAST,
CMD_READ_DUAL_OUTPUT_FAST,
CMD_READ_QUAD_OUTPUT_FAST,
CMD_READ_DUAL_IO_FAST,
CMD_READ_QUAD_IO_FAST };
/* Read the ID codes */ /* Read the ID codes */
ret = spi_flash_cmd(spi, CMD_READ_ID, idcode, sizeof(idcode)); ret = spi_flash_cmd(spi, CMD_READ_ID, idcode, sizeof(idcode));
@ -1162,14 +1155,14 @@ int spi_flash_scan(struct spi_flash *flash)
flash->size <<= 1; flash->size <<= 1;
#endif #endif
#ifdef CONFIG_SPI_FLASH_USE_4K_SECTORS
/* Compute erase sector and command */ /* Compute erase sector and command */
if (params->flags & SECT_4K) { if (params->flags & SECT_4K) {
flash->erase_cmd = CMD_ERASE_4K; flash->erase_cmd = CMD_ERASE_4K;
flash->erase_size = 4096 << flash->shift; flash->erase_size = 4096 << flash->shift;
} else if (params->flags & SECT_32K) { } else
flash->erase_cmd = CMD_ERASE_32K; #endif
flash->erase_size = 32768 << flash->shift; {
} else {
flash->erase_cmd = CMD_ERASE_64K; flash->erase_cmd = CMD_ERASE_64K;
flash->erase_size = flash->sector_size; flash->erase_size = flash->sector_size;
} }
@ -1177,17 +1170,16 @@ int spi_flash_scan(struct spi_flash *flash)
/* Now erase size becomes valid sector size */ /* Now erase size becomes valid sector size */
flash->sector_size = flash->erase_size; flash->sector_size = flash->erase_size;
/* Look for the fastest read cmd */ /* Look for read commands */
cmd = fls(params->e_rd_cmd & spi->mode_rx); flash->read_cmd = CMD_READ_ARRAY_FAST;
if (cmd) { if (spi->mode & SPI_RX_SLOW)
cmd = spi_read_cmds_array[cmd - 1]; flash->read_cmd = CMD_READ_ARRAY_SLOW;
flash->read_cmd = cmd; else if (spi->mode & SPI_RX_QUAD && params->flags & RD_QUAD)
} else { flash->read_cmd = CMD_READ_QUAD_OUTPUT_FAST;
/* Go for default supported read cmd */ else if (spi->mode & SPI_RX_DUAL && params->flags & RD_DUAL)
flash->read_cmd = CMD_READ_ARRAY_FAST; flash->read_cmd = CMD_READ_DUAL_OUTPUT_FAST;
}
/* Not require to look for fastest only two write cmds yet */ /* Look for write commands */
if (params->flags & WR_QPP && spi->mode & SPI_TX_QUAD) if (params->flags & WR_QPP && spi->mode & SPI_TX_QUAD)
flash->write_cmd = CMD_QUAD_PAGE_PROGRAM; flash->write_cmd = CMD_QUAD_PAGE_PROGRAM;
else else

14
drivers/spi/Kconfig
View File

@ -61,13 +61,6 @@ config FSL_DSPI
this Freescale DSPI IP core. LS102xA and Colibri VF50/VF61 platforms this Freescale DSPI IP core. LS102xA and Colibri VF50/VF61 platforms
use this driver. use this driver.
config FSL_QSPI
bool "Freescale QSPI driver"
help
Enable the Freescale Quad-SPI (QSPI) driver. This driver can be
used to access the SPI NOR flash on platforms embedding this
Freescale IP core.
config ICH_SPI config ICH_SPI
bool "Intel ICH SPI driver" bool "Intel ICH SPI driver"
help help
@ -188,6 +181,13 @@ config FSL_ESPI
access the SPI interface and SPI NOR flash on platforms embedding access the SPI interface and SPI NOR flash on platforms embedding
this Freescale eSPI IP core. this Freescale eSPI IP core.
config FSL_QSPI
bool "Freescale QSPI driver"
help
Enable the Freescale Quad-SPI (QSPI) driver. This driver can be
used to access the SPI NOR flash on platforms embedding this
Freescale IP core.
config TI_QSPI config TI_QSPI
bool "TI QSPI driver" bool "TI QSPI driver"
help help

2
drivers/spi/cadence_qspi.c
View File

@ -251,7 +251,7 @@ static int cadence_spi_xfer(struct udevice *dev, unsigned int bitlen,
break; break;
case CQSPI_INDIRECT_READ: case CQSPI_INDIRECT_READ:
err = cadence_qspi_apb_indirect_read_setup(plat, err = cadence_qspi_apb_indirect_read_setup(plat,
priv->cmd_len, dm_plat->mode_rx, cmd_buf); priv->cmd_len, dm_plat->mode, cmd_buf);
if (!err) { if (!err) {
err = cadence_qspi_apb_indirect_read_execute err = cadence_qspi_apb_indirect_read_execute
(plat, data_bytes, din); (plat, data_bytes, din);

6
drivers/spi/ich.c
View File

@ -649,10 +649,8 @@ static int ich_spi_child_pre_probe(struct udevice *dev)
* ICH 7 SPI controller only supports array read command * ICH 7 SPI controller only supports array read command
* and byte program command for SST flash * and byte program command for SST flash
*/ */
if (plat->ich_version == ICHV_7) { if (plat->ich_version == ICHV_7)
slave->mode_rx = SPI_RX_SLOW; slave->mode = SPI_RX_SLOW | SPI_TX_BYTE;
slave->mode = SPI_TX_BYTE;
}
return 0; return 0;
} }

11
drivers/spi/spi-uclass.c
View File

@ -164,7 +164,6 @@ static int spi_child_pre_probe(struct udevice *dev)
slave->max_hz = plat->max_hz; slave->max_hz = plat->max_hz;
slave->mode = plat->mode; slave->mode = plat->mode;
slave->mode_rx = plat->mode_rx;
slave->wordlen = SPI_DEFAULT_WORDLEN; slave->wordlen = SPI_DEFAULT_WORDLEN;
return 0; return 0;
@ -381,7 +380,7 @@ void spi_free_slave(struct spi_slave *slave)
int spi_slave_ofdata_to_platdata(const void *blob, int node, int spi_slave_ofdata_to_platdata(const void *blob, int node,
struct dm_spi_slave_platdata *plat) struct dm_spi_slave_platdata *plat)
{ {
int mode = 0, mode_rx = 0; int mode = 0;
int value; int value;
plat->cs = fdtdec_get_int(blob, node, "reg", -1); plat->cs = fdtdec_get_int(blob, node, "reg", -1);
@ -413,24 +412,22 @@ int spi_slave_ofdata_to_platdata(const void *blob, int node,
break; break;
} }
plat->mode = mode;
value = fdtdec_get_uint(blob, node, "spi-rx-bus-width", 1); value = fdtdec_get_uint(blob, node, "spi-rx-bus-width", 1);
switch (value) { switch (value) {
case 1: case 1:
break; break;
case 2: case 2:
mode_rx |= SPI_RX_DUAL; mode |= SPI_RX_DUAL;
break; break;
case 4: case 4:
mode_rx |= SPI_RX_QUAD; mode |= SPI_RX_QUAD;
break; break;
default: default:
error("spi-rx-bus-width %d not supported\n", value); error("spi-rx-bus-width %d not supported\n", value);
break; break;
} }
plat->mode_rx = mode_rx; plat->mode = mode;
return 0; return 0;
} }

52
drivers/spi/ti_qspi.c
View File

@ -23,6 +23,9 @@ DECLARE_GLOBAL_DATA_PTR;
#define QSPI_TIMEOUT 2000000 #define QSPI_TIMEOUT 2000000
#define QSPI_FCLK 192000000 #define QSPI_FCLK 192000000
#define QSPI_DRA7XX_FCLK 76800000 #define QSPI_DRA7XX_FCLK 76800000
#define QSPI_WLEN_MAX_BITS 128
#define QSPI_WLEN_MAX_BYTES (QSPI_WLEN_MAX_BITS >> 3)
#define QSPI_WLEN_MASK QSPI_WLEN(QSPI_WLEN_MAX_BITS)
/* clock control */ /* clock control */
#define QSPI_CLK_EN BIT(31) #define QSPI_CLK_EN BIT(31)
#define QSPI_CLK_DIV_MAX 0xffff #define QSPI_CLK_DIV_MAX 0xffff
@ -223,20 +226,34 @@ static int __ti_qspi_xfer(struct ti_qspi_priv *priv, unsigned int bitlen,
priv->cmd |= QSPI_3_PIN; priv->cmd |= QSPI_3_PIN;
priv->cmd |= 0xfff; priv->cmd |= 0xfff;
/* FIXME: This delay is required for successfull while (words) {
* completion of read/write/erase. Once its root u8 xfer_len = 0;
* caused, it will be remove from the driver.
*/
#ifdef CONFIG_AM43XX
udelay(100);
#endif
while (words--) {
if (txp) { if (txp) {
debug("tx cmd %08x dc %08x data %02x\n", u32 cmd = priv->cmd;
priv->cmd | QSPI_WR_SNGL, priv->dc, *txp);
writel(*txp++, &priv->base->data); if (words >= QSPI_WLEN_MAX_BYTES) {
writel(priv->cmd | QSPI_WR_SNGL, u32 *txbuf = (u32 *)txp;
&priv->base->cmd); u32 data;
data = cpu_to_be32(*txbuf++);
writel(data, &priv->base->data3);
data = cpu_to_be32(*txbuf++);
writel(data, &priv->base->data2);
data = cpu_to_be32(*txbuf++);
writel(data, &priv->base->data1);
data = cpu_to_be32(*txbuf++);
writel(data, &priv->base->data);
cmd &= ~QSPI_WLEN_MASK;
cmd |= QSPI_WLEN(QSPI_WLEN_MAX_BITS);
xfer_len = QSPI_WLEN_MAX_BYTES;
} else {
writeb(*txp, &priv->base->data);
xfer_len = 1;
}
debug("tx cmd %08x dc %08x\n",
cmd | QSPI_WR_SNGL, priv->dc);
writel(cmd | QSPI_WR_SNGL, &priv->base->cmd);
status = readl(&priv->base->status); status = readl(&priv->base->status);
timeout = QSPI_TIMEOUT; timeout = QSPI_TIMEOUT;
while ((status & QSPI_WC_BUSY) != QSPI_XFER_DONE) { while ((status & QSPI_WC_BUSY) != QSPI_XFER_DONE) {
@ -246,6 +263,7 @@ static int __ti_qspi_xfer(struct ti_qspi_priv *priv, unsigned int bitlen,
} }
status = readl(&priv->base->status); status = readl(&priv->base->status);
} }
txp += xfer_len;
debug("tx done, status %08x\n", status); debug("tx done, status %08x\n", status);
} }
if (rxp) { if (rxp) {
@ -262,9 +280,11 @@ static int __ti_qspi_xfer(struct ti_qspi_priv *priv, unsigned int bitlen,
status = readl(&priv->base->status); status = readl(&priv->base->status);
} }
*rxp++ = readl(&priv->base->data); *rxp++ = readl(&priv->base->data);
xfer_len = 1;
debug("rx done, status %08x, read %02x\n", debug("rx done, status %08x, read %02x\n",
status, *(rxp-1)); status, *(rxp-1));
} }
words -= xfer_len;
} }
/* Terminate frame */ /* Terminate frame */
@ -336,7 +356,7 @@ static void ti_spi_setup_spi_register(struct ti_qspi_priv *priv)
QSPI_SETUP0_NUM_D_BYTES_8_BITS | QSPI_SETUP0_NUM_D_BYTES_8_BITS |
QSPI_SETUP0_READ_QUAD | QSPI_CMD_WRITE | QSPI_SETUP0_READ_QUAD | QSPI_CMD_WRITE |
QSPI_NUM_DUMMY_BITS); QSPI_NUM_DUMMY_BITS);
slave->mode_rx = SPI_RX_QUAD; slave->mode |= SPI_RX_QUAD;
#else #else
memval |= QSPI_CMD_READ | QSPI_SETUP0_NUM_A_BYTES | memval |= QSPI_CMD_READ | QSPI_SETUP0_NUM_A_BYTES |
QSPI_SETUP0_NUM_D_BYTES_NO_BITS | QSPI_SETUP0_NUM_D_BYTES_NO_BITS |
@ -422,7 +442,7 @@ static void __ti_qspi_setup_memorymap(struct ti_qspi_priv *priv,
bool enable) bool enable)
{ {
u32 memval; u32 memval;
u32 mode = slave->mode_rx & (SPI_RX_QUAD | SPI_RX_DUAL); u32 mode = slave->mode & (SPI_RX_QUAD | SPI_RX_DUAL);
if (!enable) { if (!enable) {
writel(0, &priv->base->setup0); writel(0, &priv->base->setup0);
@ -436,7 +456,7 @@ static void __ti_qspi_setup_memorymap(struct ti_qspi_priv *priv,
memval |= QSPI_CMD_READ_QUAD; memval |= QSPI_CMD_READ_QUAD;
memval |= QSPI_SETUP0_NUM_D_BYTES_8_BITS; memval |= QSPI_SETUP0_NUM_D_BYTES_8_BITS;
memval |= QSPI_SETUP0_READ_QUAD; memval |= QSPI_SETUP0_READ_QUAD;
slave->mode_rx = SPI_RX_QUAD; slave->mode |= SPI_RX_QUAD;
break; break;
case SPI_RX_DUAL: case SPI_RX_DUAL:
memval |= QSPI_CMD_READ_DUAL; memval |= QSPI_CMD_READ_DUAL;

2
drivers/spi/zynq_spi.c
View File

@ -233,7 +233,7 @@ static int zynq_spi_xfer(struct udevice *dev, unsigned int bitlen,
/* Read the data from RX FIFO */ /* Read the data from RX FIFO */
status = readl(&regs->isr); status = readl(&regs->isr);
while (status & ZYNQ_SPI_IXR_RXNEMPTY_MASK) { while ((status & ZYNQ_SPI_IXR_RXNEMPTY_MASK) && rx_len) {
buf = readl(&regs->rxdr); buf = readl(&regs->rxdr);
if (rx_buf) if (rx_buf)
*rx_buf++ = buf; *rx_buf++ = buf;

1
include/configs/mx6sxsabreauto.h
View File

@ -173,7 +173,6 @@
#define CONFIG_IMX_THERMAL #define CONFIG_IMX_THERMAL
#define CONFIG_FSL_QSPI
#ifdef CONFIG_FSL_QSPI #ifdef CONFIG_FSL_QSPI
#define CONFIG_SYS_FSL_QSPI_AHB #define CONFIG_SYS_FSL_QSPI_AHB
#define CONFIG_SF_DEFAULT_BUS 0 #define CONFIG_SF_DEFAULT_BUS 0

4
include/configs/mx6ul_14x14_evk.h
View File

@ -186,15 +186,11 @@
#ifndef CONFIG_SYS_DCACHE_OFF #ifndef CONFIG_SYS_DCACHE_OFF
#endif #endif
#define CONFIG_FSL_QSPI
#ifdef CONFIG_FSL_QSPI #ifdef CONFIG_FSL_QSPI
#define CONFIG_SPI_FLASH
#define CONFIG_SPI_FLASH_BAR
#define CONFIG_SF_DEFAULT_BUS 0 #define CONFIG_SF_DEFAULT_BUS 0
#define CONFIG_SF_DEFAULT_CS 0 #define CONFIG_SF_DEFAULT_CS 0
#define CONFIG_SF_DEFAULT_SPEED 40000000 #define CONFIG_SF_DEFAULT_SPEED 40000000
#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 #define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
#define CONFIG_SPI_FLASH_STMICRO
#define FSL_QSPI_FLASH_NUM 1 #define FSL_QSPI_FLASH_NUM 1
#define FSL_QSPI_FLASH_SIZE SZ_32M #define FSL_QSPI_FLASH_SIZE SZ_32M
#endif #endif

13
include/spi.h
View File

@ -26,12 +26,9 @@
#define SPI_TX_BYTE BIT(8) /* transmit with 1 wire byte */ #define SPI_TX_BYTE BIT(8) /* transmit with 1 wire byte */
#define SPI_TX_DUAL BIT(9) /* transmit with 2 wires */ #define SPI_TX_DUAL BIT(9) /* transmit with 2 wires */
#define SPI_TX_QUAD BIT(10) /* transmit with 4 wires */ #define SPI_TX_QUAD BIT(10) /* transmit with 4 wires */
#define SPI_RX_SLOW BIT(11) /* receive with 1 wire slow */
/* SPI mode_rx flags */ #define SPI_RX_DUAL BIT(12) /* receive with 2 wires */
#define SPI_RX_SLOW BIT(0) /* receive with 1 wire slow */ #define SPI_RX_QUAD BIT(13) /* receive with 4 wires */
#define SPI_RX_FAST BIT(1) /* receive with 1 wire fast */
#define SPI_RX_DUAL BIT(2) /* receive with 2 wires */
#define SPI_RX_QUAD BIT(3) /* receive with 4 wires */
/* SPI bus connection options - see enum spi_dual_flash */ /* SPI bus connection options - see enum spi_dual_flash */
#define SPI_CONN_DUAL_SHARED (1 << 0) #define SPI_CONN_DUAL_SHARED (1 << 0)
@ -61,13 +58,11 @@ struct dm_spi_bus {
* @cs: Chip select number (0..n-1) * @cs: Chip select number (0..n-1)
* @max_hz: Maximum bus speed that this slave can tolerate * @max_hz: Maximum bus speed that this slave can tolerate
* @mode: SPI mode to use for this device (see SPI mode flags) * @mode: SPI mode to use for this device (see SPI mode flags)
* @mode_rx: SPI RX mode to use for this slave (see SPI mode_rx flags)
*/ */
struct dm_spi_slave_platdata { struct dm_spi_slave_platdata {
unsigned int cs; unsigned int cs;
uint max_hz; uint max_hz;
uint mode; uint mode;
u8 mode_rx;
}; };
#endif /* CONFIG_DM_SPI */ #endif /* CONFIG_DM_SPI */
@ -94,7 +89,6 @@ struct dm_spi_slave_platdata {
* bus (bus->seq) so does not need to be stored * bus (bus->seq) so does not need to be stored
* @cs: ID of the chip select connected to the slave. * @cs: ID of the chip select connected to the slave.
* @mode: SPI mode to use for this slave (see SPI mode flags) * @mode: SPI mode to use for this slave (see SPI mode flags)
* @mode_rx: SPI RX mode to use for this slave (see SPI mode_rx flags)
* @wordlen: Size of SPI word in number of bits * @wordlen: Size of SPI word in number of bits
* @max_write_size: If non-zero, the maximum number of bytes which can * @max_write_size: If non-zero, the maximum number of bytes which can
* be written at once, excluding command bytes. * be written at once, excluding command bytes.
@ -112,7 +106,6 @@ struct spi_slave {
unsigned int cs; unsigned int cs;
#endif #endif
uint mode; uint mode;
u8 mode_rx;
unsigned int wordlen; unsigned int wordlen;
unsigned int max_write_size; unsigned int max_write_size;
void *memory_map; void *memory_map;