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https://github.com/brain-hackers/u-boot-brain
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ddr: altera: Clean up sdr_*_phase() part 5
Pull out the loop for eaching working/non-working DQS enable phase into a separate function, as this is mostly common code between. Clean up sdr_working_phase() and sdr_nonworking_phase() while switching these two functions to the common sdr_find_phase(). Signed-off-by: Marek Vasut <marex@denx.de>
This commit is contained in:
Marek Vasut
parent
38ed692238
commit
192d6f9fa3
@ -1332,45 +1332,78 @@ static int find_vfifo_read(uint32_t grp, uint32_t *bit_chk)
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}
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}
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/**
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* sdr_find_phase() - Find DQS enable phase
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* @working: If 1, look for working phase, if 0, look for non-working phase
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* @grp: Read/Write group
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* @v: VFIFO value
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* @work: Working window position
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* @i: Iterator
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* @p: DQS Phase Iterator
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* @max_working_cnt: Counter
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*
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* Find working or non-working DQS enable phase setting.
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*/
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static int sdr_find_phase(int working, const u32 grp, u32 *v, u32 *work,
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u32 *i, u32 *p, u32 *max_working_cnt)
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{
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u32 ret, bit_chk;
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const u32 end = VFIFO_SIZE + (working ? 0 : 1);
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for (; *i < end; (*i)++) {
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if (working)
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*p = 0;
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for (; *p <= IO_DQS_EN_PHASE_MAX; (*p)++) {
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scc_mgr_set_dqs_en_phase_all_ranks(grp, *p);
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ret = rw_mgr_mem_calibrate_read_test_all_ranks(grp, 1,
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PASS_ONE_BIT, &bit_chk, 0);
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if (ret)
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(*max_working_cnt)++;
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if (!working)
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ret = !ret;
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if (ret)
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return 0;
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*work += IO_DELAY_PER_OPA_TAP;
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}
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if (*p > IO_DQS_EN_PHASE_MAX) {
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/* Fiddle with FIFO. */
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rw_mgr_incr_vfifo(grp, v);
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if (!working)
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*p = 0;
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}
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}
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return -EINVAL;
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}
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static int sdr_working_phase(uint32_t grp,
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uint32_t dtaps_per_ptap, uint32_t *work_bgn,
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uint32_t *v, uint32_t *d, uint32_t *p,
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uint32_t *i, uint32_t *max_working_cnt)
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{
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uint32_t tmp_delay = 0;
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uint32_t test_status;
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u32 bit_chk;
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int ret;
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for (*d = 0; *d <= dtaps_per_ptap; (*d)++, tmp_delay +=
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IO_DELAY_PER_DQS_EN_DCHAIN_TAP) {
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*work_bgn = tmp_delay;
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*work_bgn = 0;
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for (*d = 0; *d <= dtaps_per_ptap; (*d)++) {
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*i = 0;
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scc_mgr_set_dqs_en_delay_all_ranks(grp, *d);
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for (*i = 0; *i < VFIFO_SIZE; (*i)++) {
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for (*p = 0; *p <= IO_DQS_EN_PHASE_MAX; (*p)++, *work_bgn +=
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IO_DELAY_PER_OPA_TAP) {
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scc_mgr_set_dqs_en_phase_all_ranks(grp, *p);
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test_status =
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rw_mgr_mem_calibrate_read_test_all_ranks
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(grp, 1, PASS_ONE_BIT, &bit_chk, 0);
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if (test_status) {
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*max_working_cnt = 1;
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return 1;
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}
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}
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if (*p > IO_DQS_EN_PHASE_MAX)
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/* fiddle with FIFO */
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rw_mgr_incr_vfifo(grp, v);
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}
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ret = sdr_find_phase(1, grp, v, work_bgn, i, p, max_working_cnt);
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if (!ret)
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return 0;
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*work_bgn += IO_DELAY_PER_DQS_EN_DCHAIN_TAP;
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}
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/* Cannot find working solution */
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debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: no vfifo/\
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ptap/dtap\n", __func__, __LINE__);
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return 0;
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debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: no vfifo/ptap/dtap\n",
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__func__, __LINE__);
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return -EINVAL;
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}
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static void sdr_backup_phase(uint32_t grp,
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@ -1426,40 +1459,24 @@ static int sdr_nonworking_phase(uint32_t grp,
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uint32_t *p, uint32_t *i, uint32_t *max_working_cnt,
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uint32_t *work_end)
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{
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u32 bit_chk;
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int ret;
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(*p)++;
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*work_end += IO_DELAY_PER_OPA_TAP;
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if (*p > IO_DQS_EN_PHASE_MAX) {
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/* fiddle with FIFO */
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/* Fiddle with FIFO. */
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*p = 0;
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rw_mgr_incr_vfifo(grp, v);
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}
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for (; *i < VFIFO_SIZE + 1; (*i)++) {
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for (; *p <= IO_DQS_EN_PHASE_MAX; (*p)++, *work_end
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+= IO_DELAY_PER_OPA_TAP) {
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scc_mgr_set_dqs_en_phase_all_ranks(grp, *p);
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if (!rw_mgr_mem_calibrate_read_test_all_ranks
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(grp, 1, PASS_ONE_BIT, &bit_chk, 0)) {
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return 1;
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} else {
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(*max_working_cnt)++;
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}
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}
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if (*p > IO_DQS_EN_PHASE_MAX) {
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/* fiddle with FIFO */
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rw_mgr_incr_vfifo(grp, v);
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*p = 0;
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}
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ret = sdr_find_phase(0, grp, v, work_end, i, p, max_working_cnt);
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if (ret) {
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/* Cannot see edge of failing read. */
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debug_cond(DLEVEL == 2, "%s:%d: end: failed\n",
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__func__, __LINE__);
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}
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/* Cannot see edge of failing read. */
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debug_cond(DLEVEL == 2, "%s:%d sdr_nonworking_phase: end:\
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failed\n", __func__, __LINE__);
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return 0;
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return ret;
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}
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/**
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@ -1562,7 +1579,7 @@ static uint32_t rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase(uint32_t grp)
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/* * step 2: find first working phase, increment in ptaps * */
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work_bgn = 0;
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if (sdr_working_phase(grp, dtaps_per_ptap, &work_bgn, &v, &d,
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&p, &i, &max_working_cnt) == 0)
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&p, &i, &max_working_cnt))
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return 0;
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work_end = work_bgn;
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@ -1584,7 +1601,7 @@ static uint32_t rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase(uint32_t grp)
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/* * step 4a: go forward from working phase to non working
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phase, increment in ptaps * */
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if (sdr_nonworking_phase(grp, &work_bgn, &v, &d, &p,
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&i, &max_working_cnt, &work_end) == 0)
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&i, &max_working_cnt, &work_end))
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return 0;
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/* ********************************************************* */
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