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https://github.com/brain-hackers/u-boot-brain
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spi: ich: Move the protection/lockdown code into a function
Reduce the size of the probe function but putting this code into its own function. Also remove the assumption that the PCH is always a parent of the SPI controller, as this is not the case APL platforms. Use driver model to find the PCH instead. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
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@ -98,13 +98,14 @@ static void ich_set_bbar(struct ich_spi_priv *ctlr, uint32_t minaddr)
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/* @return 1 if the SPI flash supports the 33MHz speed */
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static int ich9_can_do_33mhz(struct udevice *dev)
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{
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struct ich_spi_priv *priv = dev_get_priv(dev);
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u32 fdod, speed;
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/* Observe SPI Descriptor Component Section 0 */
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dm_pci_write_config32(dev->parent, 0xb0, 0x1000);
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dm_pci_write_config32(priv->pch, 0xb0, 0x1000);
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/* Extract the Write/Erase SPI Frequency from descriptor */
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dm_pci_read_config32(dev->parent, 0xb4, &fdod);
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dm_pci_read_config32(priv->pch, 0xb4, &fdod);
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/* Bits 23:21 have the fast read clock frequency, 0=20MHz, 1=33MHz */
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speed = (fdod >> 21) & 7;
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@ -432,6 +433,37 @@ static int ich_spi_adjust_size(struct spi_slave *slave, struct spi_mem_op *op)
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return 0;
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}
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static int ich_protect_lockdown(struct udevice *dev)
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{
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struct ich_spi_platdata *plat = dev_get_platdata(dev);
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struct ich_spi_priv *priv = dev_get_priv(dev);
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int ret = -ENOSYS;
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/* Disable the BIOS write protect so write commands are allowed */
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if (priv->pch)
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ret = pch_set_spi_protect(priv->pch, false);
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if (ret == -ENOSYS) {
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u8 bios_cntl;
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bios_cntl = ich_readb(priv, priv->bcr);
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bios_cntl &= ~BIT(5); /* clear Enable InSMM_STS (EISS) */
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bios_cntl |= 1; /* Write Protect Disable (WPD) */
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ich_writeb(priv, bios_cntl, priv->bcr);
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} else if (ret) {
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debug("%s: Failed to disable write-protect: err=%d\n",
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__func__, ret);
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return ret;
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}
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/* Lock down SPI controller settings if required */
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if (plat->lockdown) {
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ich_spi_config_opcode(dev);
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spi_lock_down(plat, priv->base);
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}
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return 0;
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}
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static int ich_init_controller(struct udevice *dev,
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struct ich_spi_platdata *plat,
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struct ich_spi_priv *ctlr)
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@ -497,30 +529,15 @@ static int ich_spi_probe(struct udevice *dev)
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{
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struct ich_spi_platdata *plat = dev_get_platdata(dev);
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struct ich_spi_priv *priv = dev_get_priv(dev);
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uint8_t bios_cntl;
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int ret;
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ret = ich_init_controller(dev, plat, priv);
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if (ret)
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return ret;
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/* Disable the BIOS write protect so write commands are allowed */
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ret = pch_set_spi_protect(dev->parent, false);
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if (ret == -ENOSYS) {
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bios_cntl = ich_readb(priv, priv->bcr);
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bios_cntl &= ~BIT(5); /* clear Enable InSMM_STS (EISS) */
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bios_cntl |= 1; /* Write Protect Disable (WPD) */
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ich_writeb(priv, bios_cntl, priv->bcr);
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} else if (ret) {
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debug("%s: Failed to disable write-protect: err=%d\n",
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__func__, ret);
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return ret;
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}
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/* Lock down SPI controller settings if required */
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if (plat->lockdown) {
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ich_spi_config_opcode(dev);
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spi_lock_down(plat, priv->base);
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}
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ret = ich_protect_lockdown(dev);
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if (ret)
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return ret;
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priv->cur_speed = priv->max_speed;
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@ -579,9 +596,15 @@ static int ich_spi_child_pre_probe(struct udevice *dev)
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static int ich_spi_ofdata_to_platdata(struct udevice *dev)
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{
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struct ich_spi_platdata *plat = dev_get_platdata(dev);
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struct ich_spi_priv *priv = dev_get_priv(dev);
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int node = dev_of_offset(dev);
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int ret;
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/* Find a PCH if there is one */
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uclass_first_device(UCLASS_PCH, &priv->pch);
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if (!priv->pch)
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priv->pch = dev_get_parent(dev);
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ret = fdt_node_check_compatible(gd->fdt_blob, node, "intel,ich7-spi");
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if (ret == 0) {
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plat->ich_version = ICHV_7;
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@ -191,6 +191,7 @@ struct ich_spi_priv {
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ulong max_speed; /* Maximum bus speed in MHz */
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ulong cur_speed; /* Current bus speed */
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struct spi_trans trans; /* current transaction in progress */
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struct udevice *pch; /* PCH, used to control SPI access */
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};
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#endif /* _ICH_H_ */
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