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ARM: OMAP5: Add support for disabling clocks in uboot
Add do_disable_clocks() to disable clock domains and module clocks. These clocks are enabled using do_enable_clocks(). Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Vignesh R <vigneshr@ti.com> Reviewed-by: Jagan Teki <jteki@openedev.com>
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fca45722fb
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16ca1d09e6
@ -648,6 +648,14 @@ static inline void enable_clock_domain(u32 const clkctrl_reg, u32 enable_mode)
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debug("Enable clock domain - %x\n", clkctrl_reg);
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debug("Enable clock domain - %x\n", clkctrl_reg);
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}
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}
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static inline void disable_clock_domain(u32 const clkctrl_reg)
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{
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clrsetbits_le32(clkctrl_reg, CD_CLKCTRL_CLKTRCTRL_MASK,
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CD_CLKCTRL_CLKTRCTRL_SW_SLEEP <<
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CD_CLKCTRL_CLKTRCTRL_SHIFT);
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debug("Disable clock domain - %x\n", clkctrl_reg);
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}
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static inline void wait_for_clk_enable(u32 clkctrl_addr)
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static inline void wait_for_clk_enable(u32 clkctrl_addr)
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{
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{
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u32 clkctrl, idlest = MODULE_CLKCTRL_IDLEST_DISABLED;
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u32 clkctrl, idlest = MODULE_CLKCTRL_IDLEST_DISABLED;
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@ -677,6 +685,34 @@ static inline void enable_clock_module(u32 const clkctrl_addr, u32 enable_mode,
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wait_for_clk_enable(clkctrl_addr);
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wait_for_clk_enable(clkctrl_addr);
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}
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}
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static inline void wait_for_clk_disable(u32 clkctrl_addr)
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{
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u32 clkctrl, idlest = MODULE_CLKCTRL_IDLEST_FULLY_FUNCTIONAL;
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u32 bound = LDELAY;
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while ((idlest != MODULE_CLKCTRL_IDLEST_DISABLED)) {
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clkctrl = readl(clkctrl_addr);
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idlest = (clkctrl & MODULE_CLKCTRL_IDLEST_MASK) >>
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MODULE_CLKCTRL_IDLEST_SHIFT;
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if (--bound == 0) {
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printf("Clock disable failed for 0x%x idlest 0x%x\n",
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clkctrl_addr, clkctrl);
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return;
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}
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}
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}
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static inline void disable_clock_module(u32 const clkctrl_addr,
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u32 wait_for_disable)
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{
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clrsetbits_le32(clkctrl_addr, MODULE_CLKCTRL_MODULEMODE_MASK,
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MODULE_CLKCTRL_MODULEMODE_SW_DISABLE <<
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MODULE_CLKCTRL_MODULEMODE_SHIFT);
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debug("Disable clock module - %x\n", clkctrl_addr);
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if (wait_for_disable)
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wait_for_clk_disable(clkctrl_addr);
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}
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void freq_update_core(void)
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void freq_update_core(void)
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{
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{
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u32 freq_config1 = 0;
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u32 freq_config1 = 0;
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@ -800,6 +836,23 @@ void do_enable_clocks(u32 const *clk_domains,
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}
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}
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}
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}
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void do_disable_clocks(u32 const *clk_domains,
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u32 const *clk_modules_disable,
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u8 wait_for_disable)
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{
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u32 i, max = 100;
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/* Clock modules that need to be put in SW_DISABLE */
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for (i = 0; (i < max) && clk_modules_disable[i]; i++)
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disable_clock_module(clk_modules_disable[i],
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wait_for_disable);
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/* Put the clock domains in SW_SLEEP mode */
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for (i = 0; (i < max) && clk_domains[i]; i++)
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disable_clock_domain(clk_domains[i]);
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}
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void prcm_init(void)
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void prcm_init(void)
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{
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{
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switch (omap_hw_init_context()) {
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switch (omap_hw_init_context()) {
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@ -575,6 +575,10 @@ void do_enable_clocks(u32 const *clk_domains,
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u32 const *clk_modules_explicit_en,
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u32 const *clk_modules_explicit_en,
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u8 wait_for_enable);
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u8 wait_for_enable);
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void do_disable_clocks(u32 const *clk_domains,
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u32 const *clk_modules_disable,
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u8 wait_for_disable);
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void setup_post_dividers(u32 const base,
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void setup_post_dividers(u32 const base,
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const struct dpll_params *params);
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const struct dpll_params *params);
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u32 omap_ddr_clk(void);
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u32 omap_ddr_clk(void);
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