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https://github.com/brain-hackers/u-boot-brain
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x86: acpi: apl: Add asl files for Apollo Lake
Add Apollo Lake ASL files, taken from coreboot. Signed-off-by: Simon Glass <sjg@chromium.org>
This commit is contained in:
Simon Glass
Bin Meng
parent
d9434a17e5
commit
14f643d1a2
35
arch/x86/include/asm/arch-apollolake/acpi/dptf.asl
Normal file
35
arch/x86/include/asm/arch-apollolake/acpi/dptf.asl
Normal file
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@ -0,0 +1,35 @@
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/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (C) 2016 Intel Corporation.
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*/
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#define DPTF_CPU_DEVICE TCPU
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#define DPTF_CPU_ADDR 0x00000001
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#ifndef DPTF_CPU_PASSIVE
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#define DPTF_CPU_PASSIVE 80
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#endif
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#ifndef DPTF_CPU_CRITICAL
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#define DPTF_CPU_CRITICAL 90
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#endif
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#ifndef DPTF_CPU_ACTIVE_AC0
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#define DPTF_CPU_ACTIVE_AC0 90
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#endif
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#ifndef DPTF_CPU_ACTIVE_AC1
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#define DPTF_CPU_ACTIVE_AC1 80
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#endif
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#ifndef DPTF_CPU_ACTIVE_AC2
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#define DPTF_CPU_ACTIVE_AC2 70
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#endif
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#ifndef DPTF_CPU_ACTIVE_AC3
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#define DPTF_CPU_ACTIVE_AC3 60
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#endif
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#ifndef DPTF_CPU_ACTIVE_AC4
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#define DPTF_CPU_ACTIVE_AC4 50
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#endif
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41
arch/x86/include/asm/arch-apollolake/acpi/globalnvs.asl
Normal file
41
arch/x86/include/asm/arch-apollolake/acpi/globalnvs.asl
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@ -0,0 +1,41 @@
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/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright (C) 2016 Intel Corp.
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* (Written by Alexandru Gagniuc <alexandrux.gagniuc@intel.com> for Intel Corp.)
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*/
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/*
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* NOTE: The layout of the GNVS structure below must match the layout in
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* soc/intel/apollolake/include/soc/nvs.h !!!
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*
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*/
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External (NVSA)
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OperationRegion (GNVS, SystemMemory, NVSA, ACPI_GNVS_SIZE)
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Field (GNVS, ByteAcc, NoLock, Preserve)
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{
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/* Miscellaneous */
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Offset (0x00),
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PCNT, 8, // 0x00 - Processor Count
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PPCM, 8, // 0x01 - Max PPC State
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LIDS, 8, // 0x02 - LID State
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PWRS, 8, // 0x03 - AC Power State
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DPTE, 8, // 0x04 - Enable DPTF
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CBMC, 32, // 0x05 - 0x08 - coreboot Memory Console
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PM1I, 64, // 0x09 - 0x10 - System Wake Source - PM1 Index
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GPEI, 64, // 0x11 - 0x18 - GPE Wake Source
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NHLA, 64, // 0x19 - 0x20 - NHLT Address
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NHLL, 32, // 0x21 - 0x24 - NHLT Length
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PRT0, 32, // 0x25 - 0x28 - PERST_0 Address
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SCDP, 8, // 0x29 - SD_CD GPIO portid
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SCDO, 8, // 0x2A - GPIO pad offset relative to the community
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UIOR, 8, // 0x2B - UART debug controller init on S3 resume
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EPCS, 8, // 0x2C - SGX Enabled status
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EMNA, 64, // 0x2D - 0x34 EPC base address
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ELNG, 64, // 0x35 - 0x3C EPC Length
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/* ChromeOS stuff (0x100 -> 0xfff, size 0xeff) */
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Offset (0x100),
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#include <asm/acpi/cros_gnvs.asl>
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}
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191
arch/x86/include/asm/arch-apollolake/acpi/gpio.asl
Normal file
191
arch/x86/include/asm/arch-apollolake/acpi/gpio.asl
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@ -0,0 +1,191 @@
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/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright (C) 2016 Intel Corp.
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* (Written by Lance Zhao <lijian.zhao@intel.com> for Intel Corp.)
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*/
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#include <asm/arch/gpio.h>
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#include <asm/intel_pinctrl_defs.h>
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// #include <intelblocks/pcr.h>
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// #include <soc/pcr_ids.h>
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#include <asm/arch/iomap.h>
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#include <p2sb.h>
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#include "gpiolib.asl"
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scope (\_SB) {
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Device (GPO0)
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{
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Name (_HID, GPIO_COMM_NAME)
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Name (_CID, GPIO_COMM_NAME)
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Name (_DDN, GPIO_COMM_0_DESC)
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Name (_UID, 1)
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Name (RBUF, ResourceTemplate ()
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{
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Memory32Fixed (ReadWrite, 0, 0x4000, RMEM)
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Interrupt (ResourceConsumer, Level, ActiveLow, Shared, , , )
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{
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GPIO_BANK_INT
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}
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})
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Method (_CRS, 0x0, NotSerialized)
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{
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CreateDwordField (^RBUF, ^RMEM._BAS, RBAS)
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ShiftLeft (GPIO_COMM0_PID, PCR_PORTID_SHIFT, Local0)
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Or (IOMAP_P2SB_BAR, Local0, RBAS)
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Return (^RBUF)
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}
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Method (_STA, 0x0, NotSerialized)
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{
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Return(0xf)
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}
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}
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Device (GPO1)
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{
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Name (_HID, GPIO_COMM_NAME)
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Name (_CID, GPIO_COMM_NAME)
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Name (_DDN, GPIO_COMM_1_DESC)
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Name (_UID, 2)
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Name (RBUF, ResourceTemplate ()
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{
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Memory32Fixed (ReadWrite, 0, 0x4000, RMEM)
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Interrupt (ResourceConsumer, Level, ActiveLow, Shared, , , )
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{
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GPIO_BANK_INT
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}
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})
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Method (_CRS, 0x0, NotSerialized)
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{
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CreateDwordField (^RBUF, ^RMEM._BAS, RBAS)
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ShiftLeft (GPIO_COMM1_PID, PCR_PORTID_SHIFT, Local0)
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Or (IOMAP_P2SB_BAR, Local0, RBAS)
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Return (^RBUF)
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}
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Method (_STA, 0x0, NotSerialized)
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{
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Return(0xf)
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}
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}
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Device (GPO2)
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{
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Name (_HID, GPIO_COMM_NAME)
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Name (_CID, GPIO_COMM_NAME)
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Name (_DDN, GPIO_COMM_2_DESC)
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Name (_UID, 3)
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Name (RBUF, ResourceTemplate ()
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{
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Memory32Fixed (ReadWrite, 0, 0x4000, RMEM)
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Interrupt (ResourceConsumer, Level, ActiveLow, Shared, , , )
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{
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GPIO_BANK_INT
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}
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})
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Method (_CRS, 0x0, NotSerialized)
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{
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CreateDwordField (^RBUF, ^RMEM._BAS, RBAS)
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ShiftLeft (GPIO_COMM2_PID, PCR_PORTID_SHIFT, Local0)
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Or (IOMAP_P2SB_BAR, Local0, RBAS)
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Return (^RBUF)
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}
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Method (_STA, 0x0, NotSerialized)
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{
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Return(0xf)
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}
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}
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Device (GPO3)
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{
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Name (_HID, GPIO_COMM_NAME)
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Name (_CID, GPIO_COMM_NAME)
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Name (_DDN, GPIO_COMM_3_DESC)
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Name (_UID, 4)
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Name (RBUF, ResourceTemplate ()
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{
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Memory32Fixed (ReadWrite, 0, 0x4000, RMEM)
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Interrupt (ResourceConsumer, Level, ActiveLow, Shared, , , )
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{
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GPIO_BANK_INT
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}
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})
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Method (_CRS, 0x0, NotSerialized)
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{
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CreateDwordField (^RBUF, ^RMEM._BAS, RBAS)
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ShiftLeft (GPIO_COMM3_PID, PCR_PORTID_SHIFT, Local0)
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Or (IOMAP_P2SB_BAR, Local0, RBAS)
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Return (^RBUF)
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}
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Method (_STA, 0x0, NotSerialized)
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{
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Return(0xf)
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}
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}
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Scope(\_SB.PCI0) {
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/* PERST Assertion
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* Note: PERST is Active High
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*/
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Method (PRAS, 0x1, Serialized)
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{
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/*
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* Assert PERST
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* local1 - to toggle Tx pin of Dw0
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* local2 - Address of PERST
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*/
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Store (Arg0, Local2)
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Store (\_SB.GPC0 (Local2), Local1)
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Or (Local1, PAD_CFG0_TX_STATE, Local1)
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\_SB.SPC0 (Local2, Local1)
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}
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/* PERST DE-Assertion */
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Method (PRDA, 0x1, Serialized)
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{
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/*
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* De-assert PERST
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* local1 - to toggle Tx pin of Dw0
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* local2 - Address of PERST
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*/
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Store (Arg0, Local2)
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Store (\_SB.GPC0 (Local2), Local1)
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And (Local1, Not (PAD_CFG0_TX_STATE), Local1)
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\_SB.SPC0 (Local2, Local1)
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}
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}
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/*
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* Sleep button device ASL code. We are using this device to
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* add the _PRW method for a dummy wake event to kernel so that
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* before going to sleep kernel does not clear bit 15 in ACPI
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* gpe0a enable register which is actually the GPIO_TIER1_SCI_EN bit.
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*/
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Device (SLP)
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{
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Name (_HID, EisaId ("PNP0C0E"))
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Name (_PRW, Package() { GPE0A_GPIO_TIER1_SCI_STS, 0x3 })
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}
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}
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Scope(\_GPE)
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{
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/*
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* Dummy method for the Tier 1 GPIO SCI enable bit. When kernel reads
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* _L0F in scope GPE it sets bit for gpio_tier1_sci_en in ACPI enable
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* register at 0x430. For APL ACPI enable register DW0 i.e., ACPI
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* GPE0a_EN at 0x430 is reserved.
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*/
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Method(_L0F, 0) {}
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}
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109
arch/x86/include/asm/arch-apollolake/acpi/gpiolib.asl
Normal file
109
arch/x86/include/asm/arch-apollolake/acpi/gpiolib.asl
Normal file
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@ -0,0 +1,109 @@
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/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (C) 2016 Intel Corporation.
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*/
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Scope (\_SB)
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{
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/* Get Pad Configuration DW0 register value */
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Method (GPC0, 0x1, Serialized)
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{
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/* Arg0 - GPIO DW0 address */
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Store (Arg0, Local0)
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OperationRegion (PDW0, SystemMemory, Local0, 4)
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Field (PDW0, AnyAcc, NoLock, Preserve) {
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TEMP, 32
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}
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Return (TEMP)
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}
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/* Set Pad Configuration DW0 register value */
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Method (SPC0, 0x2, Serialized)
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{
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/* Arg0 - GPIO DW0 address */
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/* Arg1 - Value for DW0 register */
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Store (Arg0, Local0)
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OperationRegion (PDW0, SystemMemory, Local0, 4)
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Field (PDW0, AnyAcc, NoLock, Preserve) {
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TEMP,32
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}
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Store (Arg1, TEMP)
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}
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/* Get Pad Configuration DW1 register value */
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Method (GPC1, 0x1, Serialized)
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{
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/* Arg0 - GPIO DW0 address */
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Store (Add (Arg0, 0x4), Local0)
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OperationRegion (PDW1, SystemMemory, Local0, 4)
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Field (PDW1, AnyAcc, NoLock, Preserve) {
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TEMP, 32
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}
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Return (TEMP)
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}
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/* Set Pad Configuration DW1 register value */
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Method (SPC1, 0x2, Serialized)
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{
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/* Arg0 - GPIO DW0 address */
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/* Arg1 - Value for DW1 register */
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Store (Add (Arg0, 0x4), Local0)
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OperationRegion (PDW1, SystemMemory, Local0, 4)
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Field(PDW1, AnyAcc, NoLock, Preserve) {
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TEMP,32
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}
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Store (Arg1, TEMP)
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}
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/* Get DW0 address of a given pad */
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Method (GDW0, 0x2, Serialized)
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{
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/* Arg0 - GPIO portid */
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/* Arg1 - GPIO pad offset relative to the community */
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Store (0, Local1)
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Or( Or (ShiftLeft (Arg0, 16), IOMAP_P2SB_BAR),
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Local1, Local1)
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Or( Add (PAD_CFG_BASE, Multiply (Arg1, Multiply (
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GPIO_NUM_PAD_CFG_REGS, 4))), Local1, Local1)
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Return (Local1)
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}
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/* Calculate HOSTSW_REG address */
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Method (CHSA, 0x1, Serialized)
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{
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/* Arg0 - GPIO pad offset relative to the community */
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Add (HOSTSW_OWN_REG_0, Multiply (Divide (Arg0, 32), 4), Local1)
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Return (Local1)
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}
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/* Get Host ownership register of GPIO Community */
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Method (GHO, 0x2, Serialized)
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{
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/* Arg0 - GPIO portid */
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/* Arg1 - GPIO pad offset relative to the community */
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Store (CHSA (Arg1), Local1)
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OperationRegion (SHO0, SystemMemory, Or ( Or
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(IOMAP_P2SB_BAR, ShiftLeft (Arg0, 16)), Local1), 4)
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Field (SHO0, AnyAcc, NoLock, Preserve) {
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TEMP, 32
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}
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Return (TEMP)
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}
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/* Set Host ownership register of GPIO Community */
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Method (SHO, 0x3, Serialized)
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{
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/* Arg0 - GPIO portid */
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/* Arg1 - GPIO pad offset relative to the community */
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/* Arg2 - Value for Host own register */
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Store (CHSA (Arg1), Local1)
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OperationRegion (SHO0, SystemMemory, Or ( Or
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(IOMAP_P2SB_BAR, ShiftLeft (Arg0, 16)), Local1), 4)
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Field (SHO0, AnyAcc, NoLock, Preserve) {
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TEMP, 32
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}
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Store (Arg2, TEMP)
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}
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}
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105
arch/x86/include/asm/arch-apollolake/acpi/lpss.asl
Normal file
105
arch/x86/include/asm/arch-apollolake/acpi/lpss.asl
Normal file
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/* SPDX-License-Identifier: GPL-2.0+ */
|
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/*
|
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* Copyright (C) 2016 Intel Corp.
|
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* (Written by Lance Zhao <lijian.zhao@intel.com> for Intel Corp.)
|
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*/
|
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scope (\_SB.PCI0) {
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/* LPIO1 PWM */
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Device(PWM) {
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Name (_ADR, 0x001A0000)
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Name (_DDN, "Intel(R) PWM Controller")
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}
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/* LPIO1 HS-UART #1 */
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Device(URT1) {
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Name (_ADR, 0x00180000)
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Name (_DDN, "Intel(R) HS-UART Controller #1")
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}
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/* LPIO1 HS-UART #2 */
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Device(URT2) {
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Name (_ADR, 0x00180001)
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Name (_DDN, "Intel(R) HS-UART Controller #2")
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}
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/* LPIO1 HS-UART #3 */
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Device(URT3) {
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Name (_ADR, 0x00180002)
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Name (_DDN, "Intel(R) HS-UART Controller #3")
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}
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/* LPIO1 HS-UART #4 */
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Device(URT4) {
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Name (_ADR, 0x00180003)
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Name (_DDN, "Intel(R) HS-UART Controller #4")
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}
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/* LPIO1 SPI */
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Device(SPI1) {
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Name (_ADR, 0x00190000)
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Name (_DDN, "Intel(R) SPI Controller #1")
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}
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/* LPIO1 SPI #2 */
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Device(SPI2) {
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Name (_ADR, 0x00190001)
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Name (_DDN, "Intel(R) SPI Controller #2")
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}
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/* LPIO1 SPI #3 */
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Device(SPI3) {
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Name (_ADR, 0x00190002)
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Name (_DDN, "Intel(R) SPI Controller #3")
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}
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/* LPIO2 I2C #0 */
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Device(I2C0) {
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Name (_ADR, 0x00160000)
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Name (_DDN, "Intel(R) I2C Controller #0")
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}
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/* LPIO2 I2C #1 */
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Device(I2C1) {
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Name (_ADR, 0x00160001)
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Name (_DDN, "Intel(R) I2C Controller #1")
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}
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/* LPIO2 I2C #2 */
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Device(I2C2) {
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Name (_ADR, 0x00160002)
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Name (_DDN, "Intel(R) I2C Controller #2")
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}
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/* LPIO2 I2C #3 */
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Device(I2C3) {
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Name (_ADR, 0x00160003)
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Name (_DDN, "Intel(R) I2C Controller #3")
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}
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/* LPIO2 I2C #4 */
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Device(I2C4) {
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Name (_ADR, 0x00170000)
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Name (_DDN, "Intel(R) I2C Controller #4")
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}
|
||||
|
||||
/* LPIO2 I2C #5 */
|
||||
Device(I2C5) {
|
||||
Name (_ADR, 0x00170001)
|
||||
Name (_DDN, "Intel(R) I2C Controller #5")
|
||||
}
|
||||
|
||||
/* LPIO2 I2C #6 */
|
||||
Device(I2C6) {
|
||||
Name (_ADR, 0x00170002)
|
||||
Name (_DDN, "Intel(R) I2C Controller #6")
|
||||
}
|
||||
|
||||
/* LPIO2 I2C #7 */
|
||||
Device(I2C7) {
|
||||
Name (_ADR, 0x00170003)
|
||||
Name (_DDN, "Intel(R) I2C Controller #7")
|
||||
}
|
||||
}
|
||||
120
arch/x86/include/asm/arch-apollolake/acpi/northbridge.asl
Normal file
120
arch/x86/include/asm/arch-apollolake/acpi/northbridge.asl
Normal file
|
|
@ -0,0 +1,120 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* Copyright (C) 2016 Intel Corp.
|
||||
* (Written by Lance Zhao <lijian.zhao@intel.com> for Intel Corp.)
|
||||
*/
|
||||
|
||||
Name(_HID, EISAID("PNP0A08")) /* PCIe */
|
||||
Name(_CID, EISAID("PNP0A03")) /* PCI */
|
||||
Name(_BBN, 0)
|
||||
|
||||
Device (MCHC)
|
||||
{
|
||||
Name (_ADR, 0x00000000) /*Dev0 Func0 */
|
||||
|
||||
OperationRegion (MCHP, PCI_Config, 0x00, 0x100)
|
||||
Field (MCHP, DWordAcc, NoLock, Preserve)
|
||||
{
|
||||
Offset(0x60),
|
||||
MCNF, 32, /* PCI MMCONF base */
|
||||
Offset (0xA8),
|
||||
TUUD, 64, /* Top of Upper Used Memory */
|
||||
Offset(0xB4),
|
||||
BGSM, 32, /* Base of Graphics Stolen Memory */
|
||||
Offset(0xBC),
|
||||
TLUD, 32, /* Top of Low Useable DRAM */
|
||||
}
|
||||
}
|
||||
Name (MCRS, ResourceTemplate()
|
||||
{
|
||||
/* Bus Numbers */
|
||||
WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode,
|
||||
0x0000, 0x0000, 0x00ff, 0x0000, 0x0100,,,)
|
||||
|
||||
/* IO Region 0 */
|
||||
DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
|
||||
0x0000, 0x0000, 0x0cf7, 0x0000, 0x0cf8,,,)
|
||||
|
||||
/* PCI Config Space */
|
||||
Io (Decode16, 0x0cf8, 0x0cf8, 0x0001, 0x0008)
|
||||
|
||||
/* IO Region 1 */
|
||||
DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
|
||||
0x0000, 0x01000, 0xffff, 0x0000, 0xf000,,,)
|
||||
|
||||
/* VGA memory (0xa0000-0xbffff) */
|
||||
DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
|
||||
Cacheable, ReadWrite,
|
||||
0x00000000, 0x000a0000, 0x000bffff, 0x00000000,
|
||||
0x00020000,,,)
|
||||
|
||||
/* Data and GFX stolen memory */
|
||||
DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
|
||||
Cacheable, ReadWrite,
|
||||
0x00000000, 0x3be00000, 0x3fffffff, 0x00000000,
|
||||
0x04200000,,, STOM)
|
||||
|
||||
/*
|
||||
* PCI MMIO Region (TOLUD - PCI extended base MMCONF)
|
||||
* This assumes that MMCONF is placed after PCI config space,
|
||||
* and that no resources are allocated after the MMCONF region.
|
||||
* This works, sicne MMCONF is hardcoded to 0xe00000000.
|
||||
*/
|
||||
DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
|
||||
NonCacheable, ReadWrite,
|
||||
0x00000000, 0x00000000, 0x00000000, 0x00000000,
|
||||
0x00000000,,, PM01)
|
||||
|
||||
/* PCI Memory Region (TOUUD - (TOUUD + ABOVE_4G_MMIO_SIZE)) */
|
||||
QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
|
||||
NonCacheable, ReadWrite,
|
||||
0x00000000, 0x10000, 0x1ffff, 0x00000000,
|
||||
0x10000,,, PM02)
|
||||
})
|
||||
|
||||
/* Current Resource Settings */
|
||||
Method (_CRS, 0, Serialized)
|
||||
{
|
||||
|
||||
/* Find PCI resource area in MCRS */
|
||||
CreateDwordField (MCRS, ^PM01._MIN, PMIN)
|
||||
CreateDwordField (MCRS, ^PM01._MAX, PMAX)
|
||||
CreateDwordField (MCRS, ^PM01._LEN, PLEN)
|
||||
|
||||
/* Read C-Unit PCI CFG Reg. 0xBC for TOLUD (shadow from B-Unit) */
|
||||
And(^MCHC.TLUD, 0xFFF00000, PMIN)
|
||||
/* Read MMCONF base */
|
||||
And(^MCHC.MCNF, 0xF0000000, PMAX)
|
||||
|
||||
/* Calculate PCI MMIO Length */
|
||||
Add(Subtract(PMAX, PMIN), 1, PLEN)
|
||||
|
||||
/* Find GFX resource area in GCRS */
|
||||
CreateDwordField(MCRS, ^STOM._MIN, GMIN)
|
||||
CreateDwordField(MCRS, ^STOM._MAX, GMAX)
|
||||
CreateDwordField(MCRS, ^STOM._LEN, GLEN)
|
||||
|
||||
/* Read BGSM */
|
||||
And(^MCHC.BGSM, 0xFFF00000, GMIN)
|
||||
|
||||
/* Read TOLUD */
|
||||
And(^MCHC.TLUD, 0xFFF00000, GMAX)
|
||||
Decrement(GMAX)
|
||||
Add(Subtract(GMAX, GMIN), 1, GLEN)
|
||||
|
||||
/* Patch PM02 range based on Memory Size */
|
||||
CreateQwordField (MCRS, ^PM02._MIN, MMIN)
|
||||
CreateQwordField (MCRS, ^PM02._MAX, MMAX)
|
||||
CreateQwordField (MCRS, ^PM02._LEN, MLEN)
|
||||
|
||||
Store (^MCHC.TUUD, Local0)
|
||||
|
||||
If (LLessEqual (Local0, 0x1000000000))
|
||||
{
|
||||
Store (0, MMIN)
|
||||
Store (0, MLEN)
|
||||
}
|
||||
Subtract (Add (MMIN, MLEN), 1, MMAX)
|
||||
|
||||
Return (MCRS)
|
||||
}
|
||||
77
arch/x86/include/asm/arch-apollolake/acpi/pch_hda.asl
Normal file
77
arch/x86/include/asm/arch-apollolake/acpi/pch_hda.asl
Normal file
|
|
@ -0,0 +1,77 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
/*
|
||||
* Copyright (C) 2016 Intel Corporation.
|
||||
* Copyright (C) 2016 Google Inc.
|
||||
*
|
||||
*/
|
||||
|
||||
/* Audio Controller - Device 14, Function 0 */
|
||||
|
||||
Device (HDAS)
|
||||
{
|
||||
Name (_ADR, 0x000E0000)
|
||||
Name (_DDN, "Audio Controller")
|
||||
Name (UUID, ToUUID("A69F886E-6CEB-4594-A41F-7B5DCE24C553"))
|
||||
|
||||
/* Device is D3 wake capable */
|
||||
Name (_S0W, 3)
|
||||
|
||||
/* NHLT Table Address populated from GNVS values */
|
||||
Name (NBUF, ResourceTemplate() {
|
||||
QWordMemory (ResourceConsumer, PosDecode, MinFixed,
|
||||
MaxFixed, Cacheable, ReadOnly,
|
||||
0, 0, 0, 0, 1,,, NHLT, AddressRangeACPI)
|
||||
}
|
||||
)
|
||||
|
||||
/* can wake up from S3 state */
|
||||
Name (_PRW, Package() { GPE0A_AVS_PME_STS, 3 })
|
||||
|
||||
/*
|
||||
* Device Specific Method
|
||||
* Arg0 - UUID
|
||||
* Arg1 - Revision
|
||||
* Arg2 - Function Index
|
||||
*/
|
||||
Method (_DSM, 4) {
|
||||
If (LEqual (Arg0, ^UUID)) {
|
||||
/*
|
||||
* Function 0: Function Support Query
|
||||
* Returns a bitmask of functions supported.
|
||||
*/
|
||||
If (LEqual (Arg2, Zero)) {
|
||||
/*
|
||||
* NHLT Query only supported for revision 1 and
|
||||
* if NHLT address and length are set in NVS.
|
||||
*/
|
||||
If (LAnd (LEqual (Arg1, One),
|
||||
LAnd (LNotEqual (NHLA, Zero),
|
||||
LNotEqual (NHLL, Zero)))) {
|
||||
Return (Buffer (One) { 0x03 })
|
||||
}
|
||||
Else {
|
||||
Return (Buffer (One) { 0x01 })
|
||||
}
|
||||
}
|
||||
|
||||
/*
|
||||
* Function 1: Query NHLT memory address used by
|
||||
* Intel Offload Engine Driver to discover any non-HDA
|
||||
* devices that are supported by the DSP.
|
||||
*
|
||||
* Returns a pointer to NHLT table in memory.
|
||||
*/
|
||||
If (LEqual (Arg2, One)) {
|
||||
CreateQWordField (NBUF, ^NHLT._MIN, NBAS)
|
||||
CreateQWordField (NBUF, ^NHLT._MAX, NMAS)
|
||||
CreateQWordField (NBUF, ^NHLT._LEN, NLEN)
|
||||
Store (NHLA, NBAS)
|
||||
Store (NHLA, NMAS)
|
||||
Store (NHLL, NLEN)
|
||||
Return (NBUF)
|
||||
}
|
||||
}
|
||||
|
||||
Return (Buffer (One) { 0x00 })
|
||||
}
|
||||
}
|
||||
52
arch/x86/include/asm/arch-apollolake/acpi/pci_irqs.asl
Normal file
52
arch/x86/include/asm/arch-apollolake/acpi/pci_irqs.asl
Normal file
|
|
@ -0,0 +1,52 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* Copyright (C) 2016 Intel Corp.
|
||||
* (Written by Lance Zhao <lijian.zhao@intel.com> for Intel Corp.)
|
||||
*/
|
||||
|
||||
#include "soc_int.asl"
|
||||
|
||||
Method(_PRT)
|
||||
{
|
||||
Return(Package() {
|
||||
|
||||
Package(){0x0000FFFF, 0, 0, NPK_INT},
|
||||
Package(){0x0000FFFF, 1, 0, PUNIT_INT},
|
||||
Package(){0x0002FFFF, 0, 0, GEN_INT},
|
||||
Package(){0x0003FFFF, 0, 0, IUNIT_INT},
|
||||
Package(){0x000DFFFF, 1, 0, PMC_INT},
|
||||
Package(){0x000EFFFF, 0, 0, AUDIO_INT},
|
||||
Package(){0x000FFFFF, 0, 0, CSE_INT},
|
||||
Package(){0x0011FFFF, 0, 0, ISH_INT},
|
||||
Package(){0x0012FFFF, 0, 0, SATA_INT},
|
||||
Package(){0x0013FFFF, 0, 0, PIRQA_INT},
|
||||
Package(){0x0013FFFF, 1, 0, PIRQB_INT},
|
||||
Package(){0x0013FFFF, 2, 0, PIRQC_INT},
|
||||
Package(){0x0013FFFF, 3, 0, PIRQD_INT},
|
||||
Package(){0x0014FFFF, 0, 0, PIRQB_INT},
|
||||
Package(){0x0014FFFF, 1, 0, PIRQC_INT},
|
||||
Package(){0x0014FFFF, 2, 0, PIRQD_INT},
|
||||
Package(){0x0014FFFF, 3, 0, PIRQA_INT},
|
||||
Package(){0x0015FFFF, 0, 0, XHCI_INT},
|
||||
Package(){0x0015FFFF, 1, 0, XDCI_INT},
|
||||
Package(){0x0016FFFF, 0, 0, I2C0_INT},
|
||||
Package(){0x0016FFFF, 1, 0, I2C1_INT},
|
||||
Package(){0x0016FFFF, 2, 0, I2C2_INT},
|
||||
Package(){0x0016FFFF, 3, 0, I2C3_INT},
|
||||
Package(){0x0017FFFF, 0, 0, I2C4_INT},
|
||||
Package(){0x0017FFFF, 1, 0, I2C5_INT},
|
||||
Package(){0x0017FFFF, 2, 0, I2C6_INT},
|
||||
Package(){0x0017FFFF, 3, 0, I2C7_INT},
|
||||
Package(){0x0018FFFF, 0, 0, UART0_INT},
|
||||
Package(){0x0018FFFF, 1, 0, UART1_INT},
|
||||
Package(){0x0018FFFF, 2, 0, UART2_INT},
|
||||
Package(){0x0018FFFF, 3, 0, UART3_INT},
|
||||
Package(){0x0019FFFF, 0, 0, SPI0_INT},
|
||||
Package(){0x0019FFFF, 1, 0, SPI1_INT},
|
||||
Package(){0x0019FFFF, 2, 0, SPI2_INT},
|
||||
Package(){0x001BFFFF, 0, 0, SDCARD_INT},
|
||||
Package(){0x001CFFFF, 0, 0, EMMC_INT},
|
||||
Package(){0x001EFFFF, 0, 0, SDIO_INT},
|
||||
Package(){0x001FFFFF, 1, 0, SMBUS_INT},
|
||||
})
|
||||
}
|
||||
22
arch/x86/include/asm/arch-apollolake/acpi/pcie.asl
Normal file
22
arch/x86/include/asm/arch-apollolake/acpi/pcie.asl
Normal file
|
|
@ -0,0 +1,22 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
/*
|
||||
* Copyright (C) 2016 Intel Corporation
|
||||
*/
|
||||
|
||||
/* PCIe Ports */
|
||||
|
||||
Device (RP01)
|
||||
{
|
||||
Name (_ADR, 0x00140000)
|
||||
Name (_DDN, "PCIe-B 0")
|
||||
|
||||
#include "pcie_port.asl"
|
||||
}
|
||||
|
||||
Device (RP03)
|
||||
{
|
||||
Name (_ADR, 0x00130000)
|
||||
Name (_DDN, "PCIe-A 0")
|
||||
|
||||
#include "pcie_port.asl"
|
||||
}
|
||||
113
arch/x86/include/asm/arch-apollolake/acpi/pcie_port.asl
Normal file
113
arch/x86/include/asm/arch-apollolake/acpi/pcie_port.asl
Normal file
|
|
@ -0,0 +1,113 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
/*
|
||||
* Copyright (C) 2016 Intel Corporation
|
||||
*/
|
||||
|
||||
/* Include in each PCIe Root Port device */
|
||||
|
||||
/* lowest D-state supported by
|
||||
* PCIe root port during S0 state
|
||||
*/
|
||||
Name (_S0W, 4)
|
||||
|
||||
Name (PDST, 0) /* present Detect status */
|
||||
|
||||
/* Dynamic Opregion needed to access registers
|
||||
* when the controller is in D3 cold
|
||||
*/
|
||||
OperationRegion (PX01, PCI_Config, 0x00, 0xFF)
|
||||
Field (PX01, AnyAcc, NoLock, Preserve)
|
||||
{
|
||||
Offset(0x5A),
|
||||
, 6,
|
||||
PDS, 1, /* 6, Presence detect Change */
|
||||
Offset(0xE2), /* RPPGEN - Root Port Power Gating Enable */
|
||||
, 2,
|
||||
L23E, 1, /* 2, L23_Rdy Entry Request (L23ER) */
|
||||
L23R, 1, /* 3, L23_Rdy to Detect Transition (L23R2DT) */
|
||||
Offset(0xF4), /* BLKPLLEN */
|
||||
, 10,
|
||||
BPLL, 1,
|
||||
}
|
||||
|
||||
OperationRegion (PX02, PCI_Config, 0x338, 0x4)
|
||||
Field (PX02, AnyAcc, NoLock, Preserve)
|
||||
{
|
||||
, 26,
|
||||
BDQA, 1 /* BLKDQDA */
|
||||
}
|
||||
|
||||
PowerResource (PXP, 0, 0)
|
||||
{
|
||||
/* Define the PowerResource for PCIe slot */
|
||||
Method (_STA, 0, Serialized)
|
||||
{
|
||||
Store (PDS, PDST)
|
||||
If (LEqual (PDS, 1)) {
|
||||
Return (0xf)
|
||||
} Else {
|
||||
Return (0)
|
||||
}
|
||||
}
|
||||
|
||||
Method (_ON, 0, Serialized)
|
||||
{
|
||||
If (LAnd (LEqual (PDST, 1), LNotEqual (\PRT0, 0))) {
|
||||
/* Enter this condition if device
|
||||
* is connected
|
||||
*/
|
||||
|
||||
/* De-assert PERST */
|
||||
\_SB.PCI0.PRDA (\PRT0)
|
||||
|
||||
Store (0, BDQA) /* Set BLKDQDA to 0 */
|
||||
Store (0, BPLL) /* Set BLKPLLEN to 0 */
|
||||
|
||||
/* Set L23_Rdy to Detect Transition
|
||||
* (L23R2DT)
|
||||
*/
|
||||
Store (1, L23R)
|
||||
Sleep (16)
|
||||
Store (0, Local0)
|
||||
|
||||
/* Delay for transition Detect
|
||||
* and link to train
|
||||
*/
|
||||
While (L23R) {
|
||||
If (Lgreater (Local0, 4)) {
|
||||
Break
|
||||
}
|
||||
Sleep (16)
|
||||
Increment (Local0)
|
||||
}
|
||||
} /* End PDS condition check */
|
||||
}
|
||||
|
||||
Method (_OFF, 0, Serialized)
|
||||
{
|
||||
/* Set L23_Rdy Entry Request (L23ER) */
|
||||
If (LAnd (LEqual (PDST, 1), LNotEqual (\PRT0, 0))) {
|
||||
/* enter this condition if device
|
||||
* is connected
|
||||
*/
|
||||
Store (1, L23E)
|
||||
Sleep (16)
|
||||
Store (0, Local0)
|
||||
While (L23E) {
|
||||
If (Lgreater (Local0, 4)) {
|
||||
Break
|
||||
}
|
||||
Sleep (16)
|
||||
Increment (Local0)
|
||||
}
|
||||
Store (1, BDQA) /* Set BLKDQDA to 1 */
|
||||
Store (1, BPLL) /* Set BLKPLLEN to 1 */
|
||||
|
||||
/* Assert PERST */
|
||||
\_SB.PCI0.PRAS (\PRT0)
|
||||
} /* End PDS condition check */
|
||||
} /* End of Method_OFF */
|
||||
} /* End PXP */
|
||||
|
||||
Name(_PR0, Package() { PXP })
|
||||
Name(_PR3, Package() { PXP })
|
||||
10
arch/x86/include/asm/arch-apollolake/acpi/platform.asl
Normal file
10
arch/x86/include/asm/arch-apollolake/acpi/platform.asl
Normal file
|
|
@ -0,0 +1,10 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
/*
|
||||
* Copyright (C) 2007-2009 coresystems GmbH
|
||||
* Copyright (C) 2012 Google Inc.
|
||||
* Copyright (C) 2016 Intel Corp
|
||||
*/
|
||||
|
||||
/* Enable ACPI _SWS methods */
|
||||
#include <soc/intel/common/acpi/acpi_wake_source.asl>
|
||||
#include <soc/intel/common/acpi/platform.asl>
|
||||
49
arch/x86/include/asm/arch-apollolake/acpi/pmc_ipc.asl
Normal file
49
arch/x86/include/asm/arch-apollolake/acpi/pmc_ipc.asl
Normal file
|
|
@ -0,0 +1,49 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
/*
|
||||
* Copyright (C) 2016 Intel Corp.
|
||||
*/
|
||||
|
||||
#include <asm/arch/iomap.h>
|
||||
|
||||
#define MAILBOX_DATA 0x7080
|
||||
#define MAILBOX_INTF 0x7084
|
||||
#define PMIO_LENGTH 0x80
|
||||
#define PMIO_LIMIT 0x480
|
||||
|
||||
scope (\_SB) {
|
||||
Device (IPC1)
|
||||
{
|
||||
Name (_HID, "INT34D2")
|
||||
Name (_CID, "INT34D2")
|
||||
Name (_DDN, "Intel(R) IPC1 Controller")
|
||||
Name (RBUF, ResourceTemplate ()
|
||||
{
|
||||
Memory32Fixed (ReadWrite, 0x0, 0x2000, IBAR)
|
||||
Memory32Fixed (ReadWrite, 0x0, 0x4, MDAT)
|
||||
Memory32Fixed (ReadWrite, 0x0, 0x4, MINF)
|
||||
IO (Decode16, IOMAP_ACPI_BASE, PMIO_LIMIT,
|
||||
0x04, PMIO_LENGTH)
|
||||
Memory32Fixed (ReadWrite, 0x0, 0x2000, SBAR)
|
||||
Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive, , , )
|
||||
{
|
||||
PMC_INT
|
||||
}
|
||||
})
|
||||
|
||||
Method (_CRS, 0x0, NotSerialized)
|
||||
{
|
||||
CreateDwordField (^RBUF, ^IBAR._BAS, IBAS)
|
||||
Store (PMC_BAR0, IBAS)
|
||||
|
||||
CreateDwordField (^RBUF, ^MDAT._BAS, MDBA)
|
||||
Store (MCH_BASE_ADDRESS + MAILBOX_DATA, MDBA)
|
||||
CreateDwordField (^RBUF, ^MINF._BAS, MIBA)
|
||||
Store (MCH_BASE_ADDRESS + MAILBOX_INTF, MIBA)
|
||||
|
||||
CreateDwordField (^RBUF, ^SBAR._BAS, SBAS)
|
||||
Store (SRAM_BASE_0, SBAS)
|
||||
|
||||
Return (^RBUF)
|
||||
}
|
||||
}
|
||||
}
|
||||
173
arch/x86/include/asm/arch-apollolake/acpi/scs.asl
Normal file
173
arch/x86/include/asm/arch-apollolake/acpi/scs.asl
Normal file
|
|
@ -0,0 +1,173 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
/*
|
||||
* Copyright (C) 2016 Intel Corporation.
|
||||
*/
|
||||
|
||||
Scope (\_SB.PCI0) {
|
||||
/* 0xD6- is the port address */
|
||||
/* 0x600- is the dynamic clock gating control register offset (GENR) */
|
||||
OperationRegion (SBMM, SystemMemory,
|
||||
Or ( Or (IOMAP_P2SB_BAR,
|
||||
ShiftLeft(0xD6, PCR_PORTID_SHIFT)), 0x0600), 0x18)
|
||||
Field (SBMM, DWordAcc, NoLock, Preserve)
|
||||
{
|
||||
GENR, 32,
|
||||
Offset (0x08),
|
||||
, 5, /* bit[5] represents Force Card Detect SD Card */
|
||||
GRR3, 1, /* GPPRVRW3 for SD Card detect Bypass. It's active high */
|
||||
}
|
||||
|
||||
/* SCC power gate control method, this method must be serialized as
|
||||
* multiple device will control the GENR register
|
||||
*
|
||||
* Arguments: (2)
|
||||
* Arg0: 0-AND 1-OR
|
||||
* Arg1: Value
|
||||
*/
|
||||
Method (SCPG, 2, Serialized)
|
||||
{
|
||||
if (LEqual(Arg0, 0x1)) {
|
||||
Or (^GENR, Arg1, ^GENR)
|
||||
} ElseIf (LEqual(Arg0, 0x0)){
|
||||
And (^GENR, Arg1, ^GENR)
|
||||
}
|
||||
}
|
||||
|
||||
/* eMMC */
|
||||
Device (SDHA) {
|
||||
Name (_ADR, 0x001C0000)
|
||||
Name (_DDN, "Intel(R) eMMC Controller - 80865ACC")
|
||||
Name (UUID, ToUUID ("E5C937D0-3553-4D7A-9117-EA4D19C3434D"))
|
||||
|
||||
/*
|
||||
* Device Specific Method
|
||||
* Arg0 - UUID
|
||||
* Arg1 - Revision
|
||||
* Arg2 - Function Index
|
||||
*/
|
||||
Method (_DSM, 4)
|
||||
{
|
||||
If (LEqual (Arg0, ^UUID)) {
|
||||
/*
|
||||
* Function 9: Device Readiness Durations
|
||||
* Returns a package of five integers covering
|
||||
* various device related delays in PCIe Base Spec.
|
||||
*/
|
||||
If (LEqual (Arg2, 9)) {
|
||||
/*
|
||||
* Function 9 support for revision 3.
|
||||
* ECN link for function definitions
|
||||
* [https://pcisig.com/sites/default/files/
|
||||
* specification_documents/
|
||||
* ECN_fw_latency_optimization_final.pdf]
|
||||
*/
|
||||
If (LEqual (Arg1, 3)) {
|
||||
/*
|
||||
* Integer 0: FW reset time.
|
||||
* Integer 1: FW data link up time.
|
||||
* Integer 2: FW functional level reset
|
||||
* time.
|
||||
* Integer 3: FW D3 hot to D0 time.
|
||||
* Integer 4: FW VF enable time.
|
||||
* set ACPI constant Ones for elements
|
||||
* where overriding the default value
|
||||
* is not desired.
|
||||
*/
|
||||
Return (Package (5) {0, Ones, Ones,
|
||||
Ones, Ones})
|
||||
}
|
||||
}
|
||||
}
|
||||
Return (Buffer() { 0x00 })
|
||||
}
|
||||
|
||||
Method (_PS0, 0, NotSerialized)
|
||||
{
|
||||
/* Clear clock gate
|
||||
* Clear bit 6 and 0
|
||||
*/
|
||||
^^SCPG(0,0xFFFFFFBE)
|
||||
/* Sleep 2 ms */
|
||||
Sleep (2)
|
||||
}
|
||||
|
||||
Method (_PS3, 0, NotSerialized)
|
||||
{
|
||||
/* Enable power gate
|
||||
* Restore clock gate
|
||||
* Restore bit 6 and 0
|
||||
*/
|
||||
^^SCPG(1,0x00000041)
|
||||
}
|
||||
|
||||
Device (CARD)
|
||||
{
|
||||
Name (_ADR, 0x00000008)
|
||||
Method (_RMV, 0, NotSerialized)
|
||||
{
|
||||
Return (0)
|
||||
}
|
||||
}
|
||||
} /* Device (SDHA) */
|
||||
|
||||
/* SD CARD */
|
||||
Device (SDCD)
|
||||
{
|
||||
Name (_ADR, 0x001B0000)
|
||||
Name (_S0W, 4) /* _S0W: S0 Device Wake State */
|
||||
Name (SCD0, 0) /* Store SD_CD DW0 address */
|
||||
|
||||
/* Set the host ownership of sdcard cd during kernel boot */
|
||||
Method (_INI, 0)
|
||||
{
|
||||
/* Check SDCard CD port is valid */
|
||||
If (LAnd (LNotEqual (\SCDP, 0), LNotEqual (\SCDO, 0) ))
|
||||
{
|
||||
/* Store DW0 address of SD_CD */
|
||||
Store (GDW0 (\SCDP, \SCDO), SCD0)
|
||||
/* Get the current SD_CD ownership */
|
||||
Store (\_SB.GHO (\SCDP, \SCDO), Local0)
|
||||
/* Set host ownership as GPIO in HOSTSW_OWN reg */
|
||||
Or (Local0, ShiftLeft (1, Mod (\SCDO, 32)), Local0)
|
||||
\_SB.SHO (\SCDP, \SCDO, Local0)
|
||||
}
|
||||
}
|
||||
|
||||
Method (_PS0, 0, NotSerialized)
|
||||
{
|
||||
/* Check SDCard CD port is valid */
|
||||
If (LAnd (LNotEqual (\SCDP, 0), LNotEqual (\SCDO, 0) ))
|
||||
{
|
||||
/* Store DW0 into local0 to get rxstate of GPIO */
|
||||
Store (\_SB.GPC0 (SCD0), Local0)
|
||||
/* Extract rxstate [bit 1] of sdcard card detect pin */
|
||||
And (Local0, PAD_CFG0_RX_STATE, Local0)
|
||||
/* If the sdcard is present, rxstate is low.
|
||||
* If sdcard is not present, rxstate is High.
|
||||
* Write the inverted value of rxstate to GRR3.
|
||||
*/
|
||||
If (LEqual (Local0, 0)) {
|
||||
Store (1, ^^GRR3)
|
||||
} Else {
|
||||
Store (0, ^^GRR3)
|
||||
}
|
||||
Sleep (2)
|
||||
}
|
||||
}
|
||||
|
||||
Method (_PS3, 0, NotSerialized)
|
||||
{
|
||||
/* Clear GRR3 to Power Gate SD Controller */
|
||||
Store (0, ^^GRR3)
|
||||
}
|
||||
|
||||
Device (CARD)
|
||||
{
|
||||
Name (_ADR, 0x00000008)
|
||||
Method (_RMV, 0, NotSerialized)
|
||||
{
|
||||
Return (1)
|
||||
}
|
||||
}
|
||||
} /* Device (SDCD) */
|
||||
}
|
||||
50
arch/x86/include/asm/arch-apollolake/acpi/soc_int.asl
Normal file
50
arch/x86/include/asm/arch-apollolake/acpi/soc_int.asl
Normal file
|
|
@ -0,0 +1,50 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* Copyright (C) 2016 Intel Corp.
|
||||
* (Written by Lance Zhao <lijian.zhao@intel.com> for Intel Corp.)
|
||||
*/
|
||||
|
||||
#ifndef _SOC_INT_DEFINE_ASL_
|
||||
#define _SOC_INT_DEFINE_ASL_
|
||||
|
||||
#define SDCARD_INT 3 /* Need to be shared by PMC and SCC only*/
|
||||
#define UART0_INT 4 /* Need to be shared by PMC and SCC only*/
|
||||
#define UART1_INT 5 /* Need to be shared by PMC and SCC only*/
|
||||
#define UART2_INT 6 /* Need to be shared by PMC and SCC only*/
|
||||
#define UART3_INT 7 /* Need to be shared by PMC and SCC only*/
|
||||
#define XDCI_INT 13 /* Need to be shared by PMC and SCC only*/
|
||||
#define GPIO_BANK_INT 14
|
||||
#define NPK_INT 16
|
||||
#define PIRQA_INT 16
|
||||
#define PIRQB_INT 17
|
||||
#define PIRQC_INT 18
|
||||
#define SATA_INT 19
|
||||
#define GEN_INT 19
|
||||
#define PIRQD_INT 19
|
||||
#define XHCI_INT 17 /* Need to be shared by PMC and SCC only*/
|
||||
#define SMBUS_INT 20 /* PIRQE */
|
||||
#define CSE_INT 20 /* PIRQE */
|
||||
#define IUNIT_INT 21 /* PIRQF */
|
||||
#define PIRQF_INT 21
|
||||
#define PIRQG_INT 22
|
||||
#define PUNIT_INT 24
|
||||
#define AUDIO_INT 25
|
||||
#define ISH_INT 26
|
||||
#define I2C0_INT 27
|
||||
#define I2C1_INT 28
|
||||
#define I2C2_INT 29
|
||||
#define I2C3_INT 30
|
||||
#define I2C4_INT 31
|
||||
#define I2C5_INT 32
|
||||
#define I2C6_INT 33
|
||||
#define I2C7_INT 34
|
||||
#define SPI0_INT 35
|
||||
#define SPI1_INT 36
|
||||
#define SPI2_INT 37
|
||||
#define UFS_INT 38
|
||||
#define EMMC_INT 39
|
||||
#define PMC_INT 40
|
||||
#define SDIO_INT 42
|
||||
#define CNVI_INT 44
|
||||
|
||||
#endif /* _SOC_INT_DEFINE_ASL_ */
|
||||
34
arch/x86/include/asm/arch-apollolake/acpi/southbridge.asl
Normal file
34
arch/x86/include/asm/arch-apollolake/acpi/southbridge.asl
Normal file
|
|
@ -0,0 +1,34 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* Copyright (C) 2016 Intel Corp.
|
||||
* (Written by Lance Zhao <lijian.zhao@intel.com> for Intel Corp.)
|
||||
*/
|
||||
|
||||
#include <p2sb.h>
|
||||
#include <asm/arch/gpe.h>
|
||||
|
||||
/* PCIE device */
|
||||
#include "pcie.asl"
|
||||
|
||||
/* LPSS device */
|
||||
#include "lpss.asl"
|
||||
|
||||
/* PCI IRQ assignment */
|
||||
#include "pci_irqs.asl"
|
||||
|
||||
/* GPIO controller */
|
||||
#include "gpio.asl"
|
||||
|
||||
#include "xhci.asl"
|
||||
|
||||
/* LPC */
|
||||
#include <asm/acpi/lpc.asl>
|
||||
|
||||
/* eMMC */
|
||||
#include "scs.asl"
|
||||
|
||||
/* PMC IPC controller */
|
||||
#include "pmc_ipc.asl"
|
||||
|
||||
/* PCI _OSC */
|
||||
#include <asm/acpi/pci_osc.asl>
|
||||
33
arch/x86/include/asm/arch-apollolake/acpi/xhci.asl
Normal file
33
arch/x86/include/asm/arch-apollolake/acpi/xhci.asl
Normal file
|
|
@ -0,0 +1,33 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
/*
|
||||
* Copyright (C) 2016 Intel Corporation.
|
||||
*/
|
||||
|
||||
/* XHCI Controller 0:15.0 */
|
||||
Device (XHCI) {
|
||||
Name (_ADR, 0x00150000) /* Device 21, Function 0 */
|
||||
|
||||
Name (_S3D, 3) /* D3 supported in S3 */
|
||||
Name (_S0W, 3) /* D3 can wake device in S0 */
|
||||
Name (_S3W, 3) /* D3 can wake system from S3 */
|
||||
|
||||
/* Declare XHCI GPE status and enable bits are bit 13 */
|
||||
Name (_PRW, Package() { GPE0A_XHCI_PME_STS, 3 })
|
||||
|
||||
Method (_STA, 0)
|
||||
{
|
||||
Return (0xF)
|
||||
}
|
||||
|
||||
Device (RHUB)
|
||||
{
|
||||
/* Root Hub */
|
||||
Name (_ADR, Zero)
|
||||
|
||||
#if IS_ENABLED(CONFIG_SOC_INTEL_GLK)
|
||||
#include "xhci_glk_ports.asl"
|
||||
#else
|
||||
#include "xhci_apl_ports.asl"
|
||||
#endif
|
||||
}
|
||||
}
|
||||
23
arch/x86/include/asm/arch-apollolake/acpi/xhci_apl_ports.asl
Normal file
23
arch/x86/include/asm/arch-apollolake/acpi/xhci_apl_ports.asl
Normal file
|
|
@ -0,0 +1,23 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* Copyright 2019 Google LLC.
|
||||
* Copyright 2019 Intel Corp.
|
||||
*/
|
||||
|
||||
/* USB2 */
|
||||
Device (HS01) { Name (_ADR, 1) }
|
||||
Device (HS02) { Name (_ADR, 2) }
|
||||
Device (HS03) { Name (_ADR, 3) }
|
||||
Device (HS04) { Name (_ADR, 4) }
|
||||
Device (HS05) { Name (_ADR, 5) }
|
||||
Device (HS06) { Name (_ADR, 6) }
|
||||
Device (HS07) { Name (_ADR, 7) }
|
||||
Device (HS08) { Name (_ADR, 8) }
|
||||
|
||||
/* USB3 */
|
||||
Device (SS01) { Name (_ADR, 9) }
|
||||
Device (SS02) { Name (_ADR, 10) }
|
||||
Device (SS03) { Name (_ADR, 11) }
|
||||
Device (SS04) { Name (_ADR, 12) }
|
||||
Device (SS05) { Name (_ADR, 13) }
|
||||
Device (SS06) { Name (_ADR, 14) }
|
||||
24
arch/x86/include/asm/arch-apollolake/acpi/xhci_glk_ports.asl
Normal file
24
arch/x86/include/asm/arch-apollolake/acpi/xhci_glk_ports.asl
Normal file
|
|
@ -0,0 +1,24 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* Copyright 2019 Google LLC.
|
||||
* Copyright 2019 Intel Corp.
|
||||
*/
|
||||
|
||||
/* USB2 */
|
||||
Device (HS01) { Name (_ADR, 1) }
|
||||
Device (HS02) { Name (_ADR, 2) }
|
||||
Device (HS03) { Name (_ADR, 3) }
|
||||
Device (HS04) { Name (_ADR, 4) }
|
||||
Device (HS05) { Name (_ADR, 5) }
|
||||
Device (HS06) { Name (_ADR, 6) }
|
||||
Device (HS07) { Name (_ADR, 7) }
|
||||
Device (HS08) { Name (_ADR, 8) }
|
||||
Device (HS09) { Name (_ADR, 9) }
|
||||
|
||||
/* USB3 */
|
||||
Device (SS01) { Name (_ADR, 10) }
|
||||
Device (SS02) { Name (_ADR, 11) }
|
||||
Device (SS03) { Name (_ADR, 12) }
|
||||
Device (SS04) { Name (_ADR, 13) }
|
||||
Device (SS05) { Name (_ADR, 14) }
|
||||
Device (SS06) { Name (_ADR, 15) }
|
||||
Loading…
Reference in New Issue
Block a user