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net: sun8i_emac: Fix build for non-H3/H5 SoCs

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Only the H3/H5 SoCs have an internal PHY and its related clock and
reset controls.

Use an #ifdef to guard the internal PHY control code block so it
can be built for other SoCs, such as the A83T or A64.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Reviewed-by: Joe Hershberger <joe.hershberger@ni.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
This commit is contained in:
Chen-Yu Tsai 2017-09-22 15:26:33 +08:00 committed by Jagan Teki
parent 60567a320f
commit 13ae2a40e7
1 changed files with 3 additions and 0 deletions
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3
drivers/net/sun8i_emac.c
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@ -604,6 +604,8 @@ static void sun8i_emac_board_setup(struct emac_eth_dev *priv)
{
struct sunxi_ccm_reg *ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
#ifdef CONFIG_MACH_SUNXI_H3_H5
/* Only H3/H5 have clock controls for internal EPHY */
if (priv->use_internal_phy) {
/* Set clock gating for ephy */
setbits_le32(&ccm->bus_gate4, BIT(AHB_GATE_OFFSET_EPHY));
@ -611,6 +613,7 @@ static void sun8i_emac_board_setup(struct emac_eth_dev *priv)
/* Deassert EPHY */
setbits_le32(&ccm->ahb_reset2_cfg, BIT(AHB_RESET_OFFSET_EPHY));
}
#endif
/* Set clock gating for emac */
setbits_le32(&ccm->ahb_gate0, BIT(AHB_GATE_OFFSET_GMAC));