mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-06-09 23:36:03 +09:00
overo: add SPL support
* implementation based on ti beagleboard/omap3evm * timing data and i2c workaround for revision 0 boards taken from x-loader * run-tested with overo revision 0 and 1 / boot from NAND and SDcard * run-tested with x-loader Signed-off-by: Andreas Müller <schnitzeltony@gmx.de> Signed-off-by: Tom Rini <trini@ti.com>
This commit is contained in:
Andreas Müller
Albert ARIBAUD
parent
761ca31e47
commit
137703b811
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@ -123,6 +123,32 @@ enum {
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V_MCFG_BANKALLOCATION_RBC | \
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V_MCFG_B32NOT16_32 | V_MCFG_DEEPPD_EN | V_MCFG_RAMTYPE_DDR
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/* Hynix part of Overo (165MHz optimized) 6.06ns */
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#define HYNIX_TDAL_165 6
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#define HYNIX_TDPL_165 3
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#define HYNIX_TRRD_165 2
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#define HYNIX_TRCD_165 3
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#define HYNIX_TRP_165 3
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#define HYNIX_TRAS_165 7
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#define HYNIX_TRC_165 10
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#define HYNIX_TRFC_165 21
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#define HYNIX_V_ACTIMA_165 \
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ACTIM_CTRLA(HYNIX_TRFC_165, HYNIX_TRC_165, \
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HYNIX_TRAS_165, HYNIX_TRP_165, \
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HYNIX_TRCD_165, HYNIX_TRRD_165, \
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HYNIX_TDPL_165, HYNIX_TDAL_165)
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#define HYNIX_TWTR_165 1
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#define HYNIX_TCKE_165 1
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#define HYNIX_TXP_165 2
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#define HYNIX_XSR_165 24
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#define HYNIX_V_ACTIMB_165 \
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ACTIM_CTRLB(HYNIX_TWTR_165, HYNIX_TCKE_165, \
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HYNIX_TXP_165, HYNIX_XSR_165)
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#define HYNIX_RASWIDTH_165 0x2
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#define HYNIX_V_MCFG_165(size) MCFG((size), HYNIX_RASWIDTH_165)
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/* Hynix part of AM/DM37xEVM (200MHz optimized) */
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#define HYNIX_TDAL_200 6
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#define HYNIX_TDPL_200 3
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@ -1,28 +0,0 @@
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#
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# Overo uses OMAP3 (ARM-CortexA8) cpu
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#
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# See file CREDITS for list of people who contributed to this
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# project.
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#
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# This program is free software; you can redistribute it and/or
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# modify it under the terms of the GNU General Public License as
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# published by the Free Software Foundation; either version 2 of
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# the License, or (at your option) any later version.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with this program; if not, write to the Free Software
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# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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# MA 02111-1307 USA
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#
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# Physical Address:
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# 8000'0000 (bank0)
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# A000/0000 (bank1)
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# Linux-Kernel is expected to be at 8000'8000, entry 8000'8000
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# (mem base + reserved)
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CONFIG_SYS_TEXT_BASE = 0x80008000
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@ -31,6 +31,7 @@
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#include <common.h>
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#include <netdev.h>
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#include <twl4030.h>
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#include <linux/mtd/nand.h>
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#include <asm/io.h>
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#include <asm/arch/mmc_host_def.h>
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#include <asm/arch/mux.h>
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@ -99,6 +100,16 @@ int board_init(void)
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return 0;
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}
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/*
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* Routine: omap_rev_string
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* Description: For SPL builds output board rev
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*/
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#ifdef CONFIG_SPL_BUILD
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void omap_rev_string(void)
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{
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}
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#endif
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/*
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* Routine: get_board_revision
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* Description: Returns the board revision
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@ -107,6 +118,20 @@ int get_board_revision(void)
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{
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int revision;
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#ifdef CONFIG_DRIVER_OMAP34XX_I2C
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unsigned char data;
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/* board revisions <= R2410 connect 4030 irq_1 to gpio112 */
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/* these boards should return a revision number of 0 */
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/* the code below forces a 4030 RTC irq to ensure that gpio112 is low */
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i2c_set_bus_num(TWL4030_I2C_BUS);
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data = 0x01;
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i2c_write(0x4B, 0x29, 1, &data, 1);
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data = 0x0c;
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i2c_write(0x4B, 0x2b, 1, &data, 1);
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i2c_read(0x4B, 0x2a, 1, &data, 1);
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#endif
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if (!gpio_request(112, "") &&
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!gpio_request(113, "") &&
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!gpio_request(115, "")) {
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@ -126,6 +151,44 @@ int get_board_revision(void)
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return revision;
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}
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#ifdef CONFIG_SPL_BUILD
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/*
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* Routine: get_board_mem_timings
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* Description: If we use SPL then there is no x-loader nor config header
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* so we have to setup the DDR timings ourself on both banks.
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*/
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void get_board_mem_timings(u32 *mcfg, u32 *ctrla, u32 *ctrlb, u32 *rfr_ctrl,
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u32 *mr)
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{
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*mr = MICRON_V_MR_165;
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switch (get_board_revision()) {
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case REVISION_0: /* Micron 1286MB/256MB, 1/2 banks of 128MB */
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*mcfg = MICRON_V_MCFG_165(128 << 20);
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*ctrla = MICRON_V_ACTIMA_165;
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*ctrlb = MICRON_V_ACTIMB_165;
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*rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
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break;
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case REVISION_1: /* Micron 256MB/512MB, 1/2 banks of 256MB */
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*mcfg = MICRON_V_MCFG_165(256 << 20);
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*ctrla = MICRON_V_ACTIMA_165;
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*ctrlb = MICRON_V_ACTIMB_165;
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*rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
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break;
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case REVISION_2: /* Hynix 256MB/512MB, 1/2 banks of 256MB */
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*mcfg = HYNIX_V_MCFG_165(256 << 20);
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*ctrla = HYNIX_V_ACTIMA_165;
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*ctrlb = HYNIX_V_ACTIMB_165;
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*rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
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break;
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default:
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*mcfg = MICRON_V_MCFG_165(128 << 20);
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*ctrla = MICRON_V_ACTIMA_165;
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*ctrlb = MICRON_V_ACTIMB_165;
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*rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
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}
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}
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#endif
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/*
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* Routine: get_sdio2_config
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* Description: Return information about the wifi module connection
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@ -337,7 +400,7 @@ int board_eth_init(bd_t *bis)
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return rc;
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}
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#ifdef CONFIG_GENERIC_MMC
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#if defined(CONFIG_GENERIC_MMC) && !defined(CONFIG_SPL_BUILD)
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int board_mmc_init(bd_t *bis)
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{
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omap_mmc_init(0);
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@ -33,6 +33,11 @@ const omap3_sysinfo sysinfo = {
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#endif
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};
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/* overo revisions */
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#define REVISION_0 0x0
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#define REVISION_1 0x1
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#define REVISION_2 0x2
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/*
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* IEN - Input Enable
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* IDIS - Input Disable
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@ -285,6 +285,11 @@
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#endif /* (CONFIG_CMD_NET) */
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/*
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* Leave it at 0x80008000 to allow booting new u-boot.bin with X-loader
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* and older u-boot.bin with the new U-Boot SPL.
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*/
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#define CONFIG_SYS_TEXT_BASE 0x80008000
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#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
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#define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800
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#define CONFIG_SYS_INIT_RAM_SIZE 0x800
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@ -294,4 +299,51 @@
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#define CONFIG_SYS_CACHELINE_SIZE 64
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/* Defines for SPL */
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#define CONFIG_SPL
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#define CONFIG_SPL_NAND_SIMPLE
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#define CONFIG_SPL_TEXT_BASE 0x40200800
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#define CONFIG_SPL_MAX_SIZE (45 * 1024)
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#define CONFIG_SPL_STACK LOW_LEVEL_SRAM_STACK
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/* move malloc and bss high to prevent clashing with the main image */
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#define CONFIG_SYS_SPL_MALLOC_START 0x87000000
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#define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000
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#define CONFIG_SPL_BSS_START_ADDR 0x87080000 /* end of minimum RAM */
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#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */
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#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */
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#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x200 /* 256 KB */
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#define CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION 1
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#define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME "u-boot.img"
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#define CONFIG_SPL_LIBCOMMON_SUPPORT
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#define CONFIG_SPL_LIBDISK_SUPPORT
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#define CONFIG_SPL_I2C_SUPPORT
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#define CONFIG_SPL_LIBGENERIC_SUPPORT
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#define CONFIG_SPL_MMC_SUPPORT
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#define CONFIG_SPL_FAT_SUPPORT
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#define CONFIG_SPL_SERIAL_SUPPORT
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#define CONFIG_SPL_NAND_SUPPORT
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#define CONFIG_SPL_POWER_SUPPORT
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#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds"
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/* NAND boot config */
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#define CONFIG_SYS_NAND_5_ADDR_CYCLE
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#define CONFIG_SYS_NAND_PAGE_COUNT 64
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#define CONFIG_SYS_NAND_PAGE_SIZE 2048
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#define CONFIG_SYS_NAND_OOBSIZE 64
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#define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024)
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#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS
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#define CONFIG_SYS_NAND_ECCPOS {2, 3, 4, 5, 6, 7, 8, 9,\
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10, 11, 12, 13}
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#define CONFIG_SYS_NAND_ECCSIZE 512
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#define CONFIG_SYS_NAND_ECCBYTES 3
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#define CONFIG_SYS_NAND_ECCSTEPS (CONFIG_SYS_NAND_PAGE_SIZE / \
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CONFIG_SYS_NAND_ECCSIZE)
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#define CONFIG_SYS_NAND_ECCTOTAL (CONFIG_SYS_NAND_ECCBYTES * \
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CONFIG_SYS_NAND_ECCSTEPS)
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#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
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#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000
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#endif /* __CONFIG_H */
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