brain-hackers_pepepper-mirror/u-boot-brain
1
0
Fork 0
mirror of https://github.com/brain-hackers/u-boot-brain synced 2024-06-09 23:36:03 +09:00
Code Issues Projects Releases Wiki Activity

arm: socfpga: soc64: Initialize timer in SPL only

Browse Source 
Timer only need to be initialized once in SPL.
This patch remove the redundancy of initializing the
timer again in U-Boot proper

Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>
Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
This commit is contained in:
Chee Hong Ang 2020-07-10 23:53:13 +08:00 committed by Ley Foon Tan
parent 464ca99f8e
commit 12cc44884b
1 changed files with 2 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
arch/arm/mach-socfpga/timer_s10.c
View File

@ -14,6 +14,7 @@
*/
int timer_init(void)
{
#ifdef CONFIG_SPL_BUILD
int enable = 0x3; /* timer enable + output signal masked */
int loadval = ~0;
@ -22,6 +23,6 @@ int timer_init(void)
/* enable processor pysical counter */
asm volatile("msr cntp_ctl_el0, %0" : : "r" (enable));
asm volatile("msr cntp_tval_el0, %0" : : "r" (loadval));
#endif
return 0;
}