mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-07-07 11:46:17 +09:00
Move mpc86xx PIXIS code to board directory
First cut at moving the PIXIS platform code out of the 86xx cpu directory and into board/mpc8641hpcn where it belongs. Signed-off-by: Jon Loeliger <jdl@freescale.com>
This commit is contained in:
Jon Loeliger
Jon Loeliger
parent
38cee12dcf
commit
126aa70f10
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@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk
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LIB = lib$(BOARD).a
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OBJS := $(BOARD).o oftree.o
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OBJS := $(BOARD).o pixis.o oftree.o
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SOBJS := init.o
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$(LIB): $(OBJS) $(SOBJS)
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324
board/mpc8641hpcn/pixis.c
Normal file
324
board/mpc8641hpcn/pixis.c
Normal file
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@ -0,0 +1,324 @@
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/*
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* Copyright 2006 Freescale Semiconductor
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* Jeff Brown
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* Srikanth Srinivasan (srikanth.srinivasan@freescale.com)
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <watchdog.h>
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#include <command.h>
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#include <asm/cache.h>
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#include <mpc86xx.h>
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#include "pixis.h"
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/*
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* Per table 27, page 58 of MPC8641HPCN spec.
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*/
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int set_px_sysclk(ulong sysclk)
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{
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u8 sysclk_s, sysclk_r, sysclk_v, vclkh, vclkl, sysclk_aux;
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switch (sysclk) {
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case 33:
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sysclk_s = 0x04;
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sysclk_r = 0x04;
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sysclk_v = 0x07;
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sysclk_aux = 0x00;
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break;
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case 40:
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sysclk_s = 0x01;
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sysclk_r = 0x1F;
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sysclk_v = 0x20;
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sysclk_aux = 0x01;
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break;
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case 50:
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sysclk_s = 0x01;
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sysclk_r = 0x1F;
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sysclk_v = 0x2A;
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sysclk_aux = 0x02;
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break;
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case 66:
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sysclk_s = 0x01;
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sysclk_r = 0x04;
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sysclk_v = 0x04;
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sysclk_aux = 0x03;
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break;
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case 83:
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sysclk_s = 0x01;
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sysclk_r = 0x1F;
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sysclk_v = 0x4B;
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sysclk_aux = 0x04;
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break;
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case 100:
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sysclk_s = 0x01;
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sysclk_r = 0x1F;
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sysclk_v = 0x5C;
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sysclk_aux = 0x05;
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break;
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case 134:
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sysclk_s = 0x06;
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sysclk_r = 0x1F;
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sysclk_v = 0x3B;
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sysclk_aux = 0x06;
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break;
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case 166:
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sysclk_s = 0x06;
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sysclk_r = 0x1F;
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sysclk_v = 0x4B;
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sysclk_aux = 0x07;
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break;
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default:
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printf("Unsupported SYSCLK frequency.\n");
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return 0;
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}
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vclkh = (sysclk_s << 5) | sysclk_r ;
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vclkl = sysclk_v;
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out8(PIXIS_BASE + PIXIS_VCLKH, vclkh);
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out8(PIXIS_BASE + PIXIS_VCLKL, vclkl);
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out8(PIXIS_BASE + PIXIS_AUX,sysclk_aux);
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return 1;
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}
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int set_px_mpxpll(ulong mpxpll)
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{
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u8 tmp;
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u8 val;
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switch (mpxpll) {
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case 2:
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case 4:
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case 6:
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case 8:
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case 10:
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case 12:
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case 14:
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case 16:
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val = (u8)mpxpll;
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break;
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default:
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printf("Unsupported MPXPLL ratio.\n");
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return 0;
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}
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tmp = in8(PIXIS_BASE + PIXIS_VSPEED1);
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tmp = (tmp & 0xF0) | (val & 0x0F);
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out8(PIXIS_BASE + PIXIS_VSPEED1, tmp);
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return 1;
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}
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int set_px_corepll(ulong corepll)
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{
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u8 tmp;
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u8 val;
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switch ((int)corepll) {
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case 20:
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val = 0x08;
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break;
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case 25:
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val = 0x0C;
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break;
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case 30:
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val = 0x10;
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break;
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case 35:
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val = 0x1C;
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break;
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case 40:
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val = 0x14;
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break;
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case 45:
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val = 0x0E;
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break;
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default:
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printf("Unsupported COREPLL ratio.\n");
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return 0;
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}
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tmp = in8(PIXIS_BASE + PIXIS_VSPEED0);
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tmp = (tmp & 0xE0) | (val & 0x1F);
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out8(PIXIS_BASE + PIXIS_VSPEED0, tmp);
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return 1;
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}
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void read_from_px_regs(int set)
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{
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u8 mask = 0x1C;
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u8 tmp = in8(PIXIS_BASE + PIXIS_VCFGEN0);
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if (set)
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tmp = tmp | mask;
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else
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tmp = tmp & ~mask;
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out8(PIXIS_BASE + PIXIS_VCFGEN0, tmp);
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}
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void read_from_px_regs_altbank(int set)
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{
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u8 mask = 0x04;
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u8 tmp = in8(PIXIS_BASE + PIXIS_VCFGEN1);
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if (set)
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tmp = tmp | mask;
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else
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tmp = tmp & ~mask;
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out8(PIXIS_BASE + PIXIS_VCFGEN1, tmp);
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}
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void set_altbank(void)
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{
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u8 tmp;
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tmp = in8(PIXIS_BASE + PIXIS_VBOOT);
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tmp ^= 0x40;
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out8(PIXIS_BASE + PIXIS_VBOOT, tmp);
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}
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void set_px_go(void)
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{
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u8 tmp;
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tmp = in8(PIXIS_BASE + PIXIS_VCTL);
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tmp = tmp & 0x1E;
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out8(PIXIS_BASE + PIXIS_VCTL, tmp);
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tmp = in8(PIXIS_BASE + PIXIS_VCTL);
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tmp = tmp | 0x01;
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out8(PIXIS_BASE + PIXIS_VCTL, tmp);
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}
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void set_px_go_with_watchdog(void)
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{
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u8 tmp;
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tmp = in8(PIXIS_BASE + PIXIS_VCTL);
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tmp = tmp & 0x1E;
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out8(PIXIS_BASE + PIXIS_VCTL, tmp);
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tmp = in8(PIXIS_BASE + PIXIS_VCTL);
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tmp = tmp | 0x09;
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out8(PIXIS_BASE + PIXIS_VCTL, tmp);
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}
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int disable_watchdog(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
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{
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u8 tmp;
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tmp = in8(PIXIS_BASE + PIXIS_VCTL);
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tmp = tmp & 0x1E;
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out8(PIXIS_BASE + PIXIS_VCTL, tmp);
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/* setting VCTL[WDEN] to 0 to disable watch dog */
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tmp = in8(PIXIS_BASE + PIXIS_VCTL);
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tmp &= ~ 0x08;
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out8(PIXIS_BASE + PIXIS_VCTL, tmp);
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return 0;
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}
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U_BOOT_CMD(
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diswd, 1, 0, disable_watchdog,
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"diswd - Disable watchdog timer \n",
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NULL
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);
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/*
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* This function takes the non-integral cpu:mpx pll ratio
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* and converts it to an integer that can be used to assign
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* FPGA register values.
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* input: strptr i.e. argv[2]
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*/
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ulong strfractoint(uchar *strptr)
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{
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int i, j, retval;
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int mulconst;
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int intarr_len = 0, decarr_len = 0, no_dec = 0;
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ulong intval = 0, decval = 0;
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uchar intarr[3], decarr[3];
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/* Assign the integer part to intarr[]
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* If there is no decimal point i.e.
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* if the ratio is an integral value
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* simply create the intarr.
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*/
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i = 0;
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while (strptr[i] != 46) {
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if (strptr[i] == 0) {
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no_dec = 1;
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break;
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}
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intarr[i] = strptr[i];
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i++;
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}
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/* Assign length of integer part to intarr_len. */
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intarr_len = i;
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intarr[i] = '\0';
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if (no_dec) {
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/* Currently needed only for single digit corepll ratios */
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mulconst=10;
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decval = 0;
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} else {
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j = 0;
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i++; /* Skipping the decimal point */
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while ((strptr[i] > 47) && (strptr[i] < 58)) {
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decarr[j] = strptr[i];
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i++;
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j++;
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}
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decarr_len = j;
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decarr[j] = '\0';
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mulconst = 1;
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for (i = 0; i < decarr_len; i++)
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mulconst *= 10;
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decval = simple_strtoul(decarr, NULL, 10);
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}
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intval = simple_strtoul(intarr, NULL, 10);
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intval = intval * mulconst;
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retval = intval + decval;
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return retval;
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}
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33
board/mpc8641hpcn/pixis.h
Normal file
33
board/mpc8641hpcn/pixis.h
Normal file
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@ -0,0 +1,33 @@
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/*
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* Copyright 2006 Freescale Semiconductor
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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extern int set_px_sysclk(ulong sysclk);
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extern int set_px_mpxpll(ulong mpxpll);
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extern int set_px_corepll(ulong corepll);
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extern void read_from_px_regs(int set);
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extern void read_from_px_regs_altbank(int set);
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extern void set_altbank(void);
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extern void set_px_go(void);
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extern void set_px_go_with_watchdog(void);
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extern int disable_watchdog(cmd_tbl_t *cmdtp,
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int flag, int argc, char *argv[]);
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extern ulong strfractoint(uchar *strptr);
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@ -32,7 +32,7 @@
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#include <ft_build.h>
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#endif
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extern unsigned long get_board_sys_clk(ulong dummy);
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#include "../board/mpc8641hpcn/pixis.h"
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static __inline__ unsigned long get_dbat3u (void)
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@ -131,10 +131,10 @@ int checkcpu (void)
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printf(" LBC: unknown (lcrr: 0x%08x)\n", lcrr);
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}
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printf(" L2: ");
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if (get_l2cr() & 0x80000000)
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printf(" L2: ");
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if (get_l2cr() & 0x80000000)
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printf("Enabled\n");
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else
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else
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printf("Disabled\n");
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return 0;
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@ -158,298 +158,21 @@ soft_restart(unsigned long addr)
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__asm__ __volatile__ ("rfi");
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#else /* CONFIG_MPC8641HPCN */
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out8(PIXIS_BASE+PIXIS_RST,0);
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out8(PIXIS_BASE+PIXIS_RST,0);
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#endif /* !CONFIG_MPC8641HPCN */
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while(1); /* not reached */
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}
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#ifdef CONFIG_MPC8641HPCN
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int set_px_sysclk(ulong sysclk)
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{
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u8 sysclk_s, sysclk_r, sysclk_v, vclkh, vclkl, sysclk_aux;
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/* Per table 27, page 58 of MPC8641HPCN spec*/
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switch(sysclk)
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{
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case 33:
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sysclk_s = 0x04;
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sysclk_r = 0x04;
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sysclk_v = 0x07;
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sysclk_aux = 0x00;
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break;
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case 40:
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sysclk_s = 0x01;
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sysclk_r = 0x1F;
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sysclk_v = 0x20;
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sysclk_aux = 0x01;
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break;
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case 50:
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sysclk_s = 0x01;
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sysclk_r = 0x1F;
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sysclk_v = 0x2A;
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sysclk_aux = 0x02;
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break;
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case 66:
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sysclk_s = 0x01;
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sysclk_r = 0x04;
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sysclk_v = 0x04;
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sysclk_aux = 0x03;
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break;
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case 83:
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sysclk_s = 0x01;
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sysclk_r = 0x1F;
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sysclk_v = 0x4B;
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sysclk_aux = 0x04;
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break;
|
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case 100:
|
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sysclk_s = 0x01;
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sysclk_r = 0x1F;
|
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sysclk_v = 0x5C;
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sysclk_aux = 0x05;
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break;
|
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case 134:
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sysclk_s = 0x06;
|
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sysclk_r = 0x1F;
|
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sysclk_v = 0x3B;
|
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sysclk_aux = 0x06;
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break;
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case 166:
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sysclk_s = 0x06;
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sysclk_r = 0x1F;
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sysclk_v = 0x4B;
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sysclk_aux = 0x07;
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break;
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default:
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printf("Unsupported SYSCLK frequency.\n");
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return 0;
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}
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|
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vclkh = (sysclk_s << 5) | sysclk_r ;
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vclkl = sysclk_v;
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out8(PIXIS_BASE+PIXIS_VCLKH,vclkh);
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out8(PIXIS_BASE+PIXIS_VCLKL,vclkl);
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out8(PIXIS_BASE+PIXIS_AUX,sysclk_aux);
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return 1;
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}
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|
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int set_px_mpxpll(ulong mpxpll)
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{
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u8 tmp;
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u8 val;
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switch(mpxpll)
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{
|
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case 2:
|
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case 4:
|
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case 6:
|
||||
case 8:
|
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case 10:
|
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case 12:
|
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case 14:
|
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case 16:
|
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val = (u8)mpxpll;
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break;
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default:
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printf("Unsupported MPXPLL ratio.\n");
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return 0;
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}
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tmp = in8(PIXIS_BASE+PIXIS_VSPEED1);
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tmp = (tmp & 0xF0) | (val & 0x0F);
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out8(PIXIS_BASE+PIXIS_VSPEED1,tmp);
|
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return 1;
|
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}
|
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|
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int set_px_corepll(ulong corepll)
|
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{
|
||||
u8 tmp;
|
||||
u8 val;
|
||||
|
||||
switch ((int)corepll) {
|
||||
case 20:
|
||||
val = 0x08;
|
||||
break;
|
||||
case 25:
|
||||
val = 0x0C;
|
||||
break;
|
||||
case 30:
|
||||
val = 0x10;
|
||||
break;
|
||||
case 35:
|
||||
val = 0x1C;
|
||||
break;
|
||||
case 40:
|
||||
val = 0x14;
|
||||
break;
|
||||
case 45:
|
||||
val = 0x0E;
|
||||
break;
|
||||
default:
|
||||
printf("Unsupported COREPLL ratio.\n");
|
||||
return 0;
|
||||
}
|
||||
|
||||
tmp = in8(PIXIS_BASE+PIXIS_VSPEED0);
|
||||
tmp = (tmp & 0xE0) | (val & 0x1F);
|
||||
out8(PIXIS_BASE+PIXIS_VSPEED0,tmp);
|
||||
|
||||
return 1;
|
||||
}
|
||||
|
||||
void read_from_px_regs(int set)
|
||||
{
|
||||
u8 tmp, mask = 0x1C;
|
||||
tmp = in8(PIXIS_BASE+PIXIS_VCFGEN0);
|
||||
if (set)
|
||||
tmp = tmp | mask;
|
||||
else
|
||||
tmp = tmp & ~mask;
|
||||
out8(PIXIS_BASE+PIXIS_VCFGEN0,tmp);
|
||||
}
|
||||
|
||||
void read_from_px_regs_altbank(int set)
|
||||
{
|
||||
u8 tmp, mask = 0x04;
|
||||
tmp = in8(PIXIS_BASE+PIXIS_VCFGEN1);
|
||||
if (set)
|
||||
tmp = tmp | mask;
|
||||
else
|
||||
tmp = tmp & ~mask;
|
||||
out8(PIXIS_BASE+PIXIS_VCFGEN1,tmp);
|
||||
}
|
||||
|
||||
void set_altbank(void)
|
||||
{
|
||||
u8 tmp;
|
||||
tmp = in8(PIXIS_BASE+PIXIS_VBOOT);
|
||||
tmp ^= 0x40;
|
||||
out8(PIXIS_BASE+PIXIS_VBOOT,tmp);
|
||||
}
|
||||
|
||||
|
||||
void set_px_go(void)
|
||||
{
|
||||
u8 tmp;
|
||||
tmp = in8(PIXIS_BASE+PIXIS_VCTL);
|
||||
tmp = tmp & 0x1E;
|
||||
out8(PIXIS_BASE+PIXIS_VCTL,tmp);
|
||||
tmp = in8(PIXIS_BASE+PIXIS_VCTL);
|
||||
tmp = tmp | 0x01;
|
||||
out8(PIXIS_BASE+PIXIS_VCTL,tmp);
|
||||
}
|
||||
|
||||
void set_px_go_with_watchdog(void)
|
||||
{
|
||||
u8 tmp;
|
||||
tmp = in8(PIXIS_BASE+PIXIS_VCTL);
|
||||
tmp = tmp & 0x1E;
|
||||
out8(PIXIS_BASE+PIXIS_VCTL,tmp);
|
||||
tmp = in8(PIXIS_BASE+PIXIS_VCTL);
|
||||
tmp = tmp | 0x09;
|
||||
out8(PIXIS_BASE+PIXIS_VCTL,tmp);
|
||||
}
|
||||
|
||||
int disable_watchdog(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
|
||||
{
|
||||
u8 tmp;
|
||||
tmp = in8(PIXIS_BASE+PIXIS_VCTL);
|
||||
tmp = tmp & 0x1E;
|
||||
out8(PIXIS_BASE+PIXIS_VCTL,tmp);
|
||||
tmp = in8(PIXIS_BASE + PIXIS_VCTL);
|
||||
tmp &= ~ 0x08; /* setting VCTL[WDEN] to 0 to disable watch dog */
|
||||
out8(PIXIS_BASE + PIXIS_VCTL, tmp);
|
||||
return 0;
|
||||
}
|
||||
|
||||
U_BOOT_CMD(
|
||||
diswd, 1, 0, disable_watchdog,
|
||||
"diswd - Disable watchdog timer \n",
|
||||
NULL
|
||||
);
|
||||
|
||||
/* This function takes the non-integral cpu:mpx pll ratio
|
||||
* and converts it to an integer that can be used to assign
|
||||
* FPGA register values.
|
||||
* input: strptr i.e. argv[2]
|
||||
*/
|
||||
|
||||
ulong strfractoint(uchar *strptr)
|
||||
{
|
||||
int i,j,retval,intarr_len=0, decarr_len=0, mulconst, no_dec=0;
|
||||
ulong intval =0, decval=0;
|
||||
uchar intarr[3], decarr[3];
|
||||
|
||||
/* Assign the integer part to intarr[]
|
||||
* If there is no decimal point i.e.
|
||||
* if the ratio is an integral value
|
||||
* simply create the intarr.
|
||||
*/
|
||||
i=0;
|
||||
while(strptr[i] != 46)
|
||||
{
|
||||
if(strptr[i] == 0)
|
||||
{
|
||||
no_dec = 1;
|
||||
break; /* Break from loop once the end of string is reached */
|
||||
}
|
||||
|
||||
intarr[i] = strptr[i];
|
||||
i++;
|
||||
}
|
||||
|
||||
intarr_len = i; /* Assign length of integer part to intarr_len*/
|
||||
intarr[i] = '\0'; /* */
|
||||
|
||||
if(no_dec)
|
||||
{
|
||||
mulconst=10; /* Currently needed only for single digit corepll ratios */
|
||||
decval = 0;
|
||||
}
|
||||
else
|
||||
{
|
||||
j=0;
|
||||
i++; /* Skipping the decimal point */
|
||||
while ((strptr[i] > 47) && (strptr[i] < 58))
|
||||
{
|
||||
decarr[j] = strptr[i];
|
||||
i++;
|
||||
j++;
|
||||
}
|
||||
|
||||
decarr_len = j;
|
||||
decarr[j] = '\0';
|
||||
|
||||
mulconst=1;
|
||||
for(i=0; i<decarr_len;i++)
|
||||
mulconst = mulconst*10;
|
||||
decval = simple_strtoul(decarr,NULL,10);
|
||||
}
|
||||
|
||||
intval = simple_strtoul(intarr,NULL,10);
|
||||
intval = intval*mulconst;
|
||||
|
||||
retval = intval+decval;
|
||||
|
||||
return retval;
|
||||
|
||||
}
|
||||
|
||||
|
||||
#endif /* CONFIG_MPC8641HPCN */
|
||||
|
||||
|
||||
/* no generic way to do board reset. simply call soft_reset. */
|
||||
/*
|
||||
* No generic way to do board reset. Simply call soft_reset.
|
||||
*/
|
||||
void
|
||||
do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
|
||||
do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
|
||||
{
|
||||
char cmd;
|
||||
ulong addr, val;
|
||||
ulong corepll;
|
||||
char cmd;
|
||||
ulong addr, val;
|
||||
ulong corepll;
|
||||
|
||||
#ifdef CFG_RESET_ADDRESS
|
||||
addr = CFG_RESET_ADDRESS;
|
||||
|
|
@ -478,11 +201,11 @@ do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
|
|||
__asm__ __volatile__ ("isync");
|
||||
__asm__ __volatile__ ("sync");
|
||||
|
||||
soft_restart(addr);
|
||||
soft_restart(addr);
|
||||
|
||||
#else /* CONFIG_MPC8641HPCN */
|
||||
|
||||
if (argc > 1) {
|
||||
if (argc > 1) {
|
||||
cmd = argv[1][1];
|
||||
switch(cmd) {
|
||||
case 'f': /* reset with frequency changed */
|
||||
|
|
@ -560,7 +283,7 @@ my_usage:
|
|||
printf("For example: reset cf 40 2.5 10\n");
|
||||
printf("See MPC8641HPCN Design Workbook for valid values of command line parameters.\n");
|
||||
return;
|
||||
} else
|
||||
} else
|
||||
out8(PIXIS_BASE+PIXIS_RST,0);
|
||||
|
||||
#endif /* !CONFIG_MPC8641HPCN */
|
||||
|
|
@ -598,7 +321,6 @@ void dma_init(void)
|
|||
dma->satr0 = 0x00040000;
|
||||
dma->datr0 = 0x00040000;
|
||||
asm("sync; isync");
|
||||
return;
|
||||
}
|
||||
|
||||
uint dma_check(void)
|
||||
|
|
|
|||
Loading…
Reference in New Issue
Block a user