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https://github.com/brain-hackers/u-boot-brain
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arm: rmobile: Add support koelsch board
The koelsch board has R8A7791, 2GB DDR3-SDRAM, USB, Quad SPI, Ethernet, and more. This patch supports the following functions: - DDR3-SDRAM - SCIF Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> Signed-off-by: Hisashi Nakamura <hisashi.nakamura.ak@renesas.com> CC: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> CC: Albert Aribaud <albert.u.boot@aribaud.net>
This commit is contained in:
Nobuhiro Iwamatsu
Nobuhiro Iwamatsu
parent
bd0550fc5f
commit
1251e49030
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@ -1,6 +1,5 @@
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/*
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* arch/arm/include/asm/arch-rmobile/r8a7791.h
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* This file is r8a7791 processor definition.
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*
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* Copyright (C) 2013 Renesas Electronics Corporation
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*
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@ -64,12 +63,48 @@
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#define DBSC3_0_QOS_W14_BASE 0xE6792E00
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#define DBSC3_0_QOS_W15_BASE 0xE6792F00
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#define DBSC3_1_QOS_R0_BASE 0xE67A1000
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#define DBSC3_1_QOS_R1_BASE 0xE67A1100
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#define DBSC3_1_QOS_R2_BASE 0xE67A1200
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#define DBSC3_1_QOS_R3_BASE 0xE67A1300
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#define DBSC3_1_QOS_R4_BASE 0xE67A1400
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#define DBSC3_1_QOS_R5_BASE 0xE67A1500
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#define DBSC3_1_QOS_R6_BASE 0xE67A1600
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#define DBSC3_1_QOS_R7_BASE 0xE67A1700
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#define DBSC3_1_QOS_R8_BASE 0xE67A1800
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#define DBSC3_1_QOS_R9_BASE 0xE67A1900
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#define DBSC3_1_QOS_R10_BASE 0xE67A1A00
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#define DBSC3_1_QOS_R11_BASE 0xE67A1B00
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#define DBSC3_1_QOS_R12_BASE 0xE67A1C00
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#define DBSC3_1_QOS_R13_BASE 0xE67A1D00
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#define DBSC3_1_QOS_R14_BASE 0xE67A1E00
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#define DBSC3_1_QOS_R15_BASE 0xE67A1F00
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#define DBSC3_1_QOS_W0_BASE 0xE67A2000
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#define DBSC3_1_QOS_W1_BASE 0xE67A2100
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#define DBSC3_1_QOS_W2_BASE 0xE67A2200
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#define DBSC3_1_QOS_W3_BASE 0xE67A2300
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#define DBSC3_1_QOS_W4_BASE 0xE67A2400
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#define DBSC3_1_QOS_W5_BASE 0xE67A2500
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#define DBSC3_1_QOS_W6_BASE 0xE67A2600
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#define DBSC3_1_QOS_W7_BASE 0xE67A2700
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#define DBSC3_1_QOS_W8_BASE 0xE67A2800
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#define DBSC3_1_QOS_W9_BASE 0xE67A2900
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#define DBSC3_1_QOS_W10_BASE 0xE67A2A00
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#define DBSC3_1_QOS_W11_BASE 0xE67A2B00
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#define DBSC3_1_QOS_W12_BASE 0xE67A2C00
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#define DBSC3_1_QOS_W13_BASE 0xE67A2D00
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#define DBSC3_1_QOS_W14_BASE 0xE67A2E00
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#define DBSC3_1_QOS_W15_BASE 0xE67A2F00
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#define DBSC3_0_DBADJ2 0xE67900C8
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#define CCI_400_MAXOT_1 0xF0091110
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#define CCI_400_MAXOT_2 0xF0092110
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#define CCI_400_QOSCNTL_1 0xF009110C
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#define CCI_400_QOSCNTL_2 0xF009210C
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#define MXI_BASE 0xFE960000
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#define MXI_QOS_BASE 0xFE960300
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#define SYS_AXI_SYX64TO128_BASE 0xFF800300
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#define SYS_AXI_AVB_BASE 0xFF800340
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@ -95,11 +130,28 @@
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#define SYS_AXI_USB21_BASE 0xFF800C40
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#define SYS_AXI_USB22_BASE 0xFF800C80
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#define SYS_AXI_USB30_BASE 0xFF800CC0
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#define SYS_AXI_AX2M_BASE 0xFF800380
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#define SYS_AXI_CC50_BASE 0xFF8003C0
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#define SYS_AXI_CCI_BASE 0xFF800440
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#define SYS_AXI_CS_BASE 0xFF800480
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#define SYS_AXI_DDM_BASE 0xFF8004C0
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#define SYS_AXI_ETH_BASE 0xFF800500
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#define SYS_AXI_MPXM_BASE 0xFF800840
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#define SYS_AXI_SAT0_BASE 0xFF800980
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#define SYS_AXI_SAT1_BASE 0xFF8009C0
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#define SYS_AXI_SDM0_BASE 0xFF800A00
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#define SYS_AXI_SDM1_BASE 0xFF800A40
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#define SYS_AXI_TRAB_BASE 0xFF800B00
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#define SYS_AXI_UDM0_BASE 0xFF800B80
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#define SYS_AXI_UDM1_BASE 0xFF800BC0
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#define RT_AXI_SHX_BASE 0xFF810100
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#define RT_AXI_DBG_BASE 0xFF810140
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#define RT_AXI_RDM_BASE 0xFF810180
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#define RT_AXI_RDS_BASE 0xFF8101C0
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#define RT_AXI_RTX64TO128_BASE 0xFF810200
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#define RT_AXI_STPRO_BASE 0xFF810240
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#define RT_AXI_SY2RT_BASE 0xFF810280
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#define MP_AXI_ADSP_BASE 0xFF820100
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#define MP_AXI_ASDS0_BASE 0xFF8201C0
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@ -123,6 +175,8 @@
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#define CCI_AXI_MMUS1_BASE 0xFF880280
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#define CCI_AXI_MMUMP_BASE 0xFF8802C0
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#define MEDIA_AXI_MXR_BASE 0xFE960080
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#define MEDIA_AXI_MXW_BASE 0xFE9600C0
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#define MEDIA_AXI_JPR_BASE 0xFE964100
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#define MEDIA_AXI_JPW_BASE 0xFE966100
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#define MEDIA_AXI_GCU0R_BASE 0xFE964140
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@ -567,18 +621,30 @@ struct r8a7791_dbsc3_qos {
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u32 dbthres0;
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u32 dbthres1;
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u32 dbthres2;
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u32 dummy0; /* 0x24 */
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u32 dblgqon;
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};
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/* MXI(QoS) */
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struct r8a7791_mxi {
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u32 dummy0[10]; /* 0x00 .. 0x24 */
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u32 mxsaar0;
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u32 mxsaar1;
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u32 dummy0[8]; /* 0x08 .. 0x24 */
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u32 mxs3cracr;
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u32 dummy1[5]; /* 0x2C .. 0x3C */
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u32 dummy1[3]; /* 0x2C .. 0x34 */
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u32 mxs3cwacr;
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u32 dummy2; /* 0x3C */
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u32 mxrtcr;
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u32 mxwtcr;
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};
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struct r8a7791_mxi_qos {
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u32 vspdu0;
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u32 vspdu1;
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u32 du0;
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u32 du1;
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};
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/* AXI(QoS) */
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struct r8a7791_axi_qos {
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u32 qosconf;
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9
board/renesas/koelsch/Makefile
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9
board/renesas/koelsch/Makefile
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@ -0,0 +1,9 @@
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#
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# board/renesas/koelsch/Makefile
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#
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# Copyright (C) 2013 Renesas Electronics Corporation
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#
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# SPDX-License-Identifier: GPL-2.0
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#
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obj-y := koelsch.o qos.o
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283
board/renesas/koelsch/koelsch.c
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283
board/renesas/koelsch/koelsch.c
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@ -0,0 +1,283 @@
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/*
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* board/renesas/koelsch/koelsch.c
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*
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* Copyright (C) 2013 Renesas Electronics Corporation
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*
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* SPDX-License-Identifier: GPL-2.0
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*
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*/
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#include <common.h>
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#include <malloc.h>
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#include <asm/processor.h>
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#include <asm/mach-types.h>
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#include <asm/io.h>
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#include <asm/errno.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/gpio.h>
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#include <asm/arch/rmobile.h>
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#include <i2c.h>
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#include "qos.h"
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DECLARE_GLOBAL_DATA_PTR;
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#define s_init_wait(cnt) \
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({ \
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u32 i = 0x10000 * cnt; \
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while (i > 0) \
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i--; \
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})
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#define dbpdrgd_check(bsc) \
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({ \
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while ((readl(&bsc->dbpdrgd) & 0x1) != 0x1) \
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; \
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})
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#if defined(CONFIG_NORFLASH)
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static void bsc_init(void)
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{
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struct r8a7791_lbsc *lbsc = (struct r8a7791_lbsc *)LBSC_BASE;
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struct r8a7791_dbsc3 *dbsc3_0 = (struct r8a7791_dbsc3 *)DBSC3_0_BASE;
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/* LBSC */
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writel(0x00000020, &lbsc->cs0ctrl);
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writel(0x00000020, &lbsc->cs1ctrl);
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writel(0x00002020, &lbsc->ecs0ctrl);
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writel(0x00002020, &lbsc->ecs1ctrl);
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writel(0x077F077F, &lbsc->cswcr0);
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writel(0x077F077F, &lbsc->cswcr1);
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writel(0x077F077F, &lbsc->ecswcr0);
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writel(0x077F077F, &lbsc->ecswcr1);
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/* DBSC3 */
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s_init_wait(10);
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writel(0x0000A55A, &dbsc3_0->dbpdlck);
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writel(0x00000001, &dbsc3_0->dbpdrga);
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writel(0x80000000, &dbsc3_0->dbpdrgd);
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writel(0x00000004, &dbsc3_0->dbpdrga);
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dbpdrgd_check(dbsc3_0);
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writel(0x00000006, &dbsc3_0->dbpdrga);
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writel(0x0001C000, &dbsc3_0->dbpdrgd);
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writel(0x00000023, &dbsc3_0->dbpdrga);
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writel(0x00FD2480, &dbsc3_0->dbpdrgd);
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writel(0x00000010, &dbsc3_0->dbpdrga);
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writel(0xF004649B, &dbsc3_0->dbpdrgd);
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writel(0x0000000F, &dbsc3_0->dbpdrga);
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writel(0x00181EE4, &dbsc3_0->dbpdrgd);
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writel(0x0000000E, &dbsc3_0->dbpdrga);
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writel(0x33C03812, &dbsc3_0->dbpdrgd);
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writel(0x00000003, &dbsc3_0->dbpdrga);
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writel(0x0300C481, &dbsc3_0->dbpdrgd);
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writel(0x00000007, &dbsc3_0->dbkind);
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writel(0x10030A02, &dbsc3_0->dbconf0);
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writel(0x00000001, &dbsc3_0->dbphytype);
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writel(0x00000000, &dbsc3_0->dbbl);
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writel(0x0000000B, &dbsc3_0->dbtr0);
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writel(0x00000008, &dbsc3_0->dbtr1);
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writel(0x00000000, &dbsc3_0->dbtr2);
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writel(0x0000000B, &dbsc3_0->dbtr3);
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writel(0x000C000B, &dbsc3_0->dbtr4);
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writel(0x00000027, &dbsc3_0->dbtr5);
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writel(0x0000001C, &dbsc3_0->dbtr6);
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writel(0x00000005, &dbsc3_0->dbtr7);
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writel(0x00000018, &dbsc3_0->dbtr8);
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writel(0x00000008, &dbsc3_0->dbtr9);
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writel(0x0000000C, &dbsc3_0->dbtr10);
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writel(0x00000009, &dbsc3_0->dbtr11);
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writel(0x00000012, &dbsc3_0->dbtr12);
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writel(0x000000D0, &dbsc3_0->dbtr13);
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writel(0x00140005, &dbsc3_0->dbtr14);
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writel(0x00050004, &dbsc3_0->dbtr15);
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writel(0x70233005, &dbsc3_0->dbtr16);
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writel(0x000C0000, &dbsc3_0->dbtr17);
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writel(0x00000300, &dbsc3_0->dbtr18);
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writel(0x00000040, &dbsc3_0->dbtr19);
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writel(0x00000001, &dbsc3_0->dbrnk0);
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writel(0x00020001, &dbsc3_0->dbadj0);
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writel(0x20082008, &dbsc3_0->dbadj2);
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writel(0x00020002, &dbsc3_0->dbwt0cnf0);
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writel(0x0000000F, &dbsc3_0->dbwt0cnf4);
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writel(0x00000015, &dbsc3_0->dbpdrga);
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writel(0x00000D70, &dbsc3_0->dbpdrgd);
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writel(0x00000016, &dbsc3_0->dbpdrga);
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writel(0x00000006, &dbsc3_0->dbpdrgd);
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writel(0x00000017, &dbsc3_0->dbpdrga);
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writel(0x00000018, &dbsc3_0->dbpdrgd);
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writel(0x00000012, &dbsc3_0->dbpdrga);
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writel(0x9D5CBB66, &dbsc3_0->dbpdrgd);
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writel(0x00000013, &dbsc3_0->dbpdrga);
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writel(0x1A868300, &dbsc3_0->dbpdrgd);
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writel(0x00000023, &dbsc3_0->dbpdrga);
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writel(0x00FDB6C0, &dbsc3_0->dbpdrgd);
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writel(0x00000014, &dbsc3_0->dbpdrga);
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writel(0x300214D8, &dbsc3_0->dbpdrgd);
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writel(0x0000001A, &dbsc3_0->dbpdrga);
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writel(0x930035C7, &dbsc3_0->dbpdrgd);
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writel(0x00000060, &dbsc3_0->dbpdrga);
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writel(0x330657B2, &dbsc3_0->dbpdrgd);
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writel(0x00000011, &dbsc3_0->dbpdrga);
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writel(0x1000040B, &dbsc3_0->dbpdrgd);
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writel(0x0000FA00, &dbsc3_0->dbcmd);
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writel(0x00000001, &dbsc3_0->dbpdrga);
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writel(0x00000071, &dbsc3_0->dbpdrgd);
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writel(0x00000004, &dbsc3_0->dbpdrga);
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dbpdrgd_check(dbsc3_0);
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writel(0x0000FA00, &dbsc3_0->dbcmd);
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writel(0x2100FA00, &dbsc3_0->dbcmd);
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writel(0x0000FA00, &dbsc3_0->dbcmd);
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writel(0x0000FA00, &dbsc3_0->dbcmd);
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writel(0x0000FA00, &dbsc3_0->dbcmd);
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writel(0x0000FA00, &dbsc3_0->dbcmd);
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writel(0x0000FA00, &dbsc3_0->dbcmd);
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writel(0x0000FA00, &dbsc3_0->dbcmd);
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writel(0x0000FA00, &dbsc3_0->dbcmd);
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writel(0x110000DB, &dbsc3_0->dbcmd);
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writel(0x00000001, &dbsc3_0->dbpdrga);
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writel(0x00000181, &dbsc3_0->dbpdrgd);
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writel(0x00000004, &dbsc3_0->dbpdrga);
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dbpdrgd_check(dbsc3_0);
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writel(0x00000001, &dbsc3_0->dbpdrga);
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writel(0x0000FE01, &dbsc3_0->dbpdrgd);
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writel(0x00000004, &dbsc3_0->dbpdrga);
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dbpdrgd_check(dbsc3_0);
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writel(0x00000000, &dbsc3_0->dbbs0cnt1);
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writel(0x01004C20, &dbsc3_0->dbcalcnf);
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writel(0x014000AA, &dbsc3_0->dbcaltr);
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writel(0x00000140, &dbsc3_0->dbrfcnf0);
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writel(0x00081860, &dbsc3_0->dbrfcnf1);
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writel(0x00010000, &dbsc3_0->dbrfcnf2);
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writel(0x00000001, &dbsc3_0->dbrfen);
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writel(0x00000001, &dbsc3_0->dbacen);
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}
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#else
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#define bsc_init() do {} while (0)
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#endif /* CONFIG_NORFLASH */
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void s_init(void)
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{
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struct r8a7791_rwdt *rwdt = (struct r8a7791_rwdt *)RWDT_BASE;
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struct r8a7791_swdt *swdt = (struct r8a7791_swdt *)SWDT_BASE;
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/* Watchdog init */
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writel(0xA5A5A500, &rwdt->rwtcsra);
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writel(0xA5A5A500, &swdt->swtcsra);
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/* QoS */
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qos_init();
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/* BSC */
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bsc_init();
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}
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#define MSTPSR1 0xE6150038
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#define SMSTPCR1 0xE6150134
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#define TMU0_MSTP125 (1 << 25)
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#define MSTPSR7 0xE61501C4
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#define SMSTPCR7 0xE615014C
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#define SCIF0_MSTP721 (1 << 21)
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#define PMMR 0xE6060000
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#define GPSR4 0xE6060014
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#define IPSR14 0xE6060058
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#define set_guard_reg(addr, mask, value) \
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{ \
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u32 val; \
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val = (readl(addr) & ~(mask)) | (value); \
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writel(~val, PMMR); \
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writel(val, addr); \
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}
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#define mstp_setbits(type, addr, saddr, set) \
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out_##type((saddr), in_##type(addr) | (set))
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#define mstp_clrbits(type, addr, saddr, clear) \
|
||||
out_##type((saddr), in_##type(addr) & ~(clear))
|
||||
#define mstp_setbits_le32(addr, saddr, set) \
|
||||
mstp_setbits(le32, addr, saddr, set)
|
||||
#define mstp_clrbits_le32(addr, saddr, clear) \
|
||||
mstp_clrbits(le32, addr, saddr, clear)
|
||||
|
||||
int board_early_init_f(void)
|
||||
{
|
||||
mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125);
|
||||
|
||||
#if defined(CONFIG_NORFLASH)
|
||||
/* SCIF0 */
|
||||
set_guard_reg(GPSR4, 0x34000000, 0x00000000);
|
||||
set_guard_reg(IPSR14, 0x00000FC7, 0x00000481);
|
||||
set_guard_reg(GPSR4, 0x00000000, 0x34000000);
|
||||
#endif
|
||||
|
||||
mstp_clrbits_le32(MSTPSR7, SMSTPCR7, SCIF0_MSTP721);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int board_init(void)
|
||||
{
|
||||
/* adress of boot parameters */
|
||||
gd->bd->bi_boot_params = KOELSCH_SDRAM_BASE + 0x100;
|
||||
|
||||
/* Init PFC controller */
|
||||
r8a7791_pinmux_init();
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int dram_init(void)
|
||||
{
|
||||
gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
|
||||
gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
const struct rmobile_sysinfo sysinfo = {
|
||||
CONFIG_RMOBILE_BOARD_STRING
|
||||
};
|
||||
|
||||
void dram_init_banksize(void)
|
||||
{
|
||||
gd->bd->bi_dram[0].start = KOELSCH_SDRAM_BASE;
|
||||
gd->bd->bi_dram[0].size = KOELSCH_SDRAM_SIZE;
|
||||
}
|
||||
|
||||
int board_late_init(void)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
void reset_cpu(ulong addr)
|
||||
{
|
||||
}
|
||||
1220
board/renesas/koelsch/qos.c
Normal file
1220
board/renesas/koelsch/qos.c
Normal file
File diff suppressed because it is too large
Load Diff
12
board/renesas/koelsch/qos.h
Normal file
12
board/renesas/koelsch/qos.h
Normal file
|
|
@ -0,0 +1,12 @@
|
|||
/*
|
||||
* Copyright (C) 2013 Renesas Electronics Corporation
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0
|
||||
*/
|
||||
|
||||
#ifndef __QOS_H__
|
||||
#define __QOS_H__
|
||||
|
||||
void qos_init(void);
|
||||
|
||||
#endif
|
||||
|
|
@ -340,6 +340,8 @@ Active arm armv7 rmobile atmark-techno armadillo-800eva
|
|||
Active arm armv7 rmobile kmc kzm9g kzm9g - Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>:Tetsuyuki Kobayashi <koba@kmckk.co.jp>
|
||||
Active arm armv7 rmobile renesas lager lager - Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
|
||||
Active arm armv7 rmobile renesas lager lager_nor lager:NORFLASH Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
|
||||
Active arm armv7 rmobile renesas koelsch koelsch - Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
|
||||
Active arm armv7 rmobile renesas koelsch koelsch_nor koelsch:NORFLASH Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
|
||||
Active arm armv7 s5pc1xx samsung goni s5p_goni - Minkyu Kang <mk7.kang@samsung.com>
|
||||
Active arm armv7 s5pc1xx samsung smdkc100 smdkc100 - Minkyu Kang <mk7.kang@samsung.com>
|
||||
Active arm armv7 socfpga altera socfpga socfpga_cyclone5 - -
|
||||
|
|
|
|||
133
include/configs/koelsch.h
Normal file
133
include/configs/koelsch.h
Normal file
|
|
@ -0,0 +1,133 @@
|
|||
/*
|
||||
* include/configs/koelsch.h
|
||||
*
|
||||
* Copyright (C) 2013 Renesas Electronics Corporation
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0
|
||||
*/
|
||||
|
||||
#ifndef __KOELSCH_H
|
||||
#define __KOELSCH_H
|
||||
|
||||
#undef DEBUG
|
||||
#define CONFIG_ARMV7
|
||||
#define CONFIG_R8A7791
|
||||
#define CONFIG_RMOBILE
|
||||
#define CONFIG_RMOBILE_BOARD_STRING "Koelsch"
|
||||
#define CONFIG_SH_GPIO_PFC
|
||||
|
||||
#include <asm/arch/rmobile.h>
|
||||
|
||||
#define CONFIG_CMD_EDITENV
|
||||
#define CONFIG_CMD_SAVEENV
|
||||
#define CONFIG_CMD_MEMORY
|
||||
#define CONFIG_CMD_DFL
|
||||
#define CONFIG_CMD_SDRAM
|
||||
#define CONFIG_CMD_RUN
|
||||
#define CONFIG_CMD_LOADS
|
||||
#define CONFIG_CMD_BOOTZ
|
||||
#define CONFIG_CMD_FLASH
|
||||
|
||||
#define CONFIG_CMDLINE_TAG
|
||||
#define CONFIG_SETUP_MEMORY_TAGS
|
||||
#define CONFIG_INITRD_TAG
|
||||
#define CONFIG_CMDLINE_EDITING
|
||||
|
||||
#define CONFIG_OF_LIBFDT
|
||||
#define BOARD_LATE_INIT
|
||||
|
||||
#define CONFIG_BAUDRATE 38400
|
||||
#define CONFIG_BOOTDELAY 3
|
||||
#define CONFIG_BOOTARGS ""
|
||||
|
||||
#define CONFIG_VERSION_VARIABLE
|
||||
#undef CONFIG_SHOW_BOOT_PROGRESS
|
||||
|
||||
#define CONFIG_ARCH_CPU_INIT
|
||||
#define CONFIG_DISPLAY_CPUINFO
|
||||
#define CONFIG_DISPLAY_BOARDINFO
|
||||
#define CONFIG_BOARD_EARLY_INIT_F
|
||||
#define CONFIG_USE_ARCH_MEMSET
|
||||
#define CONFIG_USE_ARCH_MEMCPY
|
||||
#define CONFIG_TMU_TIMER
|
||||
|
||||
/* STACK */
|
||||
#define CONFIG_SYS_INIT_SP_ADDR 0xE633fffc
|
||||
#define STACK_AREA_SIZE 0xC000
|
||||
#define LOW_LEVEL_MERAM_STACK \
|
||||
(CONFIG_SYS_INIT_SP_ADDR + STACK_AREA_SIZE - 4)
|
||||
|
||||
/* MEMORY */
|
||||
#define KOELSCH_SDRAM_BASE 0x40000000
|
||||
#define KOELSCH_SDRAM_SIZE (2048u * 1024 * 1024)
|
||||
#define KOELSCH_UBOOT_SDRAM_SIZE (512 * 1024 * 1024)
|
||||
|
||||
#define CONFIG_SYS_LONGHELP
|
||||
#define CONFIG_SYS_CBSIZE 256
|
||||
#define CONFIG_SYS_PBSIZE 256
|
||||
#define CONFIG_SYS_MAXARGS 16
|
||||
#define CONFIG_SYS_BARGSIZE 512
|
||||
#define CONFIG_SYS_BAUDRATE_TABLE { 38400, 115200 }
|
||||
|
||||
/* SCIF */
|
||||
#define CONFIG_SCIF_CONSOLE
|
||||
#define CONFIG_CONS_SCIF0
|
||||
#define SCIF0_BASE 0xe6e60000
|
||||
#undef CONFIG_SYS_CONSOLE_INFO_QUIET
|
||||
#undef CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
|
||||
#undef CONFIG_SYS_CONSOLE_ENV_OVERWRITE
|
||||
|
||||
#define CONFIG_SYS_MEMTEST_START (KOELSCH_SDRAM_BASE)
|
||||
#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + \
|
||||
504 * 1024 * 1024)
|
||||
#undef CONFIG_SYS_ALT_MEMTEST
|
||||
#undef CONFIG_SYS_MEMTEST_SCRATCH
|
||||
#undef CONFIG_SYS_LOADS_BAUD_CHANGE
|
||||
|
||||
#define CONFIG_SYS_SDRAM_BASE (KOELSCH_SDRAM_BASE)
|
||||
#define CONFIG_SYS_SDRAM_SIZE (KOELSCH_UBOOT_SDRAM_SIZE)
|
||||
#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x7fc0)
|
||||
#define CONFIG_NR_DRAM_BANKS 1
|
||||
|
||||
#define CONFIG_SYS_MONITOR_BASE 0x00000000
|
||||
#define CONFIG_SYS_MONITOR_LEN (256 * 1024)
|
||||
#define CONFIG_SYS_MALLOC_LEN (1 * 1024 * 1024)
|
||||
#define CONFIG_SYS_GBL_DATA_SIZE (256)
|
||||
#define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024)
|
||||
|
||||
/* FLASH */
|
||||
#define CONFIG_SYS_TEXT_BASE 0x00000000
|
||||
#define CONFIG_SYS_FLASH_CFI
|
||||
#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
|
||||
#define CONFIG_FLASH_CFI_DRIVER
|
||||
#define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
|
||||
#define CONFIG_FLASH_SHOW_PROGRESS 45
|
||||
#define CONFIG_SYS_FLASH_BASE 0x00000000
|
||||
#define CONFIG_SYS_FLASH_SIZE 0x04000000 /* 64 MB */
|
||||
#define CONFIG_SYS_MAX_FLASH_SECT 1024
|
||||
#define CONFIG_SYS_MAX_FLASH_BANKS 1
|
||||
#define CONFIG_SYS_FLASH_BANKS_LIST { (CONFIG_SYS_FLASH_BASE) }
|
||||
#define CONFIG_SYS_FLASH_BANKS_SIZES { (CONFIG_SYS_FLASH_SIZE) }
|
||||
#define CONFIG_SYS_FLASH_ERASE_TOUT 3000
|
||||
#define CONFIG_SYS_FLASH_WRITE_TOUT 3000
|
||||
#define CONFIG_SYS_FLASH_LOCK_TOUT 3000
|
||||
#define CONFIG_SYS_FLASH_UNLOCK_TOUT 3000
|
||||
|
||||
/* ENV setting */
|
||||
#define CONFIG_ENV_IS_IN_FLASH
|
||||
#define CONFIG_ENV_OVERWRITE 1
|
||||
#define CONFIG_ENV_SECT_SIZE (256 * 1024)
|
||||
#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + \
|
||||
CONFIG_SYS_MONITOR_LEN)
|
||||
#define CONFIG_ENV_OFFSET (CONFIG_ENV_ADDR)
|
||||
#define CONFIG_ENV_SIZE (CONFIG_ENV_SECT_SIZE)
|
||||
#define CONFIG_ENV_SIZE_REDUND (CONFIG_SYS_MONITOR_LEN)
|
||||
|
||||
/* Board Clock */
|
||||
#define CONFIG_SYS_CLK_FREQ 10000000
|
||||
#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
|
||||
#define CONFIG_SH_SCIF_CLK_FREQ 14745600
|
||||
#define CONFIG_SYS_TMU_CLK_DIV 4
|
||||
#define CONFIG_SYS_HZ 1000
|
||||
|
||||
#endif /* __KOELSCH_H */
|
||||
Loading…
Reference in New Issue
Block a user