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vf610: Add I2C support for Vybrid VF610 platform

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This patch adds I2C support for Vybrid VF610 platform and adds
I2C0 support to VF610TWR board.

Signed-off-by: Alison Wang <b18965@freescale.com>
This commit is contained in:
Alison Wang 2013-06-17 15:30:38 +08:00 committed by Heiko Schocher
parent cfb25cc40e
commit 1221b3d74a
7 changed files with 34 additions and 1 deletions
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7
arch/arm/cpu/armv7/vf610/generic.c
View File

@ -204,6 +204,11 @@ u32 get_fec_clk(void)
return freq;
}
static u32 get_i2c_clk(void)
{
return get_ipg_clk();
}
unsigned int mxc_get_clock(enum mxc_clock clk)
{
switch (clk) {
@ -219,6 +224,8 @@ unsigned int mxc_get_clock(enum mxc_clock clk)
return get_sdhc_clk();
case MXC_FEC_CLK:
return get_fec_clk();
case MXC_I2C_CLK:
return get_i2c_clk();
default:
break;
}

1
arch/arm/include/asm/arch-vf610/clock.h
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@ -29,6 +29,7 @@ enum mxc_clock {
MXC_UART_CLK,
MXC_ESDHC_CLK,
MXC_FEC_CLK,
MXC_I2C_CLK,
};
void enable_ocotp_clk(unsigned char enable);

1
arch/arm/include/asm/arch-vf610/crm_regs.h
View File

@ -190,6 +190,7 @@ struct anadig_reg {
#define CCM_CCGR4_WKUP_CTRL_MASK (0x3 << 20)
#define CCM_CCGR4_CCM_CTRL_MASK (0x3 << 22)
#define CCM_CCGR4_GPC_CTRL_MASK (0x3 << 24)
#define CCM_CCGR4_I2C0_CTRL_MASK (0x3 << 12)
#define CCM_CCGR6_OCOTP_CTRL_MASK (0x3 << 10)
#define CCM_CCGR6_DDRMC_CTRL_MASK (0x3 << 28)
#define CCM_CCGR7_SDHC1_CTRL_MASK (0x3 << 4)

1
arch/arm/include/asm/arch-vf610/imx-regs.h
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@ -103,6 +103,7 @@
#define CONFIG_IOMUX_SHARE_CONF_REG
#define FEC_QUIRK_ENET_MAC
#define I2C_QUIRK_REG
/* MSCM interrupt rounter */
#define MSCM_IRSPRC_CP0_EN 1

4
arch/arm/include/asm/arch-vf610/iomux-vf610.h
View File

@ -30,6 +30,8 @@
#define VF610_ENET_PAD_CTRL (PAD_CTL_PUS_47K_UP | PAD_CTL_DSE_50ohm | \
PAD_CTL_OBE_IBE_ENABLE)
#define VF610_DDR_PAD_CTRL PAD_CTL_DSE_25ohm
#define VF610_I2C_PAD_CTRL (PAD_CTL_PUS_47K_UP | PAD_CTL_DSE_50ohm | \
PAD_CTL_SPEED_HIGH | PAD_CTL_OBE_IBE_ENABLE)
enum {
VF610_PAD_PTA6__RMII0_CLKIN = IOMUX_PAD(0x0000, 0x0000, 2, __NA_, 0, VF610_ENET_PAD_CTRL),
@ -50,6 +52,8 @@ enum {
VF610_PAD_PTA27__ESDHC1_DAT1 = IOMUX_PAD(0x0044, 0x0044, 5, __NA_, 0, VF610_SDHC_PAD_CTRL),
VF610_PAD_PTA28__ESDHC1_DAT2 = IOMUX_PAD(0x0048, 0x0048, 5, __NA_, 0, VF610_SDHC_PAD_CTRL),
VF610_PAD_PTA29__ESDHC1_DAT3 = IOMUX_PAD(0x004c, 0x004c, 5, __NA_, 0, VF610_SDHC_PAD_CTRL),
VF610_PAD_PTB14__I2C0_SCL = IOMUX_PAD(0x0090, 0x0090, 2, 0x033c, 1, VF610_I2C_PAD_CTRL),
VF610_PAD_PTB15__I2C0_SDA = IOMUX_PAD(0x0094, 0x0094, 2, 0x0340, 1, VF610_I2C_PAD_CTRL),
VF610_PAD_DDR_A15__DDR_A_15 = IOMUX_PAD(0x0220, 0x0220, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
VF610_PAD_DDR_A14__DDR_A_14 = IOMUX_PAD(0x0224, 0x0224, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
VF610_PAD_DDR_A13__DDR_A_13 = IOMUX_PAD(0x0228, 0x0228, 0, __NA_, 0, VF610_DDR_PAD_CTRL),

14
board/freescale/vf610twr/vf610twr.c
View File

@ -27,6 +27,7 @@
#include <fsl_esdhc.h>
#include <miiphy.h>
#include <netdev.h>
#include <i2c.h>
DECLARE_GLOBAL_DATA_PTR;
@ -280,6 +281,16 @@ static void setup_iomux_enet(void)
imx_iomux_v3_setup_multiple_pads(enet0_pads, ARRAY_SIZE(enet0_pads));
}
static void setup_iomux_i2c(void)
{
static const iomux_v3_cfg_t i2c0_pads[] = {
VF610_PAD_PTB14__I2C0_SCL,
VF610_PAD_PTB15__I2C0_SDA,
};
imx_iomux_v3_setup_multiple_pads(i2c0_pads, ARRAY_SIZE(i2c0_pads));
}
#ifdef CONFIG_FSL_ESDHC
struct fsl_esdhc_cfg esdhc_cfg[1] = {
{ESDHC1_BASE_ADDR},
@ -328,7 +339,7 @@ static void clock_init(void)
CCM_CCGR3_ANADIG_CTRL_MASK);
clrsetbits_le32(&ccm->ccgr4, CCM_REG_CTRL_MASK,
CCM_CCGR4_WKUP_CTRL_MASK | CCM_CCGR4_CCM_CTRL_MASK |
CCM_CCGR4_GPC_CTRL_MASK);
CCM_CCGR4_GPC_CTRL_MASK | CCM_CCGR4_I2C0_CTRL_MASK);
clrsetbits_le32(&ccm->ccgr6, CCM_REG_CTRL_MASK,
CCM_CCGR6_OCOTP_CTRL_MASK | CCM_CCGR6_DDRMC_CTRL_MASK);
clrsetbits_le32(&ccm->ccgr7, CCM_REG_CTRL_MASK,
@ -387,6 +398,7 @@ int board_early_init_f(void)
setup_iomux_uart();
setup_iomux_enet();
setup_iomux_i2c();
return 0;
}

7
include/configs/vf610twr.h
View File

@ -81,6 +81,13 @@
#define CONFIG_PHYLIB
#define CONFIG_PHY_MICREL
/* I2C Configs */
#define CONFIG_CMD_I2C
#define CONFIG_HARD_I2C
#define CONFIG_I2C_MXC
#define CONFIG_SYS_I2C_BASE I2C0_BASE_ADDR
#define CONFIG_SYS_I2C_SPEED 100000
#define CONFIG_BOOTDELAY 3
#define CONFIG_LOADADDR 0x82000000