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drivers: net: add NXP ENETC ethernet driver
Adds a driver for NXP ENETC ethernet controller currently integrated in LS1028A. ENETC is a fairly straight-forward BD ring device and interfaces are presented as PCI EPs on the SoC ECAM. Signed-off-by: Catalin Horghidan <catalin.horghidan@nxp.com> Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
This commit is contained in:
parent
ff6c6b2d6d
commit
120b5ef287
@ -588,4 +588,11 @@ config HIGMACV300_ETH
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This driver supports HIGMACV300 Ethernet controller found on
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HiSilicon SoCs.
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config FSL_ENETC
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bool "NXP ENETC Ethernet controller"
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depends on DM_PCI && DM_ETH
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help
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This driver supports the NXP ENETC Ethernet controller found on some
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of the NXP SoCs.
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endif # NETDEVICES
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@ -79,3 +79,4 @@ obj-$(CONFIG_MEDIATEK_ETH) += mtk_eth.o
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obj-y += mscc_eswitch/
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obj-$(CONFIG_HIGMACV300_ETH) += higmacv300.o
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obj-$(CONFIG_MDIO_SANDBOX) += mdio_sandbox.o
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obj-$(CONFIG_FSL_ENETC) += fsl_enetc.o
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380
drivers/net/fsl_enetc.c
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380
drivers/net/fsl_enetc.c
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@ -0,0 +1,380 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* ENETC ethernet controller driver
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* Copyright 2017-2019 NXP
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*/
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#include <common.h>
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#include <dm.h>
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#include <errno.h>
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#include <memalign.h>
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#include <asm/io.h>
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#include <pci.h>
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#include "fsl_enetc.h"
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/*
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* Bind the device:
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* - set a more explicit name on the interface
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*/
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static int enetc_bind(struct udevice *dev)
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{
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char name[16];
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static int eth_num_devices;
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/*
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* prefer using PCI function numbers to number interfaces, but these
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* are only available if dts nodes are present. For PCI they are
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* optional, handle that case too. Just in case some nodes are present
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* and some are not, use different naming scheme - enetc-N based on
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* PCI function # and enetc#N based on interface count
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*/
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if (ofnode_valid(dev->node))
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sprintf(name, "enetc-%u", PCI_FUNC(pci_get_devfn(dev)));
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else
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sprintf(name, "enetc#%u", eth_num_devices++);
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device_set_name(dev, name);
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return 0;
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}
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/*
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* Probe ENETC driver:
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* - initialize port and station interface BARs
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*/
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static int enetc_probe(struct udevice *dev)
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{
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struct enetc_priv *priv = dev_get_priv(dev);
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if (ofnode_valid(dev->node) && !ofnode_is_available(dev->node)) {
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enetc_dbg(dev, "interface disabled\n");
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return -ENODEV;
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}
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priv->enetc_txbd = memalign(ENETC_BD_ALIGN,
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sizeof(struct enetc_tx_bd) * ENETC_BD_CNT);
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priv->enetc_rxbd = memalign(ENETC_BD_ALIGN,
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sizeof(union enetc_rx_bd) * ENETC_BD_CNT);
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if (!priv->enetc_txbd || !priv->enetc_rxbd) {
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/* free should be able to handle NULL, just free all pointers */
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free(priv->enetc_txbd);
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free(priv->enetc_rxbd);
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return -ENOMEM;
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}
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/* initialize register */
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priv->regs_base = dm_pci_map_bar(dev, PCI_BASE_ADDRESS_0, 0);
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if (!priv->regs_base) {
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enetc_dbg(dev, "failed to map BAR0\n");
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return -EINVAL;
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}
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priv->port_regs = priv->regs_base + ENETC_PORT_REGS_OFF;
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dm_pci_clrset_config16(dev, PCI_COMMAND, 0, PCI_COMMAND_MEMORY);
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return 0;
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}
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/*
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* Remove the driver from an interface:
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* - free up allocated memory
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*/
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static int enetc_remove(struct udevice *dev)
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{
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struct enetc_priv *priv = dev_get_priv(dev);
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free(priv->enetc_txbd);
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free(priv->enetc_rxbd);
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return 0;
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}
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/* ENETC Port MAC address registers, accepts big-endian format */
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static void enetc_set_primary_mac_addr(struct enetc_priv *priv, const u8 *addr)
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{
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u16 lower = *(const u16 *)(addr + 4);
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u32 upper = *(const u32 *)addr;
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enetc_write_port(priv, ENETC_PSIPMAR0, upper);
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enetc_write_port(priv, ENETC_PSIPMAR1, lower);
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}
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/* Configure port parameters (# of rings, frame size, enable port) */
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static void enetc_enable_si_port(struct enetc_priv *priv)
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{
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u32 val;
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/* set Rx/Tx BDR count */
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val = ENETC_PSICFGR_SET_TXBDR(ENETC_TX_BDR_CNT);
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val |= ENETC_PSICFGR_SET_RXBDR(ENETC_RX_BDR_CNT);
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enetc_write_port(priv, ENETC_PSICFGR(0), val);
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/* set Rx max frame size */
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enetc_write_port(priv, ENETC_PM_MAXFRM, ENETC_RX_MAXFRM_SIZE);
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/* enable MAC port */
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enetc_write_port(priv, ENETC_PM_CC, ENETC_PM_CC_RX_TX_EN);
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/* enable port */
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enetc_write_port(priv, ENETC_PMR, ENETC_PMR_SI0_EN);
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/* set SI cache policy */
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enetc_write(priv, ENETC_SICAR0,
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ENETC_SICAR_RD_CFG | ENETC_SICAR_WR_CFG);
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/* enable SI */
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enetc_write(priv, ENETC_SIMR, ENETC_SIMR_EN);
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}
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/* returns DMA address for a given buffer index */
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static inline u64 enetc_rxb_address(struct udevice *dev, int i)
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{
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return cpu_to_le64(dm_pci_virt_to_mem(dev, net_rx_packets[i]));
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}
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/*
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* Setup a single Tx BD Ring (ID = 0):
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* - set Tx buffer descriptor address
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* - set the BD count
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* - initialize the producer and consumer index
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*/
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static void enetc_setup_tx_bdr(struct udevice *dev)
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{
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struct enetc_priv *priv = dev_get_priv(dev);
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struct bd_ring *tx_bdr = &priv->tx_bdr;
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u64 tx_bd_add = (u64)priv->enetc_txbd;
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/* used later to advance to the next Tx BD */
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tx_bdr->bd_count = ENETC_BD_CNT;
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tx_bdr->next_prod_idx = 0;
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tx_bdr->next_cons_idx = 0;
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tx_bdr->cons_idx = priv->regs_base +
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ENETC_BDR(TX, ENETC_TX_BDR_ID, ENETC_TBCIR);
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tx_bdr->prod_idx = priv->regs_base +
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ENETC_BDR(TX, ENETC_TX_BDR_ID, ENETC_TBPIR);
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/* set Tx BD address */
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enetc_bdr_write(priv, TX, ENETC_TX_BDR_ID, ENETC_TBBAR0,
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lower_32_bits(tx_bd_add));
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enetc_bdr_write(priv, TX, ENETC_TX_BDR_ID, ENETC_TBBAR1,
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upper_32_bits(tx_bd_add));
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/* set Tx 8 BD count */
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enetc_bdr_write(priv, TX, ENETC_TX_BDR_ID, ENETC_TBLENR,
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tx_bdr->bd_count);
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/* reset both producer/consumer indexes */
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enetc_write_reg(tx_bdr->cons_idx, tx_bdr->next_cons_idx);
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enetc_write_reg(tx_bdr->prod_idx, tx_bdr->next_prod_idx);
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/* enable TX ring */
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enetc_bdr_write(priv, TX, ENETC_TX_BDR_ID, ENETC_TBMR, ENETC_TBMR_EN);
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}
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/*
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* Setup a single Rx BD Ring (ID = 0):
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* - set Rx buffer descriptors address (one descriptor per buffer)
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* - set buffer size as max frame size
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* - enable Rx ring
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* - reset consumer and producer indexes
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* - set buffer for each descriptor
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*/
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static void enetc_setup_rx_bdr(struct udevice *dev)
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{
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struct enetc_priv *priv = dev_get_priv(dev);
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struct bd_ring *rx_bdr = &priv->rx_bdr;
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u64 rx_bd_add = (u64)priv->enetc_rxbd;
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int i;
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/* used later to advance to the next BD produced by ENETC HW */
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rx_bdr->bd_count = ENETC_BD_CNT;
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rx_bdr->next_prod_idx = 0;
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rx_bdr->next_cons_idx = 0;
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rx_bdr->cons_idx = priv->regs_base +
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ENETC_BDR(RX, ENETC_RX_BDR_ID, ENETC_RBCIR);
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rx_bdr->prod_idx = priv->regs_base +
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ENETC_BDR(RX, ENETC_RX_BDR_ID, ENETC_RBPIR);
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/* set Rx BD address */
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enetc_bdr_write(priv, RX, ENETC_RX_BDR_ID, ENETC_RBBAR0,
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lower_32_bits(rx_bd_add));
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enetc_bdr_write(priv, RX, ENETC_RX_BDR_ID, ENETC_RBBAR1,
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upper_32_bits(rx_bd_add));
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/* set Rx BD count (multiple of 8) */
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enetc_bdr_write(priv, RX, ENETC_RX_BDR_ID, ENETC_RBLENR,
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rx_bdr->bd_count);
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/* set Rx buffer size */
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enetc_bdr_write(priv, RX, ENETC_RX_BDR_ID, ENETC_RBBSR, PKTSIZE_ALIGN);
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/* fill Rx BD */
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memset(priv->enetc_rxbd, 0,
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rx_bdr->bd_count * sizeof(union enetc_rx_bd));
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for (i = 0; i < rx_bdr->bd_count; i++) {
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priv->enetc_rxbd[i].w.addr = enetc_rxb_address(dev, i);
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/* each RX buffer must be aligned to 64B */
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WARN_ON(priv->enetc_rxbd[i].w.addr & (ARCH_DMA_MINALIGN - 1));
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}
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/* reset producer (ENETC owned) and consumer (SW owned) index */
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enetc_write_reg(rx_bdr->cons_idx, rx_bdr->next_cons_idx);
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enetc_write_reg(rx_bdr->prod_idx, rx_bdr->next_prod_idx);
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/* enable Rx ring */
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enetc_bdr_write(priv, RX, ENETC_RX_BDR_ID, ENETC_RBMR, ENETC_RBMR_EN);
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}
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/*
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* Start ENETC interface:
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* - perform FLR
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* - enable access to port and SI registers
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* - set mac address
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* - setup TX/RX buffer descriptors
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* - enable Tx/Rx rings
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*/
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static int enetc_start(struct udevice *dev)
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{
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struct eth_pdata *plat = dev_get_platdata(dev);
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struct enetc_priv *priv = dev_get_priv(dev);
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/* reset and enable the PCI device */
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dm_pci_flr(dev);
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dm_pci_clrset_config16(dev, PCI_COMMAND, 0,
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PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
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if (!is_valid_ethaddr(plat->enetaddr)) {
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enetc_dbg(dev, "invalid MAC address, generate random ...\n");
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net_random_ethaddr(plat->enetaddr);
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}
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enetc_set_primary_mac_addr(priv, plat->enetaddr);
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enetc_enable_si_port(priv);
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/* setup Tx/Rx buffer descriptors */
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enetc_setup_tx_bdr(dev);
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enetc_setup_rx_bdr(dev);
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return 0;
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}
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/*
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* Stop the network interface:
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* - just quiesce it, we can wipe all configuration as _start starts from
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* scratch each time
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*/
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static void enetc_stop(struct udevice *dev)
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{
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/* FLR is sufficient to quiesce the device */
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dm_pci_flr(dev);
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}
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/*
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* ENETC transmit packet:
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* - check if Tx BD ring is full
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* - set buffer/packet address (dma address)
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* - set final fragment flag
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* - try while producer index equals consumer index or timeout
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*/
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static int enetc_send(struct udevice *dev, void *packet, int length)
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{
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struct enetc_priv *priv = dev_get_priv(dev);
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struct bd_ring *txr = &priv->tx_bdr;
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void *nv_packet = (void *)packet;
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int tries = ENETC_POLL_TRIES;
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u32 pi, ci;
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pi = txr->next_prod_idx;
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ci = enetc_read_reg(txr->cons_idx) & ENETC_BDR_IDX_MASK;
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/* Tx ring is full when */
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if (((pi + 1) % txr->bd_count) == ci) {
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enetc_dbg(dev, "Tx BDR full\n");
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return -ETIMEDOUT;
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}
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enetc_dbg(dev, "TxBD[%d]send: pkt_len=%d, buff @0x%x%08x\n", pi, length,
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upper_32_bits((u64)nv_packet), lower_32_bits((u64)nv_packet));
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/* prepare Tx BD */
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memset(&priv->enetc_txbd[pi], 0x0, sizeof(struct enetc_tx_bd));
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priv->enetc_txbd[pi].addr =
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cpu_to_le64(dm_pci_virt_to_mem(dev, nv_packet));
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priv->enetc_txbd[pi].buf_len = cpu_to_le16(length);
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priv->enetc_txbd[pi].frm_len = cpu_to_le16(length);
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priv->enetc_txbd[pi].flags = cpu_to_le16(ENETC_TXBD_FLAGS_F);
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dmb();
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/* send frame: increment producer index */
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pi = (pi + 1) % txr->bd_count;
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txr->next_prod_idx = pi;
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enetc_write_reg(txr->prod_idx, pi);
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while ((--tries >= 0) &&
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(pi != (enetc_read_reg(txr->cons_idx) & ENETC_BDR_IDX_MASK)))
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udelay(10);
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return tries > 0 ? 0 : -ETIMEDOUT;
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}
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/*
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* Receive frame:
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* - wait for the next BD to get ready bit set
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* - clean up the descriptor
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* - move on and indicate to HW that the cleaned BD is available for Rx
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*/
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static int enetc_recv(struct udevice *dev, int flags, uchar **packetp)
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{
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struct enetc_priv *priv = dev_get_priv(dev);
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struct bd_ring *rxr = &priv->rx_bdr;
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int tries = ENETC_POLL_TRIES;
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int pi = rxr->next_prod_idx;
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int ci = rxr->next_cons_idx;
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u32 status;
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int len;
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u8 rdy;
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do {
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dmb();
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status = le32_to_cpu(priv->enetc_rxbd[pi].r.lstatus);
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/* check if current BD is ready to be consumed */
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rdy = ENETC_RXBD_STATUS_R(status);
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} while (--tries >= 0 && !rdy);
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if (!rdy)
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return -EAGAIN;
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dmb();
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len = le16_to_cpu(priv->enetc_rxbd[pi].r.buf_len);
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*packetp = (uchar *)enetc_rxb_address(dev, pi);
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enetc_dbg(dev, "RxBD[%d]: len=%d err=%d pkt=0x%x%08x\n", pi, len,
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ENETC_RXBD_STATUS_ERRORS(status),
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upper_32_bits((u64)*packetp), lower_32_bits((u64)*packetp));
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/* BD clean up and advance to next in ring */
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memset(&priv->enetc_rxbd[pi], 0, sizeof(union enetc_rx_bd));
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priv->enetc_rxbd[pi].w.addr = enetc_rxb_address(dev, pi);
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rxr->next_prod_idx = (pi + 1) % rxr->bd_count;
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ci = (ci + 1) % rxr->bd_count;
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rxr->next_cons_idx = ci;
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dmb();
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/* free up the slot in the ring for HW */
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enetc_write_reg(rxr->cons_idx, ci);
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return len;
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}
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static const struct eth_ops enetc_ops = {
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.start = enetc_start,
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.send = enetc_send,
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.recv = enetc_recv,
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.stop = enetc_stop,
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};
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U_BOOT_DRIVER(eth_enetc) = {
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.name = "enetc_eth",
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.id = UCLASS_ETH,
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.bind = enetc_bind,
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.probe = enetc_probe,
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.remove = enetc_remove,
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.ops = &enetc_ops,
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.priv_auto_alloc_size = sizeof(struct enetc_priv),
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.platdata_auto_alloc_size = sizeof(struct eth_pdata),
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};
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static struct pci_device_id enetc_ids[] = {
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{ PCI_DEVICE(PCI_VENDOR_ID_FREESCALE, PCI_DEVICE_ID_ENETC_ETH) },
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{}
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};
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U_BOOT_PCI_DEVICE(eth_enetc, enetc_ids);
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168
drivers/net/fsl_enetc.h
Normal file
168
drivers/net/fsl_enetc.h
Normal file
@ -0,0 +1,168 @@
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/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* ENETC ethernet controller driver
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* Copyright 2017-2019 NXP
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*/
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#ifndef _ENETC_H
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#define _ENETC_H
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#define enetc_dbg(dev, fmt, args...) debug("%s:" fmt, dev->name, ##args)
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/* PCI function IDs */
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#define PCI_DEVICE_ID_ENETC_ETH 0xE100
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|
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/* ENETC Ethernet controller registers */
|
||||
/* Station interface register offsets */
|
||||
#define ENETC_SIMR 0x000
|
||||
#define ENETC_SIMR_EN BIT(31)
|
||||
#define ENETC_SICAR0 0x040
|
||||
/* write cache cfg: snoop, no allocate, data & BD coherent */
|
||||
#define ENETC_SICAR_WR_CFG 0x6767
|
||||
/* read cache cfg: coherent copy, look up, don't alloc in cache */
|
||||
#define ENETC_SICAR_RD_CFG 0x27270000
|
||||
#define ENETC_SIROCT 0x300
|
||||
#define ENETC_SIRFRM 0x308
|
||||
#define ENETC_SITOCT 0x320
|
||||
#define ENETC_SITFRM 0x328
|
||||
|
||||
/* Rx/Tx Buffer Descriptor Ring registers */
|
||||
enum enetc_bdr_type {TX, RX};
|
||||
#define ENETC_BDR(type, n, off) (0x8000 + (type) * 0x100 + (n) * 0x200 + (off))
|
||||
#define ENETC_BDR_IDX_MASK 0xffff
|
||||
|
||||
/* Rx BDR reg offsets */
|
||||
#define ENETC_RBMR 0x00
|
||||
#define ENETC_RBMR_EN BIT(31)
|
||||
#define ENETC_RBBSR 0x08
|
||||
/* initial consumer index for Rx BDR */
|
||||
#define ENETC_RBCIR 0x0c
|
||||
#define ENETC_RBBAR0 0x10
|
||||
#define ENETC_RBBAR1 0x14
|
||||
#define ENETC_RBPIR 0x18
|
||||
#define ENETC_RBLENR 0x20
|
||||
|
||||
/* Tx BDR reg offsets */
|
||||
#define ENETC_TBMR 0x00
|
||||
#define ENETC_TBMR_EN BIT(31)
|
||||
#define ENETC_TBBAR0 0x10
|
||||
#define ENETC_TBBAR1 0x14
|
||||
#define ENETC_TBPIR 0x18
|
||||
#define ENETC_TBCIR 0x1c
|
||||
#define ENETC_TBLENR 0x20
|
||||
|
||||
/* Port registers offset */
|
||||
#define ENETC_PORT_REGS_OFF 0x10000
|
||||
|
||||
/* Port registers */
|
||||
#define ENETC_PMR 0x0000
|
||||
#define ENETC_PMR_SI0_EN BIT(16)
|
||||
#define ENETC_PSIPMMR 0x0018
|
||||
#define ENETC_PSIPMAR0 0x0100
|
||||
#define ENETC_PSIPMAR1 0x0104
|
||||
#define ENETC_PSICFGR(n) (0x0940 + (n) * 0x10)
|
||||
#define ENETC_PSICFGR_SET_TXBDR(val) ((val) & 0xff)
|
||||
#define ENETC_PSICFGR_SET_RXBDR(val) (((val) & 0xff) << 16)
|
||||
/* MAC configuration */
|
||||
#define ENETC_PM_CC 0x8008
|
||||
#define ENETC_PM_CC_DEFAULT 0x0810
|
||||
#define ENETC_PM_CC_RX_TX_EN 0x8813
|
||||
#define ENETC_PM_MAXFRM 0x8014
|
||||
#define ENETC_RX_MAXFRM_SIZE PKTSIZE_ALIGN
|
||||
|
||||
/* buffer descriptors count must be multiple of 8 and aligned to 128 bytes */
|
||||
#define ENETC_BD_CNT CONFIG_SYS_RX_ETH_BUFFER
|
||||
#define ENETC_BD_ALIGN 128
|
||||
|
||||
/* single pair of Rx/Tx rings */
|
||||
#define ENETC_RX_BDR_CNT 1
|
||||
#define ENETC_TX_BDR_CNT 1
|
||||
#define ENETC_RX_BDR_ID 0
|
||||
#define ENETC_TX_BDR_ID 0
|
||||
|
||||
/* Tx buffer descriptor */
|
||||
struct enetc_tx_bd {
|
||||
__le64 addr;
|
||||
__le16 buf_len;
|
||||
__le16 frm_len;
|
||||
__le16 err_csum;
|
||||
__le16 flags;
|
||||
};
|
||||
|
||||
#define ENETC_TXBD_FLAGS_F BIT(15)
|
||||
#define ENETC_POLL_TRIES 32000
|
||||
|
||||
/* Rx buffer descriptor */
|
||||
union enetc_rx_bd {
|
||||
/* SW provided BD format */
|
||||
struct {
|
||||
__le64 addr;
|
||||
u8 reserved[8];
|
||||
} w;
|
||||
|
||||
/* ENETC returned BD format */
|
||||
struct {
|
||||
__le16 inet_csum;
|
||||
__le16 parse_summary;
|
||||
__le32 rss_hash;
|
||||
__le16 buf_len;
|
||||
__le16 vlan_opt;
|
||||
union {
|
||||
struct {
|
||||
__le16 flags;
|
||||
__le16 error;
|
||||
};
|
||||
__le32 lstatus;
|
||||
};
|
||||
} r;
|
||||
};
|
||||
|
||||
#define ENETC_RXBD_STATUS_R(status) (((status) >> 30) & 0x1)
|
||||
#define ENETC_RXBD_STATUS_F(status) (((status) >> 31) & 0x1)
|
||||
#define ENETC_RXBD_STATUS_ERRORS(status) (((status) >> 16) & 0xff)
|
||||
#define ENETC_RXBD_STATUS(flags) ((flags) << 16)
|
||||
|
||||
/* Tx/Rx ring info */
|
||||
struct bd_ring {
|
||||
void *cons_idx;
|
||||
void *prod_idx;
|
||||
/* next BD index to use */
|
||||
int next_prod_idx;
|
||||
int next_cons_idx;
|
||||
int bd_count;
|
||||
};
|
||||
|
||||
/* ENETC private structure */
|
||||
struct enetc_priv {
|
||||
struct enetc_tx_bd *enetc_txbd;
|
||||
union enetc_rx_bd *enetc_rxbd;
|
||||
|
||||
void *regs_base; /* base ENETC registers */
|
||||
void *port_regs; /* base ENETC port registers */
|
||||
|
||||
/* Rx/Tx buffer descriptor rings info */
|
||||
struct bd_ring tx_bdr;
|
||||
struct bd_ring rx_bdr;
|
||||
};
|
||||
|
||||
/* register accessors */
|
||||
#define enetc_read_reg(x) readl((x))
|
||||
#define enetc_write_reg(x, val) writel((val), (x))
|
||||
#define enetc_read(priv, off) enetc_read_reg((priv)->regs_base + (off))
|
||||
#define enetc_write(priv, off, v) \
|
||||
enetc_write_reg((priv)->regs_base + (off), v)
|
||||
|
||||
/* port register accessors */
|
||||
#define enetc_port_regs(priv, off) ((priv)->port_regs + (off))
|
||||
#define enetc_read_port(priv, off) \
|
||||
enetc_read_reg(enetc_port_regs((priv), (off)))
|
||||
#define enetc_write_port(priv, off, v) \
|
||||
enetc_write_reg(enetc_port_regs((priv), (off)), v)
|
||||
|
||||
/* BDR register accessors, see ENETC_BDR() */
|
||||
#define enetc_bdr_read(priv, t, n, off) \
|
||||
enetc_read(priv, ENETC_BDR(t, n, off))
|
||||
#define enetc_bdr_write(priv, t, n, off, val) \
|
||||
enetc_write(priv, ENETC_BDR(t, n, off), val)
|
||||
|
||||
#endif /* _ENETC_H */
|
Loading…
Reference in New Issue
Block a user