imx6: aristainetos: readd aristainetos 2b board
readd aristainetos 2b board. Signed-off-by: Heiko Schocher <hs@denx.de>
This commit is contained in:
Heiko Schocher
Stefano Babic
parent
1c9c4642c3
commit
1204b9675e
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@ -578,6 +578,8 @@ ifneq ($(CONFIG_MX6DL)$(CONFIG_MX6QDL)$(CONFIG_MX6S),)
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dtb-y += \
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imx6dl-aristainetos2_4.dtb \
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imx6dl-aristainetos2_7.dtb \
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imx6dl-aristainetos2b_4.dtb \
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imx6dl-aristainetos2b_7.dtb \
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imx6dl-brppt2.dtb \
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imx6dl-dhcom-pdk2.dtb \
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imx6dl-icore.dtb \
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@ -0,0 +1,13 @@
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// SPDX-License-Identifier: GPL-2.0+ or X11
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/*
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* Copyright (C) 2019 Heiko Schocher <hs@denx.de>
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*/
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#include <imx6qdl-aristainetos2b-u-boot.dtsi>
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&lcd_panel {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_ipu_disp>;
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enable-gpios = <&gpio6 15 GPIO_ACTIVE_HIGH>;
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backlight = <&backlight>;
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};
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@ -0,0 +1,50 @@
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// SPDX-License-Identifier: (GPL-2.0)
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/*
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* support for the imx6 based aristainetos2b board
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* parts for 4.3 inch LG display on spi1 port1
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*
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* Copyright (C) 2019 Heiko Schocher <hs@denx.de>
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*
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*/
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/dts-v1/;
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#include "imx6dl-aristainetos2_4.dtsi"
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#include "imx6qdl-aristainetos2b.dtsi"
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/ {
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model = "aristainetos2b i.MX6 Dual Lite Board 4";
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compatible = "fsl,imx6dl";
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};
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&ecspi1 {
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lcd_panel: display@0 {
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compatible = "lg,lg4573";
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spi-max-frequency = <10000000>;
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reg = <1>;
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power-on-delay = <10>;
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display-timings {
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480x800p57 {
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native-mode;
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clock-frequency = <27000027>;
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hactive = <480>;
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vactive = <800>;
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hfront-porch = <10>;
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hback-porch = <59>;
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hsync-len = <10>;
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vback-porch = <15>;
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vfront-porch = <15>;
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vsync-len = <15>;
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hsync-active = <1>;
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vsync-active = <1>;
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};
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};
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port {
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panel_in: endpoint {
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remote-endpoint = <&display_out>;
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};
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};
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};
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};
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@ -0,0 +1,19 @@
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// SPDX-License-Identifier: GPL-2.0+ or X11
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/*
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* Copyright (C) 2019 Heiko Schocher <hs@denx.de>
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*/
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#include <imx6qdl-aristainetos2b-u-boot.dtsi>
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/ {
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vdd_panel_reg: regulator-panel {
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compatible = "regulator-fixed";
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regulator-name = "panel_regulator";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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regulator-always-on;
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};
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};
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&panel0 {
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power-supply = <&vdd_panel_reg>;
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};
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@ -0,0 +1,16 @@
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// SPDX-License-Identifier: (GPL-2.0)
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/*
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* support for the imx6 based aristainetos2 board
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*
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* Copyright (C) 2019 Heiko Schocher <hs@denx.de>
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* Copyright (C) 2015 Heiko Schocher <hs@denx.de>
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*
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*/
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/dts-v1/;
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#include "imx6dl-aristainetos2_7.dtsi"
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#include "imx6qdl-aristainetos2b.dtsi"
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/ {
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model = "aristainetos2b i.MX6 Dual Lite Board 7";
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compatible = "fsl,imx6dl";
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};
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@ -0,0 +1,77 @@
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// SPDX-License-Identifier: GPL-2.0+ or X11
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/*
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* Copyright (C) 2019 Heiko Schocher <hs@denx.de>
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*/
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/ {
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chosen {
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u-boot,dm-pre-reloc;
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stdout-path = &uart2;
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};
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wdt-reboot {
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compatible = "wdt-reboot";
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wdt = <&wdog1>;
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};
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};
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&uart2 {
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u-boot,dm-pre-reloc;
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};
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&pinctrl_gpio {
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u-boot,dm-pre-reloc;
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};
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&pinctrl_uart2 {
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u-boot,dm-pre-reloc;
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};
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&iomuxc {
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u-boot,dm-pre-reloc;
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};
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&aips2 {
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u-boot,dm-pre-reloc;
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};
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&backlight {
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pwms = <&pwm1 0 300000>;
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default-brightness-level = <2>;
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};
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/*
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* allow switching write protect / reset pin by gpio,
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* because "pinctrl-assert-gpios" from &ecspi1 isn't handled by u-boot
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*/
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&gpio2 {
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u-boot,dm-pre-reloc;
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wp_spi_nor {
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gpio-hog;
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output-high;
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gpios = <15 GPIO_ACTIVE_HIGH>;
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};
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reset_spi_nor {
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gpio-hog;
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output-high;
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gpios = <28 GPIO_ACTIVE_HIGH>;
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};
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};
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&gpio4 {
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u-boot,dm-pre-reloc;
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};
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&ecspi1 {
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u-boot,dm-pre-reloc;
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};
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&flash {
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u-boot,dm-pre-reloc;
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};
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&pinctrl_ecspi1 {
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u-boot,dm-pre-reloc;
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};
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@ -0,0 +1,266 @@
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// SPDX-License-Identifier: (GPL-2.0)
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/*
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* support for the imx6 based aristainetos2b board
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*
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* Copyright (C) 2019 Heiko Schocher <hs@denx.de>
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* Copyright (C) 2015 Heiko Schocher <hs@denx.de>
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*
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*/
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/clock/imx6qdl-clock.h>
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#include "imx6qdl-aristainetos2-common.dtsi"
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/ {
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leds {
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compatible = "gpio-leds";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_gpio>;
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LED_blue {
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label = "led_blue";
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gpios = <&gpio2 29 GPIO_ACTIVE_HIGH>;
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};
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LED_green {
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label = "led_green";
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gpios = <&gpio5 4 GPIO_ACTIVE_HIGH>;
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};
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LED_red {
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label = "led_red";
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gpios = <&gpio5 0 GPIO_ACTIVE_HIGH>;
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};
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LED_yellow {
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label = "led_yellow";
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gpios = <&gpio6 16 GPIO_ACTIVE_HIGH>;
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};
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LED_ena {
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label = "led_ena";
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gpios = <&gpio1 25 GPIO_ACTIVE_LOW>;
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};
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};
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};
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&ecspi1 {
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fsl,spi-num-chipselects = <3>;
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cs-gpios = <&gpio2 30 GPIO_ACTIVE_HIGH
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&gpio4 10 GPIO_ACTIVE_HIGH
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&gpio4 11 GPIO_ACTIVE_HIGH>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_ecspi1>;
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status = "okay";
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pinctrl-assert-gpios = <&gpio2 28 GPIO_ACTIVE_HIGH>;
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pinctrl-assert-gpios = <&gpio2 15 GPIO_ACTIVE_HIGH>;
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flash: m25p80@0 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "micron,n25q128a11", "jedec,spi-nor";
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spi-max-frequency = <20000000>;
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reg = <0>;
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};
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};
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&ecspi4 {
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fsl,spi-num-chipselects = <2>;
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cs-gpios = <&gpio3 29 GPIO_ACTIVE_HIGH &gpio5 2 GPIO_ACTIVE_HIGH>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_ecspi4>;
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status = "okay";
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};
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&i2c1 {
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tpm@20 {
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compatible = "infineon,slb9645tt";
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reg = <0x20>;
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};
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};
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&gpio7 {
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sd2_driver_ena {
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gpio-hog;
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output-high;
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gpios = <8 GPIO_ACTIVE_HIGH>;
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};
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};
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&gpmi {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_gpmi_nand>;
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status = "okay";
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};
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&can1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_flexcan1>;
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status = "okay";
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};
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&can2 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_flexcan2>;
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status = "okay";
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};
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&usdhc1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_usdhc1>;
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cd-gpios = <&gpio1 27 GPIO_ACTIVE_LOW>;
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wp-gpios = <&gpio4 20 GPIO_ACTIVE_HIGH>;
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no-1-8-v;
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status = "okay";
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};
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&usdhc2 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_usdhc2>;
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/*
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* comment out this line to make the WiFi Eval-Module work in
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* SD-Slot2, and add line:
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* broken-cd;
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* causes 6% CPU load if no WiFi module installed (polling)
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*/
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cd-gpios = <&gpio4 5 GPIO_ACTIVE_LOW>;
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wp-gpios = <&gpio2 10 GPIO_ACTIVE_HIGH>;
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no-1-8-v;
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status = "okay";
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};
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&iomuxc {
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pinctrl_ecspi1: ecspi1grp {
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fsl,pins = <
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MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1
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MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1
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MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1
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/* SS0# */
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MX6QDL_PAD_EIM_EB2__GPIO2_IO30 0x100b1
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/* SS1# */
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MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x100b1
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/* SS2# */
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MX6QDL_PAD_KEY_ROW2__GPIO4_IO11 0x100b1
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/* WP pin NOR Flash */
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MX6QDL_PAD_SD4_DAT7__GPIO2_IO15 0x4001b0b0
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/* Flash nReset */
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MX6QDL_PAD_EIM_EB0__GPIO2_IO28 0x4001b0b0
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>;
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};
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pinctrl_ecspi4: ecspi4grp {
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fsl,pins = <
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MX6QDL_PAD_EIM_D21__ECSPI4_SCLK 0x100b1
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MX6QDL_PAD_EIM_D22__ECSPI4_MISO 0x100b1
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MX6QDL_PAD_EIM_D28__ECSPI4_MOSI 0x100b1
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MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x100b1 /* SS0# */
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MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x100b1 /* SS1# */
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>;
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};
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pinctrl_gpio: gpiogrp {
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fsl,pins = <
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/* led enable */
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MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x4001b0b0
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/* LCD power enable */
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MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x4001b0b0
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/* led yellow */
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MX6QDL_PAD_NANDF_CS3__GPIO6_IO16 0x4001b0b0
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/* led red */
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MX6QDL_PAD_EIM_WAIT__GPIO5_IO00 0x4001b0b0
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/* led green */
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MX6QDL_PAD_EIM_A24__GPIO5_IO04 0x4001b0b0
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/* led blue */
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MX6QDL_PAD_EIM_EB1__GPIO2_IO29 0x4001b0b0
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/* Profibus IRQ */
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MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x1b0b0
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/* FPGA IRQ currently unused*/
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MX6QDL_PAD_SD3_DAT6__GPIO6_IO18 0x1b0b0
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/* Display reset because of clock failure */
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MX6QDL_PAD_SD4_DAT3__GPIO2_IO11 0x4001b0b0
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/* spi bus #2 SS driver enable */
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MX6QDL_PAD_EIM_A23__GPIO6_IO06 0x4001b0b0
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/* RST_LOC# PHY reset input (has pull-down!)*/
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MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x4001b0b0
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/* Touchscreen IRQ */
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MX6QDL_PAD_SD4_DAT1__GPIO2_IO09 0x1b0b0
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/* PCIe reset */
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MX6QDL_PAD_EIM_A22__GPIO2_IO16 0x4001b0b0
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/* make sure pin is GPIO and not ENET_REF_CLK */
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MX6QDL_PAD_GPIO_16__GPIO7_IO11 0x4001a0b0
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/* SD2 level shifter output enable / SD2 Reset# */
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MX6QDL_PAD_SD3_RST__GPIO7_IO08 0x4001b0b0
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>;
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};
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pinctrl_gpmi_nand: gpmi-nand {
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fsl,pins = <
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MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1
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MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1
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MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1
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MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000
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MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1
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MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1
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MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1
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MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1
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MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1
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MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1
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MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1
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MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1
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MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1
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MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1
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MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1
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>;
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};
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pinctrl_flexcan1: flexcan1grp {
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fsl,pins = <
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MX6QDL_PAD_SD3_CLK__FLEXCAN1_RX 0x1b0b0
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MX6QDL_PAD_SD3_CMD__FLEXCAN1_TX 0x1b0b0
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>;
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};
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pinctrl_flexcan2: flexcan2grp {
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fsl,pins = <
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MX6QDL_PAD_SD3_DAT0__FLEXCAN2_TX 0x1b0b0
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MX6QDL_PAD_SD3_DAT1__FLEXCAN2_RX 0x1b0b0
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>;
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};
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pinctrl_usbotg: usbotggrp {
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fsl,pins = <
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MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059
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MX6QDL_PAD_KEY_COL4__USB_OTG_OC 0x1b0b0
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>;
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};
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pinctrl_usdhc1: usdhc1grp {
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fsl,pins = <
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MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17059
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MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10059
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MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17059
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MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17059
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MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17059
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MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17059
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/* SD1 card detect input */
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MX6QDL_PAD_ENET_RXD0__GPIO1_IO27 0x1b0b0
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/* SD1 write protect input */
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MX6QDL_PAD_DI0_PIN4__GPIO4_IO20 0x1b0b0
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>;
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};
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pinctrl_usdhc2: usdhc2grp {
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fsl,pins = <
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MX6QDL_PAD_SD2_CMD__SD2_CMD 0x71
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MX6QDL_PAD_SD2_CLK__SD2_CLK 0x71
|
||||
MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x71
|
||||
MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x71
|
||||
MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x71
|
||||
MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x71
|
||||
/* SD2 card detect input */
|
||||
MX6QDL_PAD_GPIO_19__GPIO4_IO05 0x1b0b0
|
||||
/* SD2 write protect input */
|
||||
MX6QDL_PAD_SD4_DAT2__GPIO2_IO10 0x1b0b0
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
|
@ -136,6 +136,17 @@ config TARGET_ARISTAINETOS2
|
|||
imply CMD_SATA
|
||||
imply CMD_DM
|
||||
|
||||
config TARGET_ARISTAINETOS2B
|
||||
bool "Support aristainetos2-revB"
|
||||
select BOARD_LATE_INIT
|
||||
select MX6DL
|
||||
select SYS_I2C_MXC
|
||||
select MXC_UART
|
||||
select FEC_MXC
|
||||
select DM
|
||||
imply CMD_SATA
|
||||
imply CMD_DM
|
||||
|
||||
config TARGET_CGTQMX6EVAL
|
||||
bool "cgtqmx6eval"
|
||||
select BOARD_LATE_INIT
|
||||
|
|
|
|||
|
|
@ -9,3 +9,15 @@ config SYS_BOARD_VERSION
|
|||
default 2
|
||||
|
||||
endif
|
||||
|
||||
if TARGET_ARISTAINETOS2B
|
||||
|
||||
source "board/aristainetos/common/Kconfig"
|
||||
|
||||
config SYS_BOARD
|
||||
default "aristainetos"
|
||||
|
||||
config SYS_BOARD_VERSION
|
||||
default 3
|
||||
|
||||
endif
|
||||
|
|
|
|||
|
|
@ -4,6 +4,7 @@ S: Maintained
|
|||
F: board/aristainetos/
|
||||
F: include/configs/aristainetos2.h
|
||||
F: configs/aristainetos2_defconfig
|
||||
F: configs/aristainetos2b_defconfig
|
||||
F: arch/arm/dts/imx6qdl-aristainetos2.dtsi
|
||||
F: arch/arm/dts/imx6qdl-aristainetos2-common.dtsi
|
||||
F: arch/arm/dts/imx6qdl-aristainetos2-u-boot.dtsi
|
||||
|
|
@ -13,3 +14,9 @@ F: arch/arm/dts/imx6dl-aristainetos2_7-u-boot.dtsi
|
|||
F: arch/arm/dts/imx6dl-aristainetos2_4.dts
|
||||
F: arch/arm/dts/imx6dl-aristainetos2_4.dtsi
|
||||
F: arch/arm/dts/imx6dl-aristainetos2_4-u-boot.dtsi
|
||||
F: arch/arm/dts/imx6dl-aristainetos2b_4.dts
|
||||
F: arch/arm/dts/imx6dl-aristainetos2b_4-u-boot.dtsi
|
||||
F: arch/arm/dts/imx6dl-aristainetos2b_7.dts
|
||||
F: arch/arm/dts/imx6dl-aristainetos2b_7-u-boot.dtsi
|
||||
F: arch/arm/dts/imx6qdl-aristainetos2b-u-boot.dtsi
|
||||
F: arch/arm/dts/imx6qdl-aristainetos2b.dtsi
|
||||
|
|
|
|||
|
|
@ -3,6 +3,7 @@ config SYS_BOARD_VERSION
|
|||
help
|
||||
version of aristainetos board version
|
||||
2 version 2
|
||||
3 version 2b
|
||||
|
||||
config SYS_I2C_MXC_I2C1
|
||||
default y
|
||||
|
|
|
|||
|
|
@ -0,0 +1,115 @@
|
|||
CONFIG_ARM=y
|
||||
CONFIG_SYS_THUMB_BUILD=y
|
||||
CONFIG_ARCH_MX6=y
|
||||
CONFIG_SYS_TEXT_BASE=0x17800000
|
||||
CONFIG_SYS_MALLOC_F_LEN=0xe000
|
||||
CONFIG_ENV_SIZE=0x3000
|
||||
CONFIG_ENV_OFFSET=0xD0000
|
||||
CONFIG_TARGET_ARISTAINETOS2B=y
|
||||
CONFIG_NR_DRAM_BANKS=1
|
||||
CONFIG_ENV_SECT_SIZE=0x10000
|
||||
CONFIG_IMX_HAB=y
|
||||
# CONFIG_CMD_DEKBLOB is not set
|
||||
# CONFIG_CMD_NANDBCB is not set
|
||||
CONFIG_FIT=y
|
||||
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/aristainetos/aristainetos2.cfg"
|
||||
CONFIG_BOOTDELAY=3
|
||||
CONFIG_USE_BOOTCOMMAND=y
|
||||
CONFIG_BOOTCOMMAND="run ari_boot"
|
||||
# CONFIG_CONSOLE_MUX is not set
|
||||
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
|
||||
CONFIG_SUPPORT_RAW_INITRD=y
|
||||
CONFIG_VERSION_VARIABLE=y
|
||||
CONFIG_BOUNCE_BUFFER=y
|
||||
CONFIG_BOARD_TYPES=y
|
||||
CONFIG_BOARD_EARLY_INIT_F=y
|
||||
CONFIG_HUSH_PARSER=y
|
||||
CONFIG_AUTOBOOT_KEYED=y
|
||||
CONFIG_AUTOBOOT_ENCRYPTION=y
|
||||
CONFIG_AUTOBOOT_STOP_STR_SHA256="30bb0bce5f77da71a6e8e436fe40af54bc823db9501ae170f77e9992499d88fb"
|
||||
CONFIG_CMD_BOOTZ=y
|
||||
# CONFIG_BOOTM_NETBSD is not set
|
||||
# CONFIG_BOOTM_PLAN9 is not set
|
||||
# CONFIG_BOOTM_RTEMS is not set
|
||||
# CONFIG_BOOTM_VXWORKS is not set
|
||||
# CONFIG_CMD_FLASH is not set
|
||||
CONFIG_CMD_GPIO=y
|
||||
CONFIG_CMD_I2C=y
|
||||
CONFIG_CMD_MMC=y
|
||||
CONFIG_CMD_NAND_TRIMFFS=y
|
||||
# CONFIG_CMD_PINMUX is not set
|
||||
# CONFIG_CMD_SATA is not set
|
||||
CONFIG_CMD_USB=y
|
||||
CONFIG_CMD_DHCP=y
|
||||
CONFIG_CMD_MII=y
|
||||
CONFIG_CMD_PING=y
|
||||
CONFIG_CMD_BMP=y
|
||||
CONFIG_CMD_CACHE=y
|
||||
# CONFIG_CMD_HASH is not set
|
||||
CONFIG_CMD_EXT2=y
|
||||
CONFIG_CMD_EXT4=y
|
||||
CONFIG_CMD_EXT4_WRITE=y
|
||||
CONFIG_CMD_FAT=y
|
||||
CONFIG_CMD_FS_GENERIC=y
|
||||
CONFIG_CMD_MTDPARTS=y
|
||||
CONFIG_CMD_UBI=y
|
||||
CONFIG_OF_CONTROL=y
|
||||
CONFIG_DEFAULT_DEVICE_TREE="imx6dl-aristainetos2b_4"
|
||||
CONFIG_OF_LIST="imx6dl-aristainetos2b_4 imx6dl-aristainetos2b_7"
|
||||
CONFIG_DTB_RESELECT=y
|
||||
CONFIG_MULTI_DTB_FIT=y
|
||||
CONFIG_ENV_IS_IN_SPI_FLASH=y
|
||||
CONFIG_ENV_SPI_EARLY=y
|
||||
CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
|
||||
CONFIG_ENV_OFFSET_REDUND=0xE0000
|
||||
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
|
||||
CONFIG_DM_GPIO=y
|
||||
CONFIG_GPIO_HOG=y
|
||||
CONFIG_DM_PCA953X=y
|
||||
CONFIG_DM_I2C=y
|
||||
CONFIG_LED=y
|
||||
CONFIG_LED_GPIO=y
|
||||
CONFIG_MISC=y
|
||||
CONFIG_I2C_EEPROM=y
|
||||
CONFIG_DM_MMC=y
|
||||
CONFIG_FSL_USDHC=y
|
||||
CONFIG_MTD=y
|
||||
CONFIG_NAND=y
|
||||
CONFIG_NAND_MXS=y
|
||||
CONFIG_DM_SPI_FLASH=y
|
||||
CONFIG_SF_DEFAULT_MODE=0
|
||||
CONFIG_SF_DEFAULT_SPEED=20000000
|
||||
CONFIG_SPI_FLASH_STMICRO=y
|
||||
CONFIG_SPI_FLASH_MTD=y
|
||||
CONFIG_MTD_UBI_FASTMAP=y
|
||||
CONFIG_MTD_UBI_FASTMAP_AUTOCONVERT=1
|
||||
CONFIG_PHYLIB=y
|
||||
CONFIG_PHY_MICREL=y
|
||||
CONFIG_PHY_MICREL_KSZ90X1=y
|
||||
CONFIG_DM_ETH=y
|
||||
CONFIG_MII=y
|
||||
CONFIG_PHY=y
|
||||
CONFIG_PINCTRL=y
|
||||
CONFIG_PINCTRL_IMX6=y
|
||||
CONFIG_DM_PMIC=y
|
||||
CONFIG_DM_REGULATOR=y
|
||||
CONFIG_DM_REGULATOR_FIXED=y
|
||||
CONFIG_DM_PWM=y
|
||||
CONFIG_PWM_IMX=y
|
||||
CONFIG_DM_RTC=y
|
||||
CONFIG_RTC_DS1307=y
|
||||
CONFIG_DM_SERIAL=y
|
||||
CONFIG_SPI=y
|
||||
CONFIG_DM_SPI=y
|
||||
CONFIG_MXC_SPI=y
|
||||
CONFIG_SYSRESET=y
|
||||
CONFIG_SYSRESET_WATCHDOG=y
|
||||
CONFIG_USB=y
|
||||
CONFIG_DM_USB=y
|
||||
CONFIG_USB_STORAGE=y
|
||||
CONFIG_DM_VIDEO=y
|
||||
CONFIG_SYS_WHITE_ON_BLACK=y
|
||||
CONFIG_DISPLAY=y
|
||||
CONFIG_VIDEO_IPUV3=y
|
||||
CONFIG_IMX_WATCHDOG=y
|
||||
# CONFIG_EFI_LOADER is not set
|
||||
|
|
@ -86,6 +86,28 @@
|
|||
"enable_hab_check=0\0"
|
||||
#endif
|
||||
|
||||
#if (CONFIG_SYS_BOARD_VERSION == 3)
|
||||
#define CONFIG_EXTRA_ENV_BOARD_SETTINGS \
|
||||
"dead=led led_red on\0" \
|
||||
"mtdids=nand0=gpmi-nand,nor0=spi0.0\0" \
|
||||
"mtdparts=mtdparts=spi0.0:832k(u-boot),64k(env),64k(env-red)," \
|
||||
"-(ubi-nor);gpmi-nand:-(ubi)\0" \
|
||||
"addmisc=setenv bootargs ${bootargs} net.ifnames=0 consoleblank=0 " \
|
||||
"bootmode=${bootmode} mmcpart=${mmcpart}\0" \
|
||||
"mainboot=echo Booting from SD-card ...; " \
|
||||
"run mainargs addmtd addmisc;" \
|
||||
"if test -n ${addmiscM}; then run addmiscM;fi;" \
|
||||
"if test -n ${addmiscC}; then run addmiscC;fi;" \
|
||||
"if test -n ${addmiscD}; then run addmiscD;fi;" \
|
||||
"run boot_board_type;" \
|
||||
"bootm ${fit_addr_r}\0" \
|
||||
"mainargs=setenv bootargs console=${console},${baudrate} " \
|
||||
"root=${mmcroot}\0" \
|
||||
"main_load_fit=ext4load mmc ${mmcdev}:${mmcpart} ${fit_addr_r} " \
|
||||
"${fit_file}\0" \
|
||||
"rescue_load_fit=ext4load mmc ${mmcdev}:${mmcrescuepart} " \
|
||||
"${fit_addr_r} ${rescue_fit_file}\0"
|
||||
#else
|
||||
#define CONFIG_EXTRA_ENV_BOARD_SETTINGS \
|
||||
"dead=led led_red on\0" \
|
||||
"mtdids=nand0=gpmi-nand,nor0=spi3.1\0" \
|
||||
|
|
@ -106,6 +128,7 @@
|
|||
"${fit_file}\0" \
|
||||
"rescue_load_fit=ext4load mmc ${mmcdev}:${mmcrescuepart} " \
|
||||
"${fit_addr_r} ${rescue_fit_file}\0"
|
||||
#endif
|
||||
|
||||
#define CONFIG_EXTRA_ENV_SETTINGS \
|
||||
"disable_giga=yes\0" \
|
||||
|
|
|
|||
Loading…
Reference in New Issue