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https://github.com/brain-hackers/u-boot-brain
synced 2024-09-22 20:50:25 +09:00
arm64: dts: imx8mm-beacon: Re-sync dts file with Linux 5.10-rc6
There have been some updates to the device trees, so re-sync. Signed-off-by: Adam Ford <aford173@gmail.com> Acked-by: Peng Fan <peng.fan@nxp.com>
This commit is contained in:
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15d79fcac0
commit
1170d2b759
@ -10,19 +10,19 @@
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led0 {
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label = "gen_led0";
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gpios = <&pca6416_1 4 GPIO_ACTIVE_HIGH>;
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default-state = "none";
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default-state = "off";
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};
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led1 {
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label = "gen_led1";
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gpios = <&pca6416_1 5 GPIO_ACTIVE_HIGH>;
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default-state = "none";
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default-state = "off";
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};
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led2 {
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label = "gen_led2";
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gpios = <&pca6416_1 6 GPIO_ACTIVE_HIGH>;
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default-state = "none";
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default-state = "off";
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};
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led3 {
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@ -70,7 +70,7 @@
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&ecspi2 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_espi2>;
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cs-gpios = <&gpio5 9 0>;
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cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>;
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status = "okay";
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eeprom@0 {
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@ -210,7 +210,7 @@
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>;
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};
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pinctrl_pcal6414: pcal6414-gpio {
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pinctrl_pcal6414: pcal6414-gpiogrp {
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fsl,pins = <
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MX8MM_IOMUXC_SAI2_MCLK_GPIO4_IO27 0x19
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>;
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@ -240,7 +240,7 @@
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>;
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};
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pinctrl_usdhc2_gpio: usdhc2grpgpio {
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pinctrl_usdhc2_gpio: usdhc2gpiogrp {
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fsl,pins = <
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MX8MM_IOMUXC_SD2_CD_B_USDHC2_CD_B 0x41
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MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41
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@ -259,7 +259,7 @@
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>;
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};
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pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
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pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
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fsl,pins = <
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MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194
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MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4
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@ -271,7 +271,7 @@
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>;
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};
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pinctrl_usdhc2_200mhz: usdhc2grp200mhz {
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pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
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fsl,pins = <
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MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196
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MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6
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@ -24,6 +24,26 @@
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cpu-supply = <&buck2_reg>;
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};
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&ddrc {
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operating-points-v2 = <&ddrc_opp_table>;
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ddrc_opp_table: opp-table {
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compatible = "operating-points-v2";
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opp-25M {
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opp-hz = /bits/ 64 <25000000>;
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};
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opp-100M {
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opp-hz = /bits/ 64 <100000000>;
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};
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opp-750M {
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opp-hz = /bits/ 64 <750000000>;
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};
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};
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};
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&fec1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_fec1>;
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@ -52,9 +72,10 @@
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pmic@4b {
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compatible = "rohm,bd71847";
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reg = <0x4b>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_pmic>;
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interrupt-parent = <&gpio1>;
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interrupts = <3 GPIO_ACTIVE_LOW>;
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interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
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rohm,reset-snvs-powered;
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regulators {
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@ -116,7 +137,7 @@
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ldo1_reg: LDO1 {
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regulator-name = "ldo1";
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regulator-min-microvolt = <3000000>;
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regulator-min-microvolt = <1600000>;
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regulator-max-microvolt = <3300000>;
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regulator-boot-on;
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regulator-always-on;
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@ -124,7 +145,7 @@
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ldo2_reg: LDO2 {
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regulator-name = "ldo2";
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regulator-min-microvolt = <900000>;
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regulator-min-microvolt = <800000>;
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regulator-max-microvolt = <900000>;
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regulator-boot-on;
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regulator-always-on;
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@ -164,7 +185,7 @@
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status = "okay";
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eeprom@50 {
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compatible = "microchip, at24c64d", "atmel,24c64";
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compatible = "microchip,24c64", "atmel,24c64";
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pagesize = <32>;
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read-only; /* Manufacturing EEPROM programmed at factory */
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reg = <0x50>;
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@ -190,6 +211,7 @@
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host-wakeup-gpios = <&gpio2 8 GPIO_ACTIVE_HIGH>;
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device-wakeup-gpios = <&gpio2 7 GPIO_ACTIVE_HIGH>;
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clocks = <&osc_32k>;
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max-speed = <4000000>;
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clock-names = "extclk";
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};
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};
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@ -270,9 +292,9 @@
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>;
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};
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pinctrl_pmic: pmicirq {
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pinctrl_pmic: pmicirqgrp {
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fsl,pins = <
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MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x41
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MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x141
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>;
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};
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@ -289,7 +311,7 @@
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>;
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};
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pinctrl_usdhc1_gpio: usdhc1grpgpio {
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pinctrl_usdhc1_gpio: usdhc1gpiogrp {
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fsl,pins = <
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MX8MM_IOMUXC_SD1_RESET_B_GPIO2_IO10 0x41
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>;
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@ -306,7 +328,7 @@
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>;
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};
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pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
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pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
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fsl,pins = <
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MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x194
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MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d4
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@ -317,7 +339,7 @@
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>;
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};
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pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
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pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
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fsl,pins = <
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MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x196
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MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d6
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@ -344,7 +366,7 @@
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>;
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};
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pinctrl_usdhc3_100mhz: usdhc3grp100mhz {
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pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
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fsl,pins = <
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MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x194
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MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4
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@ -360,7 +382,7 @@
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>;
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};
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pinctrl_usdhc3_200mhz: usdhc3grp200mhz {
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pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
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fsl,pins = <
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MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x196
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MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6
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