ARM: rmobile: Add R8A77995 SoC
Add bits to support yet another SoC, the R8A77995 D3 . Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
This commit is contained in:
Marek Vasut
Marek Vasut
parent
5cb19e7ad5
commit
1154541a52
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@ -0,0 +1,410 @@
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/*
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* Device Tree Source for the r8a77995 SoC
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*
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* Copyright (C) 2016 Renesas Electronics Corp.
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* Copyright (C) 2017 Glider bvba
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*
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* This file is licensed under the terms of the GNU General Public License
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* version 2. This program is licensed "as is" without any warranty of any
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* kind, whether express or implied.
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*/
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#include <dt-bindings/clock/r8a77995-cpg-mssr.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/power/r8a77995-sysc.h>
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/ {
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compatible = "renesas,r8a77995";
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#address-cells = <2>;
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#size-cells = <2>;
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psci {
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compatible = "arm,psci-1.0", "arm,psci-0.2";
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method = "smc";
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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a53_0: cpu@0 {
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compatible = "arm,cortex-a53", "arm,armv8";
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reg = <0x0>;
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device_type = "cpu";
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power-domains = <&sysc R8A77995_PD_CA53_CPU0>;
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next-level-cache = <&L2_CA53>;
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enable-method = "psci";
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};
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L2_CA53: cache-controller-1 {
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compatible = "cache";
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power-domains = <&sysc R8A77995_PD_CA53_SCU>;
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cache-unified;
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cache-level = <2>;
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};
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};
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extal_clk: extal {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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/* This value must be overridden by the board */
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clock-frequency = <0>;
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u-boot,dm-pre-reloc;
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};
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scif_clk: scif {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <0>;
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};
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soc {
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compatible = "simple-bus";
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interrupt-parent = <&gic>;
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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u-boot,dm-pre-reloc;
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gic: interrupt-controller@f1010000 {
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compatible = "arm,gic-400";
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#interrupt-cells = <3>;
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#address-cells = <0>;
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interrupt-controller;
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reg = <0x0 0xf1010000 0 0x1000>,
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<0x0 0xf1020000 0 0x20000>,
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<0x0 0xf1040000 0 0x20000>,
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<0x0 0xf1060000 0 0x20000>;
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interrupts = <GIC_PPI 9
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(GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>;
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clocks = <&cpg CPG_MOD 408>;
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clock-names = "clk";
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power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
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resets = <&cpg 408>;
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};
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timer {
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compatible = "arm,armv8-timer";
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interrupts = <GIC_PPI 13
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(GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 14
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(GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 11
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(GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 10
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(GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>;
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};
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rwdt: watchdog@e6020000 {
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compatible = "renesas,r8a77995-wdt",
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"renesas,rcar-gen3-wdt";
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reg = <0 0xe6020000 0 0x0c>;
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clocks = <&cpg CPG_MOD 402>;
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power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
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resets = <&cpg 402>;
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status = "disabled";
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};
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pmu_a53 {
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compatible = "arm,cortex-a53-pmu";
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interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
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};
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cpg: clock-controller@e6150000 {
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compatible = "renesas,r8a77995-cpg-mssr";
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reg = <0 0xe6150000 0 0x1000>;
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clocks = <&extal_clk>;
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clock-names = "extal";
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#clock-cells = <2>;
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#power-domain-cells = <0>;
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#reset-cells = <1>;
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u-boot,dm-pre-reloc;
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};
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rst: reset-controller@e6160000 {
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compatible = "renesas,r8a77995-rst";
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reg = <0 0xe6160000 0 0x0200>;
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};
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pfc: pin-controller@e6060000 {
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compatible = "renesas,pfc-r8a77995";
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reg = <0 0xe6060000 0 0x508>;
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};
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prr: chipid@fff00044 {
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compatible = "renesas,prr";
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reg = <0 0xfff00044 0 4>;
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u-boot,dm-pre-reloc;
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};
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sysc: system-controller@e6180000 {
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compatible = "renesas,r8a77995-sysc";
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reg = <0 0xe6180000 0 0x0400>;
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#power-domain-cells = <1>;
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};
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intc_ex: interrupt-controller@e61c0000 {
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compatible = "renesas,intc-ex-r8a77995", "renesas,irqc";
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#interrupt-cells = <2>;
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interrupt-controller;
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reg = <0 0xe61c0000 0 0x200>;
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interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cpg CPG_MOD 407>;
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power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
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resets = <&cpg 407>;
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};
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gpio0: gpio@e6050000 {
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compatible = "renesas,gpio-r8a77995",
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"renesas,rcar-gen3-gpio",
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"renesas,gpio-rcar";
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reg = <0 0xe6050000 0 0x50>;
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interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
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#gpio-cells = <2>;
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gpio-controller;
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gpio-ranges = <&pfc 0 0 9>;
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#interrupt-cells = <2>;
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interrupt-controller;
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clocks = <&cpg CPG_MOD 912>;
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power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
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resets = <&cpg 912>;
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};
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gpio1: gpio@e6051000 {
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compatible = "renesas,gpio-r8a77995",
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"renesas,rcar-gen3-gpio",
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"renesas,gpio-rcar";
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reg = <0 0xe6051000 0 0x50>;
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interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
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#gpio-cells = <2>;
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gpio-controller;
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gpio-ranges = <&pfc 0 32 32>;
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#interrupt-cells = <2>;
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interrupt-controller;
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clocks = <&cpg CPG_MOD 911>;
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power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
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resets = <&cpg 911>;
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};
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gpio2: gpio@e6052000 {
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compatible = "renesas,gpio-r8a77995",
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"renesas,rcar-gen3-gpio",
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"renesas,gpio-rcar";
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reg = <0 0xe6052000 0 0x50>;
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interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
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#gpio-cells = <2>;
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gpio-controller;
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gpio-ranges = <&pfc 0 64 32>;
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#interrupt-cells = <2>;
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interrupt-controller;
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clocks = <&cpg CPG_MOD 910>;
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power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
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resets = <&cpg 910>;
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};
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gpio3: gpio@e6053000 {
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compatible = "renesas,gpio-r8a77995",
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"renesas,rcar-gen3-gpio",
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"renesas,gpio-rcar";
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reg = <0 0xe6053000 0 0x50>;
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interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
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#gpio-cells = <2>;
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gpio-controller;
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gpio-ranges = <&pfc 0 96 10>;
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#interrupt-cells = <2>;
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interrupt-controller;
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clocks = <&cpg CPG_MOD 909>;
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power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
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resets = <&cpg 909>;
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};
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gpio4: gpio@e6054000 {
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compatible = "renesas,gpio-r8a77995",
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"renesas,rcar-gen3-gpio",
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"renesas,gpio-rcar";
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reg = <0 0xe6054000 0 0x50>;
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interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
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#gpio-cells = <2>;
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gpio-controller;
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gpio-ranges = <&pfc 0 128 32>;
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#interrupt-cells = <2>;
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interrupt-controller;
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clocks = <&cpg CPG_MOD 908>;
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power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
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resets = <&cpg 908>;
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};
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gpio5: gpio@e6055000 {
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compatible = "renesas,gpio-r8a77995",
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"renesas,rcar-gen3-gpio",
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"renesas,gpio-rcar";
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reg = <0 0xe6055000 0 0x50>;
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interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
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#gpio-cells = <2>;
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gpio-controller;
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gpio-ranges = <&pfc 0 160 21>;
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#interrupt-cells = <2>;
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interrupt-controller;
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clocks = <&cpg CPG_MOD 907>;
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power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
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resets = <&cpg 907>;
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};
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gpio6: gpio@e6055400 {
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compatible = "renesas,gpio-r8a77995",
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"renesas,rcar-gen3-gpio",
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"renesas,gpio-rcar";
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reg = <0 0xe6055400 0 0x50>;
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interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
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#gpio-cells = <2>;
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gpio-controller;
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gpio-ranges = <&pfc 0 192 14>;
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#interrupt-cells = <2>;
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interrupt-controller;
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clocks = <&cpg CPG_MOD 906>;
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power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
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resets = <&cpg 906>;
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};
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avb: ethernet@e6800000 {
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compatible = "renesas,etheravb-r8a77995",
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"renesas,etheravb-rcar-gen3";
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reg = <0 0xe6800000 0 0x800>, <0 0xe6a00000 0 0x10000>;
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interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "ch0", "ch1", "ch2", "ch3",
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"ch4", "ch5", "ch6", "ch7",
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"ch8", "ch9", "ch10", "ch11",
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"ch12", "ch13", "ch14", "ch15",
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"ch16", "ch17", "ch18", "ch19",
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"ch20", "ch21", "ch22", "ch23",
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"ch24";
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clocks = <&cpg CPG_MOD 812>;
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power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
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resets = <&cpg 812>;
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phy-mode = "rgmii-txid";
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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scif2: serial@e6e88000 {
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compatible = "renesas,scif-r8a77995",
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"renesas,rcar-gen3-scif", "renesas,scif";
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reg = <0 0xe6e88000 0 64>;
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interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cpg CPG_MOD 310>,
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<&cpg CPG_CORE R8A77995_CLK_S3D1C>,
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<&scif_clk>;
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clock-names = "fck", "brg_int", "scif_clk";
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power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
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resets = <&cpg 310>;
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status = "disabled";
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};
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pwm0: pwm@e6e30000 {
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compatible = "renesas,pwm-r8a77995", "renesas,pwm-rcar";
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reg = <0 0xe6e30000 0 0x8>;
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#pwm-cells = <2>;
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clocks = <&cpg CPG_MOD 523>;
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power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
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resets = <&cpg 523>;
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status = "disabled";
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};
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pwm1: pwm@e6e31000 {
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compatible = "renesas,pwm-r8a77995", "renesas,pwm-rcar";
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reg = <0 0xe6e31000 0 0x8>;
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#pwm-cells = <2>;
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clocks = <&cpg CPG_MOD 523>;
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power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
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resets = <&cpg 523>;
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status = "disabled";
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};
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pwm2: pwm@e6e32000 {
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compatible = "renesas,pwm-r8a77995", "renesas,pwm-rcar";
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reg = <0 0xe6e32000 0 0x8>;
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#pwm-cells = <2>;
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clocks = <&cpg CPG_MOD 523>;
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power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
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resets = <&cpg 523>;
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status = "disabled";
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};
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pwm3: pwm@e6e33000 {
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compatible = "renesas,pwm-r8a77995", "renesas,pwm-rcar";
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reg = <0 0xe6e33000 0 0x8>;
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#pwm-cells = <2>;
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clocks = <&cpg CPG_MOD 523>;
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power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
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resets = <&cpg 523>;
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status = "disabled";
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};
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ehci0: usb@ee080100 {
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compatible = "generic-ehci";
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reg = <0 0xee080100 0 0x100>;
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interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cpg CPG_MOD 703>;
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phys = <&usb2_phy0>;
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phy-names = "usb";
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companion = <&ohci0>;
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power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
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resets = <&cpg 703>;
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status = "disabled";
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};
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ohci0: usb@ee080000 {
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compatible = "generic-ohci";
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reg = <0 0xee080000 0 0x100>;
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interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cpg CPG_MOD 703>;
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phys = <&usb2_phy0>;
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phy-names = "usb";
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power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
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resets = <&cpg 703>;
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status = "disabled";
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};
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usb2_phy0: usb-phy@ee080200 {
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compatible = "renesas,usb2-phy-r8a77995",
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"renesas,rcar-gen3-usb2-phy";
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reg = <0 0xee080200 0 0x700>;
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interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cpg CPG_MOD 703>;
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power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
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resets = <&cpg 703>;
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#phy-cells = <0>;
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status = "disabled";
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};
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};
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};
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@ -12,6 +12,9 @@ config R8A7796
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config R8A77970
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bool "Renesas SoC R8A77970"
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config R8A77995
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bool "Renesas SoC R8A77995"
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endchoice
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choice
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|
|||
|
|
@ -62,6 +62,7 @@ static const struct {
|
|||
{ RMOBILE_CPU_TYPE_R8A7795, "R8A7795" },
|
||||
{ RMOBILE_CPU_TYPE_R8A7796, "R8A7796" },
|
||||
{ RMOBILE_CPU_TYPE_R8A77970, "R8A77970" },
|
||||
{ RMOBILE_CPU_TYPE_R8A77995, "R8A77995" },
|
||||
{ 0x0, "CPU" },
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -34,6 +34,7 @@
|
|||
#define RMOBILE_CPU_TYPE_R8A7795 0x4F
|
||||
#define RMOBILE_CPU_TYPE_R8A7796 0x52
|
||||
#define RMOBILE_CPU_TYPE_R8A77970 0x54
|
||||
#define RMOBILE_CPU_TYPE_R8A77995 0x58
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
u32 rmobile_get_cpu_type(void);
|
||||
|
|
|
|||
|
|
@ -69,6 +69,26 @@ static struct mm_region r8a77970_mem_map[] = {
|
|||
}
|
||||
};
|
||||
|
||||
static struct mm_region r8a77995_mem_map[] = {
|
||||
{
|
||||
.virt = 0x0UL,
|
||||
.phys = 0x0UL,
|
||||
.size = 0xe0000000UL,
|
||||
.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
|
||||
PTE_BLOCK_INNER_SHARE
|
||||
}, {
|
||||
.virt = 0xe0000000UL,
|
||||
.phys = 0xe0000000UL,
|
||||
.size = 0xe0000000UL,
|
||||
.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
|
||||
PTE_BLOCK_NON_SHARE |
|
||||
PTE_BLOCK_PXN | PTE_BLOCK_UXN
|
||||
}, {
|
||||
/* List terminator */
|
||||
0,
|
||||
}
|
||||
};
|
||||
|
||||
struct mm_region *mem_map = r8a7795_mem_map;
|
||||
|
||||
void rcar_gen3_memmap_fixup(void)
|
||||
|
|
@ -85,5 +105,8 @@ void rcar_gen3_memmap_fixup(void)
|
|||
case RMOBILE_CPU_TYPE_R8A77970:
|
||||
mem_map = r8a77970_mem_map;
|
||||
break;
|
||||
case RMOBILE_CPU_TYPE_R8A77995:
|
||||
mem_map = r8a77995_mem_map;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
|
|
|||
|
|
@ -0,0 +1,57 @@
|
|||
/*
|
||||
* Copyright (C) 2017 Glider bvba
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*/
|
||||
#ifndef __DT_BINDINGS_CLOCK_R8A77995_CPG_MSSR_H__
|
||||
#define __DT_BINDINGS_CLOCK_R8A77995_CPG_MSSR_H__
|
||||
|
||||
#include <dt-bindings/clock/renesas-cpg-mssr.h>
|
||||
|
||||
/* r8a77995 CPG Core Clocks */
|
||||
#define R8A77995_CLK_Z2 0
|
||||
#define R8A77995_CLK_ZG 1
|
||||
#define R8A77995_CLK_ZTR 2
|
||||
#define R8A77995_CLK_ZT 3
|
||||
#define R8A77995_CLK_ZX 4
|
||||
#define R8A77995_CLK_S0D1 5
|
||||
#define R8A77995_CLK_S1D1 6
|
||||
#define R8A77995_CLK_S1D2 7
|
||||
#define R8A77995_CLK_S1D4 8
|
||||
#define R8A77995_CLK_S2D1 9
|
||||
#define R8A77995_CLK_S2D2 10
|
||||
#define R8A77995_CLK_S2D4 11
|
||||
#define R8A77995_CLK_S3D1 12
|
||||
#define R8A77995_CLK_S3D2 13
|
||||
#define R8A77995_CLK_S3D4 14
|
||||
#define R8A77995_CLK_S1D4C 15
|
||||
#define R8A77995_CLK_S3D1C 16
|
||||
#define R8A77995_CLK_S3D2C 17
|
||||
#define R8A77995_CLK_S3D4C 18
|
||||
#define R8A77995_CLK_LB 19
|
||||
#define R8A77995_CLK_CL 20
|
||||
#define R8A77995_CLK_ZB3 21
|
||||
#define R8A77995_CLK_ZB3D2 22
|
||||
#define R8A77995_CLK_CR 23
|
||||
#define R8A77995_CLK_CRD2 24
|
||||
#define R8A77995_CLK_SD0H 25
|
||||
#define R8A77995_CLK_SD0 26
|
||||
#define R8A77995_CLK_SSP2 27
|
||||
#define R8A77995_CLK_SSP1 28
|
||||
#define R8A77995_CLK_RPC 29
|
||||
#define R8A77995_CLK_RPCD2 30
|
||||
#define R8A77995_CLK_ZA2 31
|
||||
#define R8A77995_CLK_ZA8 32
|
||||
#define R8A77995_CLK_Z2D 33
|
||||
#define R8A77995_CLK_CANFD 34
|
||||
#define R8A77995_CLK_MSO 35
|
||||
#define R8A77995_CLK_R 36
|
||||
#define R8A77995_CLK_OSC 37
|
||||
#define R8A77995_CLK_LV0 38
|
||||
#define R8A77995_CLK_LV1 39
|
||||
#define R8A77995_CLK_CP 40
|
||||
|
||||
#endif /* __DT_BINDINGS_CLOCK_R8A77995_CPG_MSSR_H__ */
|
||||
|
|
@ -0,0 +1,23 @@
|
|||
/*
|
||||
* Copyright (C) 2017 Glider bvba
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*/
|
||||
#ifndef __DT_BINDINGS_POWER_R8A77995_SYSC_H__
|
||||
#define __DT_BINDINGS_POWER_R8A77995_SYSC_H__
|
||||
|
||||
/*
|
||||
* These power domain indices match the numbers of the interrupt bits
|
||||
* representing the power areas in the various Interrupt Registers
|
||||
* (e.g. SYSCISR, Interrupt Status Register)
|
||||
*/
|
||||
|
||||
#define R8A77995_PD_CA53_CPU0 5
|
||||
#define R8A77995_PD_CA53_SCU 21
|
||||
|
||||
/* Always-on power area */
|
||||
#define R8A77995_PD_ALWAYS_ON 32
|
||||
|
||||
#endif /* __DT_BINDINGS_POWER_R8A77995_SYSC_H__ */
|
||||
Loading…
Reference in New Issue