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https://github.com/brain-hackers/u-boot-brain
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serial: sh: Drop assorted SH3, SH4, SH5 macros
Drop unused macros from the header to clean it up. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Chris Brandt <chris.brandt@renesas.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> Cc: Vladimir Zapolskiy <vz@mleia.com> Cc: Yoshihiro Shimoda <shimoda.yoshihiro.uh@renesas.com>
This commit is contained in:
Marek Vasut
Marek Vasut
parent
2a219297c5
commit
10e91cfdb0
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@ -19,9 +19,7 @@
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DECLARE_GLOBAL_DATA_PTR;
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#if defined(CONFIG_CPU_SH7760) || \
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defined(CONFIG_CPU_SH7780) || \
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defined(CONFIG_CPU_SH7786)
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#if defined(CONFIG_CPU_SH7780)
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static int scif_rxfill(struct uart_port *port)
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{
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return sci_in(port, SCRFDR) & 0xff;
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@ -38,14 +36,6 @@ static int scif_rxfill(struct uart_port *port)
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return sci_in(port, SCFDR) & SCIF2_RFDC_MASK;
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}
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}
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#elif defined(CONFIG_ARCH_SH7372)
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static int scif_rxfill(struct uart_port *port)
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{
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if (port->type == PORT_SCIFA)
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return sci_in(port, SCFDR) & SCIF_RFDC_MASK;
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else
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return sci_in(port, SCRFDR);
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}
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#else
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static int scif_rxfill(struct uart_port *port)
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{
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@ -34,9 +34,6 @@ struct uart_port {
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# define SCSCR_INIT(port) (port->mapbase == SCIF2) ? 0xF3 : 0xF0
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#elif defined(CONFIG_CPU_SH7720) || \
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defined(CONFIG_CPU_SH7721) || \
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defined(CONFIG_ARCH_SH7367) || \
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defined(CONFIG_ARCH_SH7377) || \
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defined(CONFIG_ARCH_SH7372) || \
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defined(CONFIG_SH73A0) || \
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defined(CONFIG_R8A7740)
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# define SCSCR_INIT(port) 0x0030 /* TIE=0,RIE=0,TE=1,RE=1 */
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@ -46,7 +43,6 @@ struct uart_port {
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#elif defined(CONFIG_CPU_SH7750) || \
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defined(CONFIG_CPU_SH7750R) || \
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defined(CONFIG_CPU_SH7750S) || \
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defined(CONFIG_CPU_SH7091) || \
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defined(CONFIG_CPU_SH7751) || \
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defined(CONFIG_CPU_SH7751R)
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# define SCSPTR1 0xffe0001c /* 8 bit SCI */
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@ -55,24 +51,12 @@ struct uart_port {
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# define SCSCR_INIT(port) (((port)->type == PORT_SCI) ? \
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0x30 /* TIE=0,RIE=0,TE=1,RE=1 */ : \
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0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */)
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#elif defined(CONFIG_CPU_SH7760)
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# define SCSPTR0 0xfe600024 /* 16 bit SCIF */
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# define SCSPTR1 0xfe610024 /* 16 bit SCIF */
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# define SCSPTR2 0xfe620024 /* 16 bit SCIF */
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# define SCIF_ORER 0x0001 /* overrun error bit */
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# define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
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#elif defined(CONFIG_CPU_SH7710) || defined(CONFIG_CPU_SH7712)
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# define SCSPTR0 0xA4400000 /* 16 bit SCIF */
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# define SCIF_ORER 0x0001 /* overrun error bit */
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# define PACR 0xa4050100
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# define PBCR 0xa4050102
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# define SCSCR_INIT(port) 0x3B
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#elif defined(CONFIG_CPU_SH7343)
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# define SCSPTR0 0xffe00010 /* 16 bit SCIF */
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# define SCSPTR1 0xffe10010 /* 16 bit SCIF */
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# define SCSPTR2 0xffe20010 /* 16 bit SCIF */
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# define SCSPTR3 0xffe30010 /* 16 bit SCIF */
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# define SCSCR_INIT(port) 0x32 /* TIE=0,RIE=0,TE=1,RE=1,REIE=0,CKE=1 */
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#elif defined(CONFIG_CPU_SH7722)
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# define PADR 0xA4050120
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# undef PSDR
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@ -81,11 +65,6 @@ struct uart_port {
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# define PSCR 0xA405011E
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# define SCIF_ORER 0x0001 /* overrun error bit */
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# define SCSCR_INIT(port) 0x0038 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
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#elif defined(CONFIG_CPU_SH7366)
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# define SCPDR0 0xA405013E /* 16 bit SCIF0 PSDR */
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# define SCSPTR0 SCPDR0
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# define SCIF_ORER 0x0001 /* overrun error bit */
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# define SCSCR_INIT(port) 0x0038 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
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#elif defined(CONFIG_CPU_SH7723)
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# define SCSPTR0 0xa4050160
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# define SCSPTR1 0xa405013e
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@ -104,20 +83,6 @@ struct uart_port {
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# define SCSPTR5 0xFFE45020
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# define SCIF_ORER 0x0001 /* overrun error bit */
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# define SCSCR_INIT(port) 0x0038 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
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#elif defined(CONFIG_CPU_SH4_202)
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# define SCSPTR2 0xffe80020 /* 16 bit SCIF */
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# define SCIF_ORER 0x0001 /* overrun error bit */
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# define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
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#elif defined(CONFIG_CPU_SH5_101) || defined(CONFIG_CPU_SH5_103)
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# define SCIF_BASE_ADDR 0x01030000
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# define SCIF_ADDR_SH5 (PHYS_PERIPHERAL_BLOCK+SCIF_BASE_ADDR)
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# define SCIF_PTR2_OFFS 0x0000020
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# define SCIF_LSR2_OFFS 0x0000024
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# define SCSPTR\
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((port->mapbase)+SCIF_PTR2_OFFS) /* 16 bit SCIF */
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# define SCLSR2\
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((port->mapbase)+SCIF_LSR2_OFFS) /* 16 bit SCIF */
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# define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0, TE=1,RE=1,REIE=1 */
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#elif defined(CONFIG_CPU_SH7757) || \
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defined(CONFIG_CPU_SH7752) || \
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defined(CONFIG_CPU_SH7753)
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@ -133,12 +98,6 @@ struct uart_port {
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# define SCSPTR2 0xffe10020 /* 16 bit SCIF/IRDA */
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# define SCIF_ORER 0x0001 /* overrun error bit */
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# define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
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#elif defined(CONFIG_CPU_SH7770)
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# define SCSPTR0 0xff923020 /* 16 bit SCIF */
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# define SCSPTR1 0xff924020 /* 16 bit SCIF */
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# define SCSPTR2 0xff925020 /* 16 bit SCIF */
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# define SCIF_ORER 0x0001 /* overrun error bit */
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# define SCSCR_INIT(port) 0x3c /* TIE=0,RIE=0,TE=1,RE=1,REIE=1,cke=2 */
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#elif defined(CONFIG_CPU_SH7780)
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# define SCSPTR0 0xffe00024 /* 16 bit SCIF */
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# define SCSPTR1 0xffe10024 /* 16 bit SCIF */
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@ -147,30 +106,12 @@ struct uart_port {
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/* TIE=0,RIE=0,TE=1,RE=1,REIE=1,CKE1=1 */
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# define SCSCR_INIT(port) 0x3a
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#elif defined(CONFIG_CPU_SH7786)
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# define SCSPTR0 0xffea0024 /* 16 bit SCIF */
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# define SCSPTR1 0xffeb0024 /* 16 bit SCIF */
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# define SCSPTR2 0xffec0024 /* 16 bit SCIF */
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# define SCSPTR3 0xffed0024 /* 16 bit SCIF */
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# define SCSPTR4 0xffee0024 /* 16 bit SCIF */
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# define SCSPTR5 0xffef0024 /* 16 bit SCIF */
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# define SCIF_ORER 0x0001 /* Overrun error bit */
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# define SCSCR_INIT(port) 0x3a /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
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#elif defined(CONFIG_CPU_SH7201) || \
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defined(CONFIG_CPU_SH7203) || \
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defined(CONFIG_CPU_SH7206) || \
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defined(CONFIG_CPU_SH7263) || \
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#elif defined(CONFIG_CPU_SH7203) || \
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defined(CONFIG_CPU_SH7264)
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# define SCSPTR0 0xfffe8020 /* 16 bit SCIF */
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# define SCSPTR1 0xfffe8820 /* 16 bit SCIF */
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# define SCSPTR2 0xfffe9020 /* 16 bit SCIF */
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# define SCSPTR3 0xfffe9820 /* 16 bit SCIF */
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# if defined(CONFIG_CPU_SH7201)
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# define SCSPTR4 0xfffeA020 /* 16 bit SCIF */
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# define SCSPTR5 0xfffeA820 /* 16 bit SCIF */
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# define SCSPTR6 0xfffeB020 /* 16 bit SCIF */
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# define SCSPTR7 0xfffeB820 /* 16 bit SCIF */
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# endif
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# define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
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#elif defined(CONFIG_CPU_SH7269) || defined(CONFIG_RZA1)
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# define SCSPTR0 0xe8007020 /* 16 bit SCIF */
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@ -183,19 +124,6 @@ struct uart_port {
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# define SCSPTR7 0xe800a820 /* 16 bit SCIF */
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# define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
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# define SCIF_ORER 0x0001 /* overrun error bit */
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#elif defined(CONFIG_CPU_SH7619)
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# define SCSPTR0 0xf8400020 /* 16 bit SCIF */
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# define SCSPTR1 0xf8410020 /* 16 bit SCIF */
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# define SCSPTR2 0xf8420020 /* 16 bit SCIF */
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# define SCIF_ORER 0x0001 /* overrun error bit */
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# define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
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#elif defined(CONFIG_CPU_SHX3)
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# define SCSPTR0 0xffc30020 /* 16 bit SCIF */
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# define SCSPTR1 0xffc40020 /* 16 bit SCIF */
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# define SCSPTR2 0xffc50020 /* 16 bit SCIF */
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# define SCSPTR3 0xffc60020 /* 16 bit SCIF */
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# define SCIF_ORER 0x0001 /* Overrun error bit */
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# define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
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#elif defined(CONFIG_RCAR_GEN2) || defined(CONFIG_RCAR_GEN3) || \
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defined(CONFIG_R7S72100)
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# if defined(CONFIG_SCIF_A)
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@ -215,7 +143,6 @@ struct uart_port {
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#define SCI_CTRL_FLAGS_TE 0x20 /* all */
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#define SCI_CTRL_FLAGS_RE 0x10 /* all */
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#if defined(CONFIG_CPU_SH7750) || \
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defined(CONFIG_CPU_SH7091) || \
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defined(CONFIG_CPU_SH7750R) || \
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defined(CONFIG_CPU_SH7722) || \
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defined(CONFIG_CPU_SH7734) || \
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@ -223,9 +150,7 @@ struct uart_port {
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defined(CONFIG_CPU_SH7751) || \
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defined(CONFIG_CPU_SH7751R) || \
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defined(CONFIG_CPU_SH7763) || \
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defined(CONFIG_CPU_SH7780) || \
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defined(CONFIG_CPU_SH7786) || \
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defined(CONFIG_CPU_SHX3)
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defined(CONFIG_CPU_SH7780)
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#define SCI_CTRL_FLAGS_REIE 0x08 /* 7750 SCIF */
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#else
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#define SCI_CTRL_FLAGS_REIE 0
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@ -260,9 +185,6 @@ struct uart_port {
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#if defined(CONFIG_CPU_SH7705) || \
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defined(CONFIG_CPU_SH7720) || \
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defined(CONFIG_CPU_SH7721) || \
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defined(CONFIG_ARCH_SH7367) || \
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defined(CONFIG_ARCH_SH7377) || \
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defined(CONFIG_ARCH_SH7372) || \
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defined(CONFIG_SH73A0) || \
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defined(CONFIG_R8A7740)
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# define SCIF_ORER 0x0200
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@ -313,9 +235,6 @@ struct uart_port {
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#if defined(CONFIG_CPU_SH7705) || \
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defined(CONFIG_CPU_SH7720) || \
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defined(CONFIG_CPU_SH7721) || \
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defined(CONFIG_ARCH_SH7367) || \
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defined(CONFIG_ARCH_SH7377) || \
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defined(CONFIG_ARCH_SH7372) || \
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defined(CONFIG_SH73A0) || \
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defined(CONFIG_R8A7740)
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# define SCxSR_RDxF_CLEAR(port) (sci_in(port, SCxSR) & 0xfffc)
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@ -398,9 +317,6 @@ static inline void sci_##name##_out(struct uart_port *port,\
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}
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#if defined(CONFIG_CPU_SH3) || \
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defined(CONFIG_ARCH_SH7367) || \
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defined(CONFIG_ARCH_SH7377) || \
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defined(CONFIG_ARCH_SH7372) || \
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defined(CONFIG_SH73A0) || \
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defined(CONFIG_R8A7740)
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#if defined(CONFIG_CPU_SH7710) || defined(CONFIG_CPU_SH7712)
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@ -417,13 +333,10 @@ static inline void sci_##name##_out(struct uart_port *port,\
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#elif defined(CONFIG_CPU_SH7705) || \
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defined(CONFIG_CPU_SH7720) || \
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defined(CONFIG_CPU_SH7721) || \
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defined(CONFIG_ARCH_SH7367) || \
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defined(CONFIG_ARCH_SH7377) || \
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defined(CONFIG_SH73A0)
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#define SCIF_FNS(name, scif_offset, scif_size) \
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CPU_SCIF_FNS(name, scif_offset, scif_size)
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#elif defined(CONFIG_ARCH_SH7372) || \
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defined(CONFIG_R8A7740)
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#elif defined(CONFIG_R8A7740)
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#define SCIx_FNS(name, sh4_scifa_offset, sh4_scifa_size,\
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sh4_scifb_offset, sh4_scifb_size) \
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CPU_SCIx_FNS(name, sh4_scifa_offset, sh4_scifa_size,\
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@ -465,8 +378,6 @@ static inline void sci_##name##_out(struct uart_port *port,\
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#if defined(CONFIG_CPU_SH7705) || \
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defined(CONFIG_CPU_SH7720) || \
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defined(CONFIG_CPU_SH7721) || \
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defined(CONFIG_ARCH_SH7367) || \
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defined(CONFIG_ARCH_SH7377) || \
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defined(CONFIG_SH73A0)
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SCIF_FNS(SCSMR, 0x00, 16)
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@ -481,8 +392,7 @@ SCIF_FNS(SCxTDR, 0x20, 8)
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SCIF_FNS(SCxRDR, 0x24, 8)
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SCIF_FNS(SCLSR, 0x00, 0)
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SCIF_FNS(DL, 0x00, 0) /* dummy */
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#elif defined(CONFIG_ARCH_SH7372) || \
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defined(CONFIG_R8A7740)
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#elif defined(CONFIG_R8A7740)
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SCIF_FNS(SCSMR, 0x00, 16)
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SCIF_FNS(SCBRR, 0x04, 8)
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SCIF_FNS(SCSCR, 0x08, 16)
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@ -539,9 +449,7 @@ SCIx_FNS(SCxTDR, 0x06, 8, 0x0c, 8, 0x06, 8, 0x0C, 8, 0x03, 8)
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SCIx_FNS(SCxSR, 0x08, 8, 0x10, 8, 0x08, 16, 0x10, 16, 0x04, 8)
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SCIx_FNS(SCxRDR, 0x0a, 8, 0x14, 8, 0x0A, 8, 0x14, 8, 0x05, 8)
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SCIF_FNS(SCFCR, 0x0c, 8, 0x18, 16)
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#if defined(CONFIG_CPU_SH7760) || \
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defined(CONFIG_CPU_SH7780) || \
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defined(CONFIG_CPU_SH7786)
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#if defined(CONFIG_CPU_SH7780)
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SCIF_FNS(SCFDR, 0x0e, 16, 0x1C, 16)
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SCIF_FNS(SCTFDR, 0x0e, 16, 0x1C, 16)
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SCIF_FNS(SCRFDR, 0x0e, 16, 0x20, 16)
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@ -584,8 +492,7 @@ static inline int sci_rxd_in(struct uart_port *port)
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defined(CONFIG_CPU_SH7751) || \
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defined(CONFIG_CPU_SH7751R) || \
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defined(CONFIG_CPU_SH7750R) || \
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defined(CONFIG_CPU_SH7750S) || \
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defined(CONFIG_CPU_SH7091)
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defined(CONFIG_CPU_SH7750S)
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static inline int sci_rxd_in(struct uart_port *port)
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{
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if (port->mapbase == 0xffe00000)
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@ -631,15 +538,11 @@ static inline int sci_rxd_in(struct uart_port *port)
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* -- Mitch Davis - 15 Jul 2000
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*/
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#if defined(CONFIG_CPU_SH7780) || \
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defined(CONFIG_CPU_SH7786)
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#if defined(CONFIG_CPU_SH7780)
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#define SCBRR_VALUE(bps, clk) ((clk+16*bps)/(16*bps)-1)
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#elif defined(CONFIG_CPU_SH7705) || \
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defined(CONFIG_CPU_SH7720) || \
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defined(CONFIG_CPU_SH7721) || \
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defined(CONFIG_ARCH_SH7367) || \
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defined(CONFIG_ARCH_SH7377) || \
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defined(CONFIG_ARCH_SH7372) || \
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defined(CONFIG_SH73A0) || \
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defined(CONFIG_R8A7740)
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#define SCBRR_VALUE(bps, clk) (((clk*2)+16*bps)/(32*bps)-1)
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