From 10bc132510fc1433c6bfc6c626c388bde0981d42 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Pali=20Roh=C3=A1r?= Date: Sun, 7 Feb 2021 14:50:05 +0100 Subject: [PATCH] usb: musb: Fix configuring FIFO for endpoints MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This patch fixes configuring FIFOs for one-directional endpoints which have only one queue (either RX or TX, but noth both). Size of FIFO buffer is 2^(idx+3) bytes and starting address is 2^(addr+3). Moreover first 64 bytes are reserved for EP0. Without this patch if FIFO size specified by caller was zero then idx was incorrectly calculated (expr. ffs(0)-1) and size overflowed in fifosz register. This register uses has only 4 bits for FIFO size. Moreover specifying zero buffer size is not possible (with idx=0 is minimal buffer size 8 bytes). So even for one-directional endpoints we need to correctly specify both (RX and TX) FIFO buffer sizes and its addresses. This patch is fixing calculation of start address and buffer size to minimal value and ensures that it would not overlap with buffer reserved for EP0. This issue caused loose of packets on USB bus in both directions and basically usbtty was unusable. Signed-off-by: Pali Rohár Reviewed-by: Lukasz Majewski Acked-by: Pavel Machek --- drivers/usb/musb/musb_core.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/usb/musb/musb_core.c b/drivers/usb/musb/musb_core.c index cc6dc3839d..9651f074a4 100644 --- a/drivers/usb/musb/musb_core.c +++ b/drivers/usb/musb/musb_core.c @@ -50,7 +50,7 @@ void musb_start(void) # define config_fifo(dir, idx, addr) \ do { \ writeb(idx, &musbr->dir##fifosz); \ - writew(fifoaddr >> 3, &musbr->dir##fifoadd); \ + writew(addr, &musbr->dir##fifoadd); \ } while (0) #endif @@ -66,14 +66,14 @@ void musb_start(void) void musb_configure_ep(const struct musb_epinfo *epinfo, u8 cnt) { u16 csr; - u16 fifoaddr = 64; /* First 64 bytes of FIFO reserved for EP0 */ + u16 fifoaddr = 64 >> 3; /* First 64 bytes of FIFO reserved for EP0 */ u32 fifosize; u8 idx; while (cnt--) { /* prepare fifosize to write to register */ fifosize = epinfo->epsize >> 3; - idx = ffs(fifosize) - 1; + idx = fifosize ? ((ffs(fifosize) - 1) & 0xF) : 0; writeb(epinfo->epnum, &musbr->index); if (epinfo->epdir) { @@ -99,7 +99,7 @@ void musb_configure_ep(const struct musb_epinfo *epinfo, u8 cnt) writew(csr | MUSB_RXCSR_FLUSHFIFO, &musbr->rxcsr); } - fifoaddr += epinfo->epsize; + fifoaddr += 1 << idx; epinfo++; } }