brain-hackers_pepepper-mirror/u-boot-brain
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Merge branch 'master' of /home/stefan/git/u-boot/u-boot

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This commit is contained in:
Stefan Roese 2008-06-03 20:19:08 +02:00
commit 10a3367955
1048 changed files with 15027 additions and 13466 deletions
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1
MAKEALL
View File

@ -355,6 +355,7 @@ LIST_85xx=" \
sbc8540 \
sbc8548 \
sbc8560 \
socrates \
stxgp3 \
stxssa \
TQM8540 \

3
Makefile
View File

@ -2211,6 +2211,9 @@ sbc8560_66_config: unconfig
fi
@$(MKCONFIG) -a sbc8560 ppc mpc85xx sbc8560
socrates_config: unconfig
@$(MKCONFIG) $(@:_config=) ppc mpc85xx socrates
stxgp3_config: unconfig
@$(MKCONFIG) $(@:_config=) ppc mpc85xx stxgp3

2
board/MAI/AmigaOneG3SE/AmigaOneG3SE.c
View File

@ -71,7 +71,7 @@ __asm__(" .globl send_kb \n "
" li r3, 0x01 \n "
" bl send_kb \n "
" mtlr r10 \n "
" blr "
" blr \n "
);

167
board/MAI/AmigaOneG3SE/enet.c
View File

@ -379,14 +379,12 @@ static int auto_negotiate(struct eth_device* dev)
EL3WINDOW (dev, 1);
/* Wait for Auto negotiation to complete */
for (i = 0; i <= 1000; i++)
{
for (i = 0; i <= 1000; i++) {
if (ETH_INW (dev, 2) & 0x04)
break;
udelay (100);
if (i == 1000)
{
if (i == 1000) {
PRINTF ("Error: Auto negotiation failed\n");
return 0;
}
@ -405,20 +403,17 @@ void eth_interrupt(struct eth_device *dev)
if (!(status & IntLatch))
return;
if (status & (1<<6))
{
if (status & (1 << 6)) {
ETH_CMD (dev, AckIntr | (1 << 6));
printf ("Acknowledged Interrupt command\n");
}
if (status & DownComplete)
{
if (status & DownComplete) {
ETH_CMD (dev, AckIntr | DownComplete);
printf ("Acknowledged DownComplete\n");
}
if (status & UpComplete)
{
if (status & UpComplete) {
ETH_CMD (dev, AckIntr | UpComplete);
printf ("Acknowledged UpComplete\n");
}
@ -439,16 +434,18 @@ int eth_3com_initialize(bd_t *bis)
/* Find ethernet controller on the PCI bus */
if ((devno = pci_find_device(PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3C905C, 0)) < 0)
{
if ((devno =
pci_find_device (PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3C905C,
0)) < 0) {
PRINTF ("Error: Cannot find the ethernet device on the PCI bus\n");
goto Done;
}
if (s)
{
if (s) {
unsigned long base = atoi (s);
pci_write_config_dword(devno, PCI_BASE_ADDRESS_0, base | 0x01);
pci_write_config_dword (devno, PCI_BASE_ADDRESS_0,
base | 0x01);
}
ret = pci_read_config_dword (devno, PCI_BASE_ADDRESS_0, &eth_iobase);
@ -456,26 +453,25 @@ int eth_3com_initialize(bd_t *bis)
PRINTF ("eth: 3Com Found at Address: 0x%x\n", eth_iobase);
pci_write_config_dword(devno, PCI_COMMAND, PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
pci_write_config_dword (devno, PCI_COMMAND,
PCI_COMMAND_IO | PCI_COMMAND_MEMORY |
PCI_COMMAND_MASTER);
/* Check if I/O accesses and Bus Mastering are enabled */
ret = pci_read_config_dword (devno, PCI_COMMAND, &status);
if (!(status & PCI_COMMAND_IO))
{
if (!(status & PCI_COMMAND_IO)) {
printf ("Error: Cannot enable IO access.\n");
goto Done;
}
if (!(status & PCI_COMMAND_MEMORY))
{
if (!(status & PCI_COMMAND_MEMORY)) {
printf ("Error: Cannot enable MEMORY access.\n");
goto Done;
}
if (!(status & PCI_COMMAND_MASTER))
{
if (!(status & PCI_COMMAND_MASTER)) {
printf ("Error: Cannot enable Bus Mastering.\n");
goto Done;
}
@ -505,35 +501,31 @@ int eth_3com_initialize(bd_t *bis)
/* Set the latency timer for value */
s = getenv ("3com_latency");
if (s)
{
ret = pci_write_config_byte(devno, PCI_LATENCY_TIMER, (unsigned char)atoi(s));
}
else ret = pci_write_config_byte(devno, PCI_LATENCY_TIMER, 0x0a);
if (s) {
ret = pci_write_config_byte (devno, PCI_LATENCY_TIMER,
(unsigned char) atoi (s));
} else
ret = pci_write_config_byte (devno, PCI_LATENCY_TIMER, 0x0a);
read_hw_addr (dev, bis); /* get the MAC address from Window 2 */
/* Reset the ethernet controller */
PRINTF ("Issuing reset command....\n");
if (!issue_and_wait(dev, TotalReset))
{
if (!issue_and_wait (dev, TotalReset)) {
printf ("Error: Cannot reset ethernet controller.\n");
goto Done;
}
else
} else
PRINTF ("Ethernet controller reset.\n");
/* allocate memory for rx and tx rings */
if(!(rx_ring = memalign(sizeof(struct rx_desc_3com) * NUM_RX_DESC, 16)))
{
if (!(rx_ring = memalign (sizeof (struct rx_desc_3com) * NUM_RX_DESC, 16))) {
PRINTF ("Cannot allocate memory for RX_RING.....\n");
goto Done;
}
if (!(tx_ring = memalign(sizeof(struct tx_desc_3com) * NUM_TX_DESC, 16)))
{
if (!(tx_ring = memalign (sizeof (struct tx_desc_3com) * NUM_TX_DESC, 16))) {
PRINTF ("Cannot allocate memory for TX_RING.....\n");
goto Done;
}
@ -553,8 +545,7 @@ static int eth_3com_init(struct eth_device* dev, bd_t *bis)
/* Determine what type of network the machine is connected to */
/* presently drops the connect to 10Mbps */
if (!auto_negotiate(dev))
{
if (!auto_negotiate (dev)) {
printf ("Error: Cannot determine network media.\n");
goto Done;
}
@ -576,7 +567,9 @@ static int eth_3com_init(struct eth_device* dev, bd_t *bis)
/* Below sets which indication bits to be seen. */
status_enable = SetStatusEnb | HostError | DownComplete | UpComplete | (1<<6);
status_enable =
SetStatusEnb | HostError | DownComplete | UpComplete | (1 <<
6);
ETH_CMD (dev, status_enable);
/* Below sets no bits are to cause an interrupt since this is just polling */
@ -615,24 +608,21 @@ static int eth_3com_init(struct eth_device* dev, bd_t *bis)
issue_and_wait (dev, DownStall); /* Stall and set the DownListPtr. */
ETH_OUTL (dev, (u32) & tx_ring[tx_cur], DownListPtr);
issue_and_wait (dev, DownUnstall);
for (i=0; !(ETH_STATUS(dev) & DownComplete); i++)
{
if (i >= TOUT_LOOP)
{
PRINTF("TX Ring status (Init): 0x%4x\n", le32_to_cpu(tx_ring[tx_cur].status));
for (i = 0; !(ETH_STATUS (dev) & DownComplete); i++) {
if (i >= TOUT_LOOP) {
PRINTF ("TX Ring status (Init): 0x%4x\n",
le32_to_cpu (tx_ring[tx_cur].status));
PRINTF ("ETH_STATUS: 0x%x\n", ETH_STATUS (dev));
goto Done;
}
}
if (ETH_STATUS(dev) & DownComplete) /* If DownLoad Complete ACK the bit */
{
if (ETH_STATUS (dev) & DownComplete) { /* If DownLoad Complete ACK the bit */
ETH_CMD (dev, AckIntr | DownComplete); /* acknowledge the indication bit */
issue_and_wait (dev, DownStall); /* stall and clear DownListPtr */
ETH_OUTL (dev, 0, DownListPtr);
issue_and_wait (dev, DownUnstall);
}
status = 1;
Done:
return status;
}
@ -642,8 +632,7 @@ int eth_3com_send(struct eth_device* dev, volatile void *packet, int length)
int i, status = 0;
int tx_cur;
if (length <= 0)
{
if (length <= 0) {
PRINTF ("eth: bad packet size: %d\n", length);
goto Done;
}
@ -662,16 +651,14 @@ int eth_3com_send(struct eth_device* dev, volatile void *packet, int length)
ETH_OUTL (dev, (u32) & tx_ring[tx_cur], DownListPtr);
issue_and_wait (dev, DownUnstall);
for (i=0; !(ETH_STATUS(dev) & DownComplete); i++)
{
if (i >= TOUT_LOOP)
{
PRINTF("TX Ring status (send): 0x%4x\n", le32_to_cpu(tx_ring[tx_cur].status));
for (i = 0; !(ETH_STATUS (dev) & DownComplete); i++) {
if (i >= TOUT_LOOP) {
PRINTF ("TX Ring status (send): 0x%4x\n",
le32_to_cpu (tx_ring[tx_cur].status));
goto Done;
}
}
if (ETH_STATUS(dev) & DownComplete) /* If DownLoad Complete ACK the bit */
{
if (ETH_STATUS (dev) & DownComplete) { /* If DownLoad Complete ACK the bit */
ETH_CMD (dev, AckIntr | DownComplete); /* acknowledge the indication bit */
issue_and_wait (dev, DownStall); /* stall and clear DownListPtr */
ETH_OUTL (dev, 0, DownListPtr);
@ -689,8 +676,7 @@ uchar *ptr;
printf ("Printing packet of length %x.\n\n", length);
ptr = packet;
for (loop = 1; loop <= length; loop++)
{
for (loop = 1; loop <= length; loop++) {
printf ("%2x ", *ptr++);
if ((loop % 40) == 0)
printf ("\n");
@ -708,26 +694,23 @@ int eth_3com_recv(struct eth_device* dev)
status = le32_to_cpu (rx_ring[rx_next].status); /* packet status */
while (status & (1<<15))
{
while (status & (1 << 15)) {
/* A packet has been received */
if (status & (1<<15))
{
if (status & (1 << 15)) {
/* A valid frame received */
length = le32_to_cpu (rx_ring[rx_next].status) & 0x1fff; /* length is in bits 0 - 12 */
/* Pass the packet up to the protocol layers */
NetReceive((uchar *)le32_to_cpu(rx_ring[rx_next].addr), length);
NetReceive ((uchar *)
le32_to_cpu (rx_ring[rx_next].addr),
length);
rx_ring[rx_next].status = 0; /* clear the status word */
ETH_CMD (dev, AckIntr | UpComplete);
issue_and_wait (dev, UpUnstall);
}
else
if (stat & HostError)
{
} else if (stat & HostError) {
/* There was an error */
printf ("Rx error status: 0x%4x\n", stat);
@ -740,15 +723,13 @@ int eth_3com_recv(struct eth_device* dev)
stat = ETH_STATUS (dev); /* register status */
status = le32_to_cpu (rx_ring[rx_next].status); /* packet status */
}
Done:
return length;
}
void eth_3com_halt (struct eth_device *dev)
{
if (!(dev->iobase))
{
if (!(dev->iobase)) {
goto Done;
}
@ -771,9 +752,10 @@ static void init_rx_ring(struct eth_device* dev)
PRINTF ("Initializing rx_ring. rx_buffer = %p\n", rx_buffer);
issue_and_wait (dev, UpStall);
for (i = 0; i < NUM_RX_DESC; i++)
{
rx_ring[i].next = cpu_to_le32(((u32) &rx_ring[(i+1) % NUM_RX_DESC]));
for (i = 0; i < NUM_RX_DESC; i++) {
rx_ring[i].next =
cpu_to_le32 (((u32) &
rx_ring[(i + 1) % NUM_RX_DESC]));
rx_ring[i].status = 0;
rx_ring[i].addr = cpu_to_le32 (((u32) & rx_buffer[i][0]));
rx_ring[i].length = cpu_to_le32 (PKTSIZE_ALIGN | LAST_FRAG);
@ -789,8 +771,7 @@ static void purge_tx_ring(struct eth_device* dev)
tx_next = 0;
for (i = 0; i < NUM_TX_DESC; i++)
{
for (i = 0; i < NUM_TX_DESC; i++) {
tx_ring[i].next = 0;
tx_ring[i].status = 0;
tx_ring[i].addr = 0;
@ -808,12 +789,10 @@ static void read_hw_addr(struct eth_device* dev, bd_t *bis)
/* Read the station address from the EEPROM. */
EL3WINDOW (dev, 0);
for (i = 0; i < 0x40; i++)
{
for (i = 0; i < 0x40; i++) {
ETH_OUTW (dev, EEPROM_Read + i, Wn0EepromCmd);
/* Pause for at least 162 us. for the read to take place. */
for (timer = 10; timer >= 0; timer--)
{
for (timer = 10; timer >= 0; timer--) {
udelay (162);
if ((ETH_INW (dev, Wn0EepromCmd) & 0x8000) == 0)
break;
@ -828,10 +807,10 @@ static void read_hw_addr(struct eth_device* dev, bd_t *bis)
checksum = (checksum ^ (checksum >> 8)) & 0xff;
if (checksum != 0xbb)
printf(" *** INVALID EEPROM CHECKSUM %4.4x *** \n", checksum);
printf (" *** INVALID EEPROM CHECKSUM %4.4x *** \n",
checksum);
for (i = 0, j = 0; i < 3; i++)
{
for (i = 0, j = 0; i < 3; i++) {
hw_addr[j++] = (u8) ((eeprom[i + 10] >> 8) & 0xff);
hw_addr[j++] = (u8) (eeprom[i + 10] & 0xff);
}
@ -842,16 +821,13 @@ static void read_hw_addr(struct eth_device* dev, bd_t *bis)
for (i = 0; i < 6; i++)
ETH_OUTB (dev, hw_addr[i], i);
for (j = 0; j < ETH_ALEN; j+=2)
{
for (j = 0; j < ETH_ALEN; j += 2) {
hw_addr[j] = (u8) (ETH_INW (dev, j) & 0xff);
hw_addr[j + 1] = (u8) ((ETH_INW (dev, j) >> 8) & 0xff);
}
for (i=0;i<ETH_ALEN;i++)
{
if (hw_addr[i] != bis->bi_enetaddr[i])
{
for (i = 0; i < ETH_ALEN; i++) {
if (hw_addr[i] != bis->bi_enetaddr[i]) {
/* printf("Warning: HW address don't match:\n"); */
/* printf("Address in 3Com Window 2 is " */
/* "%02X:%02X:%02X:%02X:%02X:%02X\n", */
@ -864,12 +840,16 @@ static void read_hw_addr(struct eth_device* dev, bd_t *bis)
/* bis->bi_enetaddr[4], bis->bi_enetaddr[5]); */
/* goto Done; */
char buffer[256];
if (bis->bi_enetaddr[0] == 0 && bis->bi_enetaddr[1] == 0 &&
bis->bi_enetaddr[2] == 0 && bis->bi_enetaddr[3] == 0 &&
bis->bi_enetaddr[4] == 0 && bis->bi_enetaddr[5] == 0)
{
sprintf(buffer, "%02X:%02X:%02X:%02X:%02X:%02X",
if (bis->bi_enetaddr[0] == 0
&& bis->bi_enetaddr[1] == 0
&& bis->bi_enetaddr[2] == 0
&& bis->bi_enetaddr[3] == 0
&& bis->bi_enetaddr[4] == 0
&& bis->bi_enetaddr[5] == 0) {
sprintf (buffer,
"%02X:%02X:%02X:%02X:%02X:%02X",
hw_addr[0], hw_addr[1], hw_addr[2],
hw_addr[3], hw_addr[4], hw_addr[5]);
setenv ("ethaddr", buffer);
@ -877,7 +857,8 @@ static void read_hw_addr(struct eth_device* dev, bd_t *bis)
}
}
for(i=0; i<ETH_ALEN; i++) dev->enetaddr[i] = hw_addr[i];
for (i = 0; i < ETH_ALEN; i++)
dev->enetaddr[i] = hw_addr[i];
Done:
return;

41
board/MAI/AmigaOneG3SE/ps2kbd.c
View File

@ -197,17 +197,18 @@ static unsigned char kbd_ctrl_xlate[] = {
int isa_kbd_init (void)
{
char *result;
result = kbd_initialize ();
if (result != NULL)
{
if (result != NULL) {
result = kbd_initialize ();
}
if (result == NULL) {
printf ("AT Keyboard initialized\n");
irq_install_handler(KBD_INTERRUPT, (interrupt_handler_t *)kbd_interrupt, NULL);
irq_install_handler (KBD_INTERRUPT,
(interrupt_handler_t *) kbd_interrupt,
NULL);
return (1);
}
else {
} else {
printf ("%s\n", result);
return (-1);
}
@ -301,7 +302,6 @@ int kbd_getc(void)
}
/* set LEDs */
void kbd_set_leds(void)
@ -322,7 +322,6 @@ void kbd_set_leds(void)
kbd_send_data(leds);
}
void handle_keyboard_event (unsigned char scancode)
{
unsigned char keycode;
@ -342,13 +341,13 @@ void handle_keyboard_event(unsigned char scancode)
((scancode) == 0x48) || /* arrow up */
((scancode) == 0x50) || /* arrow down */
((scancode) == 0x4b) || /* arrow left */
((scancode)==0x4d))) /* arrow right */
((scancode) == 0x4d)))
/* arrow right */
/* we swallow unknown e0 codes */
return;
}
/* special cntrl keys */
switch(scancode)
{
switch (scancode) {
case 0x48:
kbd_put_queue (27);
kbd_put_queue (91);
@ -370,9 +369,9 @@ void handle_keyboard_event(unsigned char scancode)
kbd_put_queue ('C');
return;
case 0x58: /* F12 key */
if (ctrl == 1)
{
if (ctrl == 1) {
extern int console_changed;
setenv ("stdin", DEVNAME);
setenv ("stdout", "vga");
console_changed = 1;
@ -476,10 +475,8 @@ unsigned char handle_kbd_event(void)
/* Error bytes must be ignored to make the
Synaptics touchpads compaq use work */
/* Ignore error bytes */
if (!(status & (KBD_STAT_GTO | KBD_STAT_PERR)))
{
if (status & KBD_STAT_MOUSE_OBF)
; /* not supported: handle_mouse_event(scancode); */
if (!(status & (KBD_STAT_GTO | KBD_STAT_PERR))) {
if (status & KBD_STAT_MOUSE_OBF); /* not supported: handle_mouse_event(scancode); */
else
handle_keyboard_event (scancode);
}
@ -490,7 +487,6 @@ unsigned char handle_kbd_event(void)
return status;
}
/******************************************************************************
* Lowlevel Part of keyboard section
*/
@ -536,8 +532,7 @@ int kbd_wait_for_input(void)
timeout = KBD_TIMEOUT;
val = kbd_read_data ();
while(val < 0)
{
while (val < 0) {
if (timeout-- == 0)
return -1;
udelay (1000);
@ -553,6 +548,7 @@ int kb_wait(void)
do {
unsigned char status = handle_kbd_event ();
if (!(status & KBD_STAT_IBF))
return 0; /* ok */
udelay (1000);
@ -578,6 +574,7 @@ void kbd_write_output_w(int data)
void kbd_send_data (unsigned char data)
{
unsigned char status;
i8259_mask_irq (KBD_INTERRUPT); /* disable interrupt */
kbd_write_output_w (data);
status = kbd_wait_for_input ();
@ -626,8 +623,7 @@ char * kbd_initialize(void)
status = kbd_wait_for_input ();
if (status == KBD_REPLY_ACK)
break;
if (status != KBD_REPLY_RESEND)
{
if (status != KBD_REPLY_RESEND) {
PRINTF ("status: %X\n", status);
return "Kbd: reset failed, no ACK";
}
@ -653,8 +649,7 @@ char * kbd_initialize(void)
kbd_write_command_w (KBD_CCMD_WRITE_MODE);
kbd_write_output_w (KBD_MODE_KBD_INT
| KBD_MODE_SYS
| KBD_MODE_DISABLE_MOUSE
| KBD_MODE_KCC);
| KBD_MODE_DISABLE_MOUSE | KBD_MODE_KCC);
/* AMCC powerpc portables need this to use scan-code set 1 -- Cort */
kbd_write_command_w (KBD_CCMD_READ_MODE);

34
board/MAI/menu/menu.h
View File

@ -4,8 +4,7 @@
/* A single menu */
typedef void (*menu_finish_callback)(struct menu_s *menu);
typedef struct menu_s
{
typedef struct menu_s {
char *name; /* Menu name */
int num_options; /* Number of options in this menu */
int flags; /* Various flags - see below */
@ -28,8 +27,7 @@ typedef struct menu_s
char *name; \
char *help; \
int id; \
void *sys; \
void *sys;
/*
* Menu option types.
@ -110,17 +108,13 @@ typedef struct menu_text_s
#define MENU_SELECTION_TYPE 3
typedef struct menu_select_option_s
{
typedef struct menu_select_option_s {
char *map_from; /* Map this variable contents ... */
char *map_to; /* ... to this menu text and vice versa */
} menu_select_option_t;
typedef struct menu_select_s
{
OPTION_PREAMBLE
int num_options; /* Number of mappings */
typedef struct menu_select_s {
OPTION_PREAMBLE int num_options; /* Number of mappings */
menu_select_option_t **options;
/* Option list array */
} menu_select_t;
@ -129,10 +123,8 @@ typedef struct menu_select_s
#define MENU_ROUTINE_TYPE 4
typedef void (*menu_routine_callback) (struct menu_routine_s *);
typedef struct menu_routine_s
{
OPTION_PREAMBLE
menu_routine_callback callback;
typedef struct menu_routine_s {
OPTION_PREAMBLE menu_routine_callback callback;
/* routine to be called */
void *user_data; /* User data, don't care for system */
} menu_routine_t;
@ -142,10 +134,8 @@ typedef struct menu_routine_s
typedef void (*menu_custom_draw) (struct menu_custom_s *);
typedef void (*menu_custom_key) (struct menu_custom_s *, int);
typedef struct menu_custom_s
{
OPTION_PREAMBLE
menu_custom_draw drawfunc;
typedef struct menu_custom_s {
OPTION_PREAMBLE menu_custom_draw drawfunc;
menu_custom_key keyfunc;
void *user_data;
} menu_custom_t;
@ -153,10 +143,8 @@ typedef struct menu_custom_s
/*
* The menu option superstructure
*/
typedef struct menu_option_s
{
union
{
typedef struct menu_option_s {
union {
menu_submenu_t m_sub_menu;
menu_boolean_t m_boolean;
menu_text_t m_text;

4
board/RPXlite_dw/flash.c
View File

@ -178,8 +178,8 @@ static ulong flash_get_size (vu_long *addr, flash_info_t *info)
value = addr[0] ;
switch (value & 0x00FF00FF) {
case AMD_MANUFACT: /* AMD_MANUFACT=0x00010001 in flash.h. */
info->flash_id = FLASH_MAN_AMD; /* FLASH_MAN_AMD=0x00000000 in flash.h.*/
case AMD_MANUFACT: /* AMD_MANUFACT =0x00010001 in flash.h */
info->flash_id = FLASH_MAN_AMD; /* FLASH_MAN_AMD=0x00000000 in flash.h */
break;
case FUJ_MANUFACT:
info->flash_id = FLASH_MAN_FUJ;

5
board/ads5121/Makefile
View File

@ -23,9 +23,14 @@
include $(TOPDIR)/config.mk
$(shell mkdir -p $(OBJTREE)/board/freescale/common)
LIB = $(obj)lib$(BOARD).a
COBJS-y := $(BOARD).o
COBJS-${CONFIG_FSL_DIU_FB} += ads5121_diu.o
COBJS-${CONFIG_FSL_DIU_FB} += ../freescale/common/fsl_diu_fb.o
COBJS-${CONFIG_FSL_DIU_FB} += ../freescale/common/fsl_logo_bmp.o
COBJS-$(CONFIG_PCI) += pci.o
COBJS := $(COBJS-y)

62
board/ads5121/ads5121.c
View File

@ -39,17 +39,35 @@
#define SCCR2_CLOCKS_EN (CLOCK_SCCR2_MEM_EN | \
CLOCK_SCCR2_SPDIF_EN | \
CLOCK_SCCR2_DIU_EN | \
CLOCK_SCCR2_I2C_EN)
#define CSAW_START(start) ((start) & 0xFFFF0000)
#define CSAW_STOP(start, size) (((start) + (size) - 1) >> 16)
#define MPC5121_IOCTL_PSC6_0 (0x284/4)
#define MPC5121_IO_DIU_START (0x288/4)
#define MPC5121_IO_DIU_END (0x2fc/4)
/* Functional pin muxing */
#define MPC5121_IO_FUNC1 (0 << 7)
#define MPC5121_IO_FUNC2 (1 << 7)
#define MPC5121_IO_FUNC3 (2 << 7)
#define MPC5121_IO_FUNC4 (3 << 7)
#define MPC5121_IO_ST (1 << 2)
#define MPC5121_IO_DS_1 (0)
#define MPC5121_IO_DS_2 (1)
#define MPC5121_IO_DS_3 (2)
#define MPC5121_IO_DS_4 (3)
long int fixed_sdram(void);
int board_early_init_f (void)
{
volatile immap_t *im = (immap_t *) CFG_IMMR;
u32 lpcaw;
u32 lpcaw, tmp32;
volatile ioctrl512x_t *ioctl = &(im->io_ctrl);
int i;
/*
* Initialize Local Window for the CPLD registers access (CS2 selects
@ -81,6 +99,16 @@ int board_early_init_f (void)
im->clk.sccr[0] = SCCR1_CLOCKS_EN;
im->clk.sccr[1] = SCCR2_CLOCKS_EN;
/* Configure DIU clock pin */
tmp32 = ioctl->regs[MPC5121_IOCTL_PSC6_0];
tmp32 &= ~0x1ff;
tmp32 |= MPC5121_IO_FUNC3 | MPC5121_IO_DS_4;
ioctl->regs[MPC5121_IOCTL_PSC6_0] = tmp32;
/* Initialize IO pins (pin mux) for DIU function */
for (i = MPC5121_IO_DIU_START; i < MPC5121_IO_DIU_END; i++)
ioctl->regs[i] |= (MPC5121_IO_FUNC3 | MPC5121_IO_DS_4);
return 0;
}
@ -186,6 +214,38 @@ long int fixed_sdram (void)
return msize;
}
int misc_init_r(void)
{
u8 tmp_val;
/* Using this for DIU init before the driver in linux takes over
* Enable the TFP410 Encoder (I2C address 0x38)
*/
i2c_set_bus_num(2);
tmp_val = 0xBF;
i2c_write(0x38, 0x08, 1, &tmp_val, sizeof(tmp_val));
/* Verify if enabled */
tmp_val = 0;
i2c_read(0x38, 0x08, 1, &tmp_val, sizeof(tmp_val));
debug("DVI Encoder Read: 0x%02lx\n", tmp_val);
tmp_val = 0x10;
i2c_write(0x38, 0x0A, 1, &tmp_val, sizeof(tmp_val));
/* Verify if enabled */
tmp_val = 0;
i2c_read(0x38, 0x0A, 1, &tmp_val, sizeof(tmp_val));
debug("DVI Encoder Read: 0x%02lx\n", tmp_val);
#ifdef CONFIG_FSL_DIU_FB
#if !(defined(CONFIG_VIDEO) || defined(CONFIG_CFB_CONSOLE))
ads5121_diu_init();
#endif
#endif
return 0;
}
int checkboard (void)
{
ushort brd_rev = *(vu_short *) (CFG_CPLD_BASE + 0x00);

165
board/ads5121/ads5121_diu.c Normal file
View File

@ -0,0 +1,165 @@
/*
* Copyright 2008 Freescale Semiconductor, Inc.
* York Sun <yorksun@freescale.com>
*
* FSL DIU Framebuffer driver
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <command.h>
#include <asm/io.h>
#ifdef CONFIG_FSL_DIU_FB
#include "../freescale/common/pixis.h"
#include "../freescale/common/fsl_diu_fb.h"
#if defined(CONFIG_VIDEO) || defined(CONFIG_CFB_CONSOLE)
#include <devices.h>
#include <video_fb.h>
#endif
extern unsigned int FSL_Logo_BMP[];
static int xres, yres;
void diu_set_pixel_clock(unsigned int pixclock)
{
volatile immap_t *immap = (immap_t *)CFG_IMMR;
volatile clk512x_t *clk = &immap->clk;
volatile unsigned int *clkdvdr = &clk->scfr[0];
unsigned long speed_ccb, temp, pixval;
speed_ccb = get_bus_freq(0) * 4;
temp = 1000000000/pixclock;
temp *= 1000;
pixval = speed_ccb / temp;
debug("DIU pixval = %lu\n", pixval);
/* Modify PXCLK in GUTS CLKDVDR */
debug("DIU: Current value of CLKDVDR = 0x%08x\n", *clkdvdr);
temp = *clkdvdr & 0xFFFFFF00;
*clkdvdr = temp | (pixval & 0x1F);
debug("DIU: Modified value of CLKDVDR = 0x%08x\n", *clkdvdr);
}
int ads5121_diu_init(void)
{
unsigned int pixel_format;
xres = 1024;
yres = 768;
pixel_format = 0x88883316;
return fsl_diu_init(xres, pixel_format, 0,
(unsigned char *)FSL_Logo_BMP);
}
int ads5121diu_init_show_bmp(cmd_tbl_t *cmdtp,
int flag, int argc, char *argv[])
{
unsigned int addr;
if (argc < 2) {
printf("Usage:\n%s\n", cmdtp->usage);
return 1;
}
if (!strncmp(argv[1], "init", 4)) {
#if defined(CONFIG_VIDEO) || defined(CONFIG_CFB_CONSOLE)
fsl_diu_clear_screen();
drv_video_init();
#else
return ads5121_diu_init();
#endif
} else {
addr = simple_strtoul(argv[1], NULL, 16);
fsl_diu_clear_screen();
fsl_diu_display_bmp((unsigned char *)addr, 0, 0, 0);
}
return 0;
}
U_BOOT_CMD(
diufb, CFG_MAXARGS, 1, ads5121diu_init_show_bmp,
"diufb init | addr - Init or Display BMP file\n",
"init\n - initialize DIU\n"
"addr\n - display bmp at address 'addr'\n"
);
#if defined(CONFIG_VIDEO) || defined(CONFIG_CFB_CONSOLE)
/*
* The Graphic Device
*/
GraphicDevice ctfb;
void *video_hw_init(void)
{
GraphicDevice *pGD = (GraphicDevice *) &ctfb;
struct fb_info *info;
if (ads5121_diu_init() < 0)
return;
/* fill in Graphic device struct */
sprintf(pGD->modeIdent, "%dx%dx%d %ldkHz %ldHz",
xres, yres, 32, 64, 60);
pGD->frameAdrs = (unsigned int)fsl_fb_open(&info);
pGD->winSizeX = xres;
pGD->winSizeY = yres - info->logo_height;
pGD->plnSizeX = pGD->winSizeX;
pGD->plnSizeY = pGD->winSizeY;
pGD->gdfBytesPP = 4;
pGD->gdfIndex = GDF_32BIT_X888RGB;
pGD->isaBase = 0;
pGD->pciBase = 0;
pGD->memSize = info->screen_size - info->logo_size;
/* Cursor Start Address */
pGD->dprBase = 0;
pGD->vprBase = 0;
pGD->cprBase = 0;
return (void *)pGD;
}
/**
* Set the LUT
*
* @index: color number
* @r: red
* @b: blue
* @g: green
*/
void video_set_lut
(unsigned int index, unsigned char r, unsigned char g, unsigned char b)
{
return;
}
#endif /* defined(CONFIG_VIDEO) || defined(CONFIG_CFB_CONSOLE) */
#endif /* CONFIG_FSL_DIU_FB */

43
board/eric/flash.c
View File

@ -1016,7 +1016,8 @@ static int write_word (flash_info_t *info, ulong dest, ulong data)
if (info->flash_id > FLASH_AMD_COMP) {
while ((*((vu_long *)dest) & 0x00800080) != (data & 0x00800080)) {
while ((*((vu_long *) dest) & 0x00800080) !=
(data & 0x00800080)) {
if (get_timer (start) > CFG_FLASH_WRITE_TOUT) {
return (1);
}
@ -1036,10 +1037,14 @@ static int write_word (flash_info_t *info, ulong dest, ulong data)
} else {
barf = addr[0] & 0x0000003A;
}
printf("\nFlash write error at address %lx\n",(unsigned long)dest);
if(barf & 0x0002) printf("Block locked, not erased.\n");
if(barf & 0x0010) printf("Programming error.\n");
if(barf & 0x0008) printf("Vpp Low error.\n");
printf ("\nFlash write error at address %lx\n",
(unsigned long) dest);
if (barf & 0x0002)
printf ("Block locked, not erased.\n");
if (barf & 0x0010)
printf ("Programming error.\n");
if (barf & 0x0008)
printf ("Vpp Low error.\n");
return (2);
}
@ -1096,33 +1101,31 @@ static int write_short (flash_info_t *info, ulong dest, ushort data)
} else {
/* intel stuff */
while (!(addr[0] & 0x0080)) { /* wait for error or finish */
if (get_timer(start) > CFG_FLASH_WRITE_TOUT) return (1);
if (get_timer (start) > CFG_FLASH_WRITE_TOUT)
return (1);
}
if (addr[0] & 0x003A) { /* check for error */
barf = addr[0] & 0x003A;
printf("\nFlash write error at address %lx\n",(unsigned long)dest);
if(barf & 0x0002) printf("Block locked, not erased.\n");
if(barf & 0x0010) printf("Programming error.\n");
if(barf & 0x0008) printf("Vpp Low error.\n");
printf ("\nFlash write error at address %lx\n",
(unsigned long) dest);
if (barf & 0x0002)
printf ("Block locked, not erased.\n");
if (barf & 0x0010)
printf ("Programming error.\n");
if (barf & 0x0008)
printf ("Vpp Low error.\n");
return (2);
}
*addr = 0x00B0;
*addr = 0x0070;
while (!(addr[0] & 0x0080)) { /* wait for error or finish */
if (get_timer(start) > CFG_FLASH_WRITE_TOUT) return (1);
if (get_timer (start) > CFG_FLASH_WRITE_TOUT)
return (1);
}
*addr = 0x00FF;
}
return (0);
}
#endif
/*-----------------------------------------------------------------------
*/
/*-----------------------------------------------------------------------*/

3
board/esd/cpci750/sdram_init.c
View File

@ -134,8 +134,7 @@ typedef enum _max_CL_supported_SD {SD_CL_1=1, SD_CL_2, SD_CL_3, SD_CL_4, SD_CL
/* SDRAM/DDR information struct */
typedef struct _gtMemoryDimmInfo
{
typedef struct _gtMemoryDimmInfo {
MEMORY_TYPE memoryType;
unsigned int numOfRowAddresses;
unsigned int numOfColAddresses;

204
board/esteem192e/flash.c
View File

@ -39,6 +39,7 @@ flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
*/
ulong flash_get_size (volatile FLASH_WORD_SIZE * addr, flash_info_t * info);
#ifndef CONFIG_FLASH_16BIT
static int write_word (flash_info_t * info, ulong dest, ulong data);
#else
@ -65,22 +66,21 @@ unsigned long flash_init (void)
/* Static FLASH Bank configuration here - FIXME XXX */
size_b0 = flash_get_size((volatile FLASH_WORD_SIZE *)FLASH_BASE0_PRELIM,
&flash_info[0]);
size_b0 =
flash_get_size ((volatile FLASH_WORD_SIZE *)
FLASH_BASE0_PRELIM, &flash_info[0]);
if (flash_info[0].flash_id == FLASH_UNKNOWN) {
printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
size_b0, size_b0<<20);
printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n", size_b0, size_b0 << 20);
}
size_b1 = flash_get_size((volatile FLASH_WORD_SIZE *)FLASH_BASE1_PRELIM,
&flash_info[1]);
size_b1 =
flash_get_size ((volatile FLASH_WORD_SIZE *)
FLASH_BASE1_PRELIM, &flash_info[1]);
if (size_b1 > size_b0) {
printf ("## ERROR: "
"Bank 1 (0x%08lx = %ld MB) > Bank 0 (0x%08lx = %ld MB)\n",
size_b1, size_b1<<20,
size_b0, size_b0<<20
);
size_b1, size_b1 << 20, size_b0, size_b0 << 20);
flash_info[0].flash_id = FLASH_UNKNOWN;
flash_info[1].flash_id = FLASH_UNKNOWN;
flash_info[0].sector_count = -1;
@ -109,13 +109,17 @@ unsigned long flash_init (void)
#endif
if (size_b1) {
memctl->memc_or1 = CFG_OR_TIMING_FLASH | (-size_b1 & 0xFFFF8000);
memctl->memc_br1 = (CFG_FLASH_BASE | 0x00000801) + (size_b0 & BR_BA_MSK);
memctl->memc_or1 =
CFG_OR_TIMING_FLASH | (-size_b1 & 0xFFFF8000);
memctl->memc_br1 =
(CFG_FLASH_BASE | 0x00000801) + (size_b0 & BR_BA_MSK);
/*((CFG_FLASH_BASE + size_b0) & BR_BA_MSK) |
BR_MS_GPCM | BR_V; */
/* Re-do sizing to get full correct info */
size_b1 = flash_get_size((volatile FLASH_WORD_SIZE *)(CFG_FLASH_BASE + size_b0),
size_b1 =
flash_get_size ((volatile FLASH_WORD_SIZE
*) (CFG_FLASH_BASE + size_b0),
&flash_info[1]);
flash_get_offsets (CFG_FLASH_BASE + size_b0, &flash_info[1]);
@ -124,8 +128,8 @@ unsigned long flash_init (void)
/* monitor protection ON by default */
(void) flash_protect (FLAG_PROTECT_SET,
CFG_MONITOR_BASE,
CFG_MONITOR_BASE+monitor_flash_len-1,
&flash_info[1]);
CFG_MONITOR_BASE + monitor_flash_len -
1, &flash_info[1]);
#endif
} else {
memctl->memc_br1 = 0; /* invalidate bank */
@ -161,17 +165,18 @@ static void flash_get_offsets (ulong base, flash_info_t *info)
info->start[6] = base + 0x00018000;
info->start[7] = base + 0x0001C000;
for (i = 8; i < info->sector_count; i++) {
info->start[i] = base + (i * 0x00020000) - 0x000E0000;
info->start[i] =
base + (i * 0x00020000) - 0x000E0000;
}
}
else {
} else {
/* set sector offsets for bottom boot block type */
info->start[0] = base + 0x00000000;
info->start[1] = base + 0x00008000;
info->start[2] = base + 0x0000C000;
info->start[3] = base + 0x00010000;
for (i = 4; i < info->sector_count; i++) {
info->start[i] = base + (i * 0x00020000) - 0x00060000;
info->start[i] =
base + (i * 0x00020000) - 0x00060000;
}
}
#else
@ -185,17 +190,18 @@ static void flash_get_offsets (ulong base, flash_info_t *info)
info->start[6] = base + 0x0000C000;
info->start[7] = base + 0x0000E000;
for (i = 8; i < info->sector_count; i++) {
info->start[i] = base + (i * 0x00010000) - 0x00070000;
info->start[i] =
base + (i * 0x00010000) - 0x00070000;
}
}
else {
} else {
/* set sector offsets for bottom boot block type */
info->start[0] = base + 0x00000000;
info->start[1] = base + 0x00004000;
info->start[2] = base + 0x00006000;
info->start[3] = base + 0x00008000;
for (i = 4; i < info->sector_count; i++) {
info->start[i] = base + (i * 0x00010000) - 0x00030000;
info->start[i] =
base + (i * 0x00010000) - 0x00030000;
}
}
#endif
@ -267,12 +273,24 @@ void flash_print_info (flash_info_t *info)
}
switch (info->flash_id & FLASH_VENDMASK) {
case FLASH_MAN_AMD: printf ("AMD "); break;
case FLASH_MAN_FUJ: printf ("FUJITSU "); break;
case FLASH_MAN_SST: printf ("SST "); break;
case FLASH_MAN_STM: printf ("STM "); break;
case FLASH_MAN_INTEL: printf ("INTEL "); break;
default: printf ("Unknown Vendor "); break;
case FLASH_MAN_AMD:
printf ("AMD ");
break;
case FLASH_MAN_FUJ:
printf ("FUJITSU ");
break;
case FLASH_MAN_SST:
printf ("SST ");
break;
case FLASH_MAN_STM:
printf ("STM ");
break;
case FLASH_MAN_INTEL:
printf ("INTEL ");
break;
default:
printf ("Unknown Vendor ");
break;
}
if (info->flash_id & 0x0001) {
@ -282,44 +300,61 @@ void flash_print_info (flash_info_t *info)
}
switch (info->flash_id & FLASH_TYPEMASK) {
case FLASH_AM400B: printf ("AM29LV400B (4 Mbit%s",boottype);
case FLASH_AM400B:
printf ("AM29LV400B (4 Mbit%s", boottype);
break;
case FLASH_AM400T: printf ("AM29LV400T (4 Mbit%s",boottype);
case FLASH_AM400T:
printf ("AM29LV400T (4 Mbit%s", boottype);
break;
case FLASH_AM800B: printf ("AM29LV800B (8 Mbit%s",boottype);
case FLASH_AM800B:
printf ("AM29LV800B (8 Mbit%s", boottype);
break;
case FLASH_AM800T: printf ("AM29LV800T (8 Mbit%s",boottype);
case FLASH_AM800T:
printf ("AM29LV800T (8 Mbit%s", boottype);
break;
case FLASH_AM160B: printf ("AM29LV160B (16 Mbit%s",boottype);
case FLASH_AM160B:
printf ("AM29LV160B (16 Mbit%s", boottype);
break;
case FLASH_AM160T: printf ("AM29LV160T (16 Mbit%s",boottype);
case FLASH_AM160T:
printf ("AM29LV160T (16 Mbit%s", boottype);
break;
case FLASH_AM320B: printf ("AM29LV320B (32 Mbit%s",boottype);
case FLASH_AM320B:
printf ("AM29LV320B (32 Mbit%s", boottype);
break;
case FLASH_AM320T: printf ("AM29LV320T (32 Mbit%s",boottype);
case FLASH_AM320T:
printf ("AM29LV320T (32 Mbit%s", boottype);
break;
case FLASH_INTEL800B: printf ("INTEL28F800B (8 Mbit%s",boottype);
case FLASH_INTEL800B:
printf ("INTEL28F800B (8 Mbit%s", boottype);
break;
case FLASH_INTEL800T: printf ("INTEL28F800T (8 Mbit%s",boottype);
case FLASH_INTEL800T:
printf ("INTEL28F800T (8 Mbit%s", boottype);
break;
case FLASH_INTEL160B: printf ("INTEL28F160B (16 Mbit%s",boottype);
case FLASH_INTEL160B:
printf ("INTEL28F160B (16 Mbit%s", boottype);
break;
case FLASH_INTEL160T: printf ("INTEL28F160T (16 Mbit%s",boottype);
case FLASH_INTEL160T:
printf ("INTEL28F160T (16 Mbit%s", boottype);
break;
case FLASH_INTEL320B: printf ("INTEL28F320B (32 Mbit%s",boottype);
case FLASH_INTEL320B:
printf ("INTEL28F320B (32 Mbit%s", boottype);
break;
case FLASH_INTEL320T: printf ("INTEL28F320T (32 Mbit%s",boottype);
case FLASH_INTEL320T:
printf ("INTEL28F320T (32 Mbit%s", boottype);
break;
#if 0 /* enable when devices are available */
case FLASH_INTEL640B: printf ("INTEL28F640B (64 Mbit%s",boottype);
case FLASH_INTEL640B:
printf ("INTEL28F640B (64 Mbit%s", boottype);
break;
case FLASH_INTEL640T: printf ("INTEL28F640T (64 Mbit%s",boottype);
case FLASH_INTEL640T:
printf ("INTEL28F640T (64 Mbit%s", boottype);
break;
#endif
default: printf ("Unknown Chip Type\n");
default:
printf ("Unknown Chip Type\n");
break;
}
@ -331,9 +366,7 @@ void flash_print_info (flash_info_t *info)
if ((i % 5) == 0)
printf ("\n ");
printf (" %08lX%s",
info->start[i],
info->protect[i] ? " (RO)" : " "
);
info->start[i], info->protect[i] ? " (RO)" : " ");
}
printf ("\n");
return;
@ -536,17 +569,18 @@ ulong flash_get_size (volatile FLASH_WORD_SIZE *addr, flash_info_t *info)
info->start[6] = base + 0x00018000;
info->start[7] = base + 0x0001C000;
for (i = 8; i < info->sector_count; i++) {
info->start[i] = base + (i * 0x00020000) - 0x000E0000;
info->start[i] =
base + (i * 0x00020000) - 0x000E0000;
}
}
else {
} else {
/* set sector offsets for bottom boot block type */
info->start[0] = base + 0x00000000;
info->start[1] = base + 0x00008000;
info->start[2] = base + 0x0000C000;
info->start[3] = base + 0x00010000;
for (i = 4; i < info->sector_count; i++) {
info->start[i] = base + (i * 0x00020000) - 0x00060000;
info->start[i] =
base + (i * 0x00020000) - 0x00060000;
}
}
#else
@ -560,17 +594,18 @@ ulong flash_get_size (volatile FLASH_WORD_SIZE *addr, flash_info_t *info)
info->start[6] = base + 0x0000C000;
info->start[7] = base + 0x0000E000;
for (i = 8; i < info->sector_count; i++) {
info->start[i] = base + (i * 0x00010000) - 0x00070000;
info->start[i] =
base + (i * 0x00010000) - 0x00070000;
}
}
else {
} else {
/* set sector offsets for bottom boot block type */
info->start[0] = base + 0x00000000;
info->start[1] = base + 0x00004000;
info->start[2] = base + 0x00006000;
info->start[3] = base + 0x00008000;
for (i = 4; i < info->sector_count; i++) {
info->start[i] = base + (i * 0x00010000) - 0x00030000;
info->start[i] =
base + (i * 0x00010000) - 0x00030000;
}
}
#endif
@ -654,7 +689,8 @@ ulong flash_get_size (volatile FLASH_WORD_SIZE *addr, flash_info_t *info)
int flash_erase (flash_info_t * info, int s_first, int s_last)
{
volatile FLASH_WORD_SIZE *addr=(volatile FLASH_WORD_SIZE*)(info->start[0]);
volatile FLASH_WORD_SIZE *addr =
(volatile FLASH_WORD_SIZE *) (info->start[0]);
int flag, prot, sect, l_sect, barf;
ulong start, now, last;
int rcode = 0;
@ -683,8 +719,7 @@ int flash_erase (flash_info_t *info, int s_first, int s_last)
}
if (prot) {
printf ("- Warning: %d protected sectors will not be erased!\n",
prot);
printf ("- Warning: %d protected sectors will not be erased!\n", prot);
} else {
printf ("\n");
}
@ -733,8 +768,7 @@ int flash_erase (flash_info_t *info, int s_first, int s_last)
last = start;
addr = (volatile FLASH_WORD_SIZE *) (info->start[l_sect]);
while ((addr[0] & (0x00800080 & FLASH_ID_MASK)) !=
(0x00800080&FLASH_ID_MASK) )
{
(0x00800080 & FLASH_ID_MASK)) {
if ((now = get_timer (start)) > CFG_FLASH_ERASE_TOUT) {
printf ("Timeout\n");
return 1;
@ -779,14 +813,17 @@ DONE:
#endif
if (barf) {
printf ("\nFlash error in sector at %lx\n", (unsigned long) addr);
if(barf & 0x0002) printf("Block locked, not erased.\n");
if (barf & 0x0002)
printf ("Block locked, not erased.\n");
if ((barf & 0x0030) == 0x0030)
printf ("Command Sequence error.\n");
if ((barf & 0x0030) == 0x0020)
printf ("Block Erase error.\n");
if(barf & 0x0008) printf("Vpp Low error.\n");
if (barf & 0x0008)
printf ("Vpp Low error.\n");
rcode = 1;
} else printf(".");
} else
printf (".");
l_sect = sect;
}
addr = (volatile FLASH_WORD_SIZE *) info->start[0];
@ -983,7 +1020,8 @@ static int write_word (flash_info_t *info, ulong dest, ulong data)
if (info->flash_id > FLASH_AMD_COMP) {
while ((*((vu_long *)dest) & 0x00800080) != (data & 0x00800080)) {
while ((*((vu_long *) dest) & 0x00800080) !=
(data & 0x00800080)) {
if (get_timer (start) > CFG_FLASH_WRITE_TOUT) {
return (1);
}
@ -1004,9 +1042,12 @@ static int write_word (flash_info_t *info, ulong dest, ulong data)
barf = addr[0] & 0x0000003A;
}
printf ("\nFlash write error at address %lx\n", (unsigned long) dest);
if(barf & 0x0002) printf("Block locked, not erased.\n");
if(barf & 0x0010) printf("Programming error.\n");
if(barf & 0x0008) printf("Vpp Low error.\n");
if (barf & 0x0002)
printf ("Block locked, not erased.\n");
if (barf & 0x0010)
printf ("Programming error.\n");
if (barf & 0x0008)
printf ("Vpp Low error.\n");
return (2);
}
@ -1063,33 +1104,32 @@ static int write_short (flash_info_t *info, ulong dest, ushort data)
} else {
/* intel stuff */
while (!(addr[0] & 0x0080)) { /* wait for error or finish */
if (get_timer(start) > CFG_FLASH_WRITE_TOUT) return (1);
if (get_timer (start) > CFG_FLASH_WRITE_TOUT)
return (1);
}
if (addr[0] & 0x003A) { /* check for error */
barf = addr[0] & 0x003A;
printf("\nFlash write error at address %lx\n",(unsigned long)dest);
if(barf & 0x0002) printf("Block locked, not erased.\n");
if(barf & 0x0010) printf("Programming error.\n");
if(barf & 0x0008) printf("Vpp Low error.\n");
printf ("\nFlash write error at address %lx\n",
(unsigned long) dest);
if (barf & 0x0002)
printf ("Block locked, not erased.\n");
if (barf & 0x0010)
printf ("Programming error.\n");
if (barf & 0x0008)
printf ("Vpp Low error.\n");
return (2);
}
*addr = 0x00B0;
*addr = 0x0070;
while (!(addr[0] & 0x0080)) { /* wait for error or finish */
if (get_timer(start) > CFG_FLASH_WRITE_TOUT) return (1);
if (get_timer (start) > CFG_FLASH_WRITE_TOUT)
return (1);
}
*addr = 0x00FF;
}
return (0);
}
#endif
/*-----------------------------------------------------------------------
*/
/*-----------------------------------------------------------------------*/

101
board/freescale/common/fsl_diu_fb.c
View File

@ -29,12 +29,6 @@
#include "fsl_diu_fb.h"
#ifdef DEBUG
#define DPRINTF(fmt, args...) printf("%s: " fmt,__FUNCTION__,## args)
#else
#define DPRINTF(fmt, args...)
#endif
struct fb_videomode {
const char *name; /* optional */
unsigned int refresh; /* optional */
@ -163,8 +157,6 @@ struct diu_addr {
unsigned int offset;
};
#define FSL_DIU_BASE_OFFSET 0x2C000 /* Offset of Display Interface Unit */
/*
* Modes of operation of DIU
*/
@ -197,7 +189,7 @@ static void disable_lcdc(void);
static int fsl_diu_enable_panel(struct fb_info *info);
static int fsl_diu_disable_panel(struct fb_info *info);
static int allocate_buf(struct diu_addr *buf, u32 size, u32 bytes_align);
static u32 get_busfreq(void);
void diu_set_pixel_clock(unsigned int pixclock);
int fsl_diu_init(int xres,
unsigned int pixel_format,
@ -209,15 +201,11 @@ int fsl_diu_init(int xres,
struct diu *hw;
struct fb_info *info = &fsl_fb_info;
struct fb_var_screeninfo *var = &info->var;
volatile immap_t *immap = (immap_t *)CFG_IMMR;
volatile ccsr_gur_t *gur = &immap->im_gur;
volatile unsigned int *guts_clkdvdr = &gur->clkdvdr;
unsigned char *gamma_table_base;
unsigned int i, j;
unsigned long speed_ccb, temp, pixval;
DPRINTF("Enter fsl_diu_init\n");
dr.diu_reg = (struct diu *) (CFG_IMMR + FSL_DIU_BASE_OFFSET);
debug("Enter fsl_diu_init\n");
dr.diu_reg = (struct diu *) (CFG_DIU_ADDR);
hw = (struct diu *) dr.diu_reg;
disable_lcdc();
@ -230,10 +218,10 @@ int fsl_diu_init(int xres,
if (0 == fb_initialized) {
allocate_buf(&gamma, 768, 32);
DPRINTF("gamma is allocated @ 0x%x\n",
debug("gamma is allocated @ 0x%x\n",
(unsigned int)gamma.paddr);
allocate_buf(&cursor, MAX_CURS * MAX_CURS * 2, 32);
DPRINTF("curosr is allocated @ 0x%x\n",
debug("curosr is allocated @ 0x%x\n",
(unsigned int)cursor.paddr);
/* create a dummy fb and dummy ad */
@ -261,8 +249,8 @@ int fsl_diu_init(int xres,
dr.diu_reg->desc[0] = (unsigned int) &dummy_ad;
dr.diu_reg->desc[1] = (unsigned int) &dummy_ad;
dr.diu_reg->desc[2] = (unsigned int) &dummy_ad;
DPRINTF("dummy dr.diu_reg->desc[0] = 0x%x\n", dr.diu_reg->desc[0]);
DPRINTF("dummy desc[0] = 0x%x\n", hw->desc[0]);
debug("dummy dr.diu_reg->desc[0] = 0x%x\n", dr.diu_reg->desc[0]);
debug("dummy desc[0] = 0x%x\n", hw->desc[0]);
/* read mode info */
var->xres = fsl_diu_mode_db->xres;
@ -300,7 +288,7 @@ int fsl_diu_init(int xres,
ad->ckmin_b = 255;
gamma_table_base = gamma.paddr;
DPRINTF("gamma_table_base is allocated @ 0x%x\n",
debug("gamma_table_base is allocated @ 0x%x\n",
(unsigned int)gamma_table_base);
/* Prep for DIU init - gamma table */
@ -310,7 +298,7 @@ int fsl_diu_init(int xres,
*gamma_table_base++ = j;
if (gamma_fix == 1) { /* fix the gamma */
DPRINTF("Fix gamma table\n");
debug("Fix gamma table\n");
gamma_table_base = gamma.paddr;
for (i = 0; i < 256*3; i++) {
gamma_table_base[i] = (gamma_table_base[i] << 2)
@ -318,7 +306,7 @@ int fsl_diu_init(int xres,
}
}
DPRINTF("update-lcdc: HW - %p\n Disabling DIU\n", hw);
debug("update-lcdc: HW - %p\n Disabling DIU\n", hw);
/* Program DIU registers */
@ -336,37 +324,22 @@ int fsl_diu_init(int xres,
var->vsync_len << 11 | /* PW_V */
var->lower_margin; /* FP_V */
/* Pixel Clock configuration */
DPRINTF("DIU: Bus Frequency = %d\n", get_busfreq());
speed_ccb = get_busfreq();
DPRINTF("DIU pixclock in ps - %d\n", var->pixclock);
temp = 1;
temp *= 1000000000;
temp /= var->pixclock;
temp *= 1000;
pixval = speed_ccb / temp;
DPRINTF("DIU pixval = %lu\n", pixval);
hw->syn_pol = 0; /* SYNC SIGNALS POLARITY */
hw->thresholds = 0x00037800; /* The Thresholds */
hw->int_status = 0; /* INTERRUPT STATUS */
hw->int_mask = 0; /* INT MASK */
hw->plut = 0x01F5F666;
/* Modify PXCLK in GUTS CLKDVDR */
DPRINTF("DIU: Current value of CLKDVDR = 0x%08x\n", *guts_clkdvdr);
temp = *guts_clkdvdr & 0x2000FFFF;
*guts_clkdvdr = temp; /* turn off clock */
*guts_clkdvdr = temp | 0x80000000 | ((pixval & 0x1F) << 16);
DPRINTF("DIU: Modified value of CLKDVDR = 0x%08x\n", *guts_clkdvdr);
/* Pixel Clock configuration */
debug("DIU pixclock in ps - %d\n", var->pixclock);
diu_set_pixel_clock(var->pixclock);
fb_initialized = 1;
if (splash_bmp) {
info->logo_height = fsl_diu_display_bmp(splash_bmp, 0, 0, 0);
info->logo_size = info->logo_height * info->line_length;
DPRINTF("logo height %d, logo_size 0x%x\n",
debug("logo height %d, logo_size 0x%x\n",
info->logo_height,info->logo_size);
}
@ -395,10 +368,10 @@ static int fsl_diu_enable_panel(struct fb_info *info)
struct diu *hw = dr.diu_reg;
struct diu_ad *ad = &fsl_diu_fb_ad;
DPRINTF("Entered: enable_panel\n");
debug("Entered: enable_panel\n");
if (hw->desc[0] != (unsigned int)ad)
hw->desc[0] = (unsigned int)ad;
DPRINTF("desc[0] = 0x%x\n", hw->desc[0]);
debug("desc[0] = 0x%x\n", hw->desc[0]);
return 0;
}
@ -406,7 +379,7 @@ static int fsl_diu_disable_panel(struct fb_info *info)
{
struct diu *hw = dr.diu_reg;
DPRINTF("Entered: disable_panel\n");
debug("Entered: disable_panel\n");
if (hw->desc[0] != (unsigned int)&dummy_ad)
hw->desc[0] = (unsigned int)&dummy_ad;
return 0;
@ -417,10 +390,10 @@ static int map_video_memory(struct fb_info *info, unsigned long bytes_align)
unsigned long offset;
unsigned long mask;
DPRINTF("Entered: map_video_memory\n");
debug("Entered: map_video_memory\n");
/* allocate maximum 1280*1024 with 32bpp */
info->smem_len = 1280 * 4 *1024 + bytes_align;
DPRINTF("MAP_VIDEO_MEMORY: smem_len = %d\n", info->smem_len);
debug("MAP_VIDEO_MEMORY: smem_len = %d\n", info->smem_len);
info->screen_base = malloc(info->smem_len);
if (info->screen_base == NULL) {
printf("Unable to allocate fb memory\n");
@ -437,7 +410,7 @@ static int map_video_memory(struct fb_info *info, unsigned long bytes_align)
info->screen_size = info->smem_len;
DPRINTF("Allocated fb @ 0x%08lx, size=%d.\n",
debug("Allocated fb @ 0x%08lx, size=%d.\n",
info->smem_start, info->smem_len);
return 0;
@ -447,33 +420,25 @@ static void enable_lcdc(void)
{
struct diu *hw = dr.diu_reg;
DPRINTF("Entered: enable_lcdc, fb_enabled = %d\n", fb_enabled);
debug("Entered: enable_lcdc, fb_enabled = %d\n", fb_enabled);
if (!fb_enabled) {
hw->diu_mode = dr.mode;
fb_enabled++;
}
DPRINTF("diu_mode = %d\n", hw->diu_mode);
debug("diu_mode = %d\n", hw->diu_mode);
}
static void disable_lcdc(void)
{
struct diu *hw = dr.diu_reg;
DPRINTF("Entered: disable_lcdc, fb_enabled = %d\n", fb_enabled);
debug("Entered: disable_lcdc, fb_enabled = %d\n", fb_enabled);
if (fb_enabled) {
hw->diu_mode = 0;
fb_enabled = 0;
}
}
static u32 get_busfreq(void)
{
u32 fs_busfreq = 0;
fs_busfreq = get_bus_freq(0);
return fs_busfreq;
}
/*
* Align to 64-bit(8-byte), 32-byte, etc.
*/
@ -482,7 +447,7 @@ static int allocate_buf(struct diu_addr *buf, u32 size, u32 bytes_align)
u32 offset, ssize;
u32 mask;
DPRINTF("Entered: allocate_buf\n");
debug("Entered: allocate_buf\n");
ssize = size + bytes_align;
buf->paddr = malloc(ssize);
if (!buf->paddr)
@ -524,16 +489,16 @@ int fsl_diu_display_bmp(unsigned char *bmp,
bitmap = bmp + raster;
cpp = info->var.bits_per_pixel / 8;
DPRINTF("bmp = 0x%08x\n", (unsigned int)bmp);
DPRINTF("bitmap = 0x%08x\n", (unsigned int)bitmap);
DPRINTF("width = %d\n", width);
DPRINTF("height = %d\n", height);
DPRINTF("bpp = %d\n", bpp);
DPRINTF("ncolors = %d\n", ncolors);
debug("bmp = 0x%08x\n", (unsigned int)bmp);
debug("bitmap = 0x%08x\n", (unsigned int)bitmap);
debug("width = %d\n", width);
debug("height = %d\n", height);
debug("bpp = %d\n", bpp);
debug("ncolors = %d\n", ncolors);
DPRINTF("xres = %d\n", info->var.xres);
DPRINTF("yres = %d\n", info->var.yres);
DPRINTF("Screen_base = 0x%x\n", (unsigned int)info->screen_base);
debug("xres = %d\n", info->var.xres);
debug("yres = %d\n", info->var.yres);
debug("Screen_base = 0x%x\n", (unsigned int)info->screen_base);
if (((width+xoffset) > info->var.xres) ||
((height+yoffset) > info->var.yres)) {

20
board/freescale/mpc8610hpcd/mpc8610hpcd_diu.c
View File

@ -41,6 +41,26 @@ extern unsigned int FSL_Logo_BMP[];
static int xres, yres;
void diu_set_pixel_clock(unsigned int pixclock)
{
volatile immap_t *immap = (immap_t *)CFG_IMMR;
volatile ccsr_gur_t *gur = &immap->im_gur;
volatile unsigned int *guts_clkdvdr = &gur->clkdvdr;
unsigned long speed_ccb, temp, pixval;
speed_ccb = get_bus_freq(0);
temp = 1000000000/pixclock;
temp *= 1000;
pixval = speed_ccb / temp;
debug("DIU pixval = %lu\n", pixval);
/* Modify PXCLK in GUTS CLKDVDR */
debug("DIU: Current value of CLKDVDR = 0x%08x\n", *guts_clkdvdr);
temp = *guts_clkdvdr & 0x2000FFFF;
*guts_clkdvdr = temp; /* turn off clock */
*guts_clkdvdr = temp | 0x80000000 | ((pixval & 0x1F) << 16);
debug("DIU: Modified value of CLKDVDR = 0x%08x\n", *guts_clkdvdr);
}
void mpc8610hpcd_diu_init(void)
{

2
board/gen860t/README
View File

@ -142,5 +142,3 @@ Sr. Staff Engineer
Microvision, Inc.
<keith_outwater@mvis.com>
<outwater@eskimo.com>
vim: set ts=4 sw=4 tw=78:

42
board/gen860t/beeper.c
View File

@ -34,7 +34,6 @@
* drives the amplifier input.
*/
/*
* Initialize beeper-related hardware. Initialize timer 1 for use with
* the beeper. Use 66 Mhz internal clock with prescale of 33 to get
@ -42,8 +41,7 @@
* FIXME: we should really compute the prescale based on the reported
* core clock frequency.
*/
void
init_beeper(void)
void init_beeper (void)
{
volatile immap_t *immap = (immap_t *) CFG_IMMR;
@ -55,14 +53,12 @@ init_beeper(void)
immap->im_cpmtimer.cpmt_tgcr |= TGCR_RST1;
}
/*
* Set beeper frequency. Max allowed frequency is 2.5 KHz. This limit
* is mostly arbitrary, but the beeper isn't really much good beyond this
* frequency.
*/
void
set_beeper_frequency(uint frequency)
void set_beeper_frequency (uint frequency)
{
#define FREQ_LIMIT 2500
@ -72,36 +68,32 @@ set_beeper_frequency(uint frequency)
* Compute timer ticks given desired frequency. The timer is set up
* to count 0.5 uS per tick and it takes two ticks per cycle (Hz).
*/
if (frequency > FREQ_LIMIT) frequency = FREQ_LIMIT;
if (frequency > FREQ_LIMIT)
frequency = FREQ_LIMIT;
frequency = 1000000 / frequency;
immap->im_cpmtimer.cpmt_trr1 = (ushort) frequency;
}
/*
* Turn the beeper on
*/
void
beeper_on(void)
void beeper_on (void)
{
volatile immap_t *immap = (immap_t *) CFG_IMMR;
immap->im_cpmtimer.cpmt_tgcr &= ~TGCR_STP1;
}
/*
* Turn the beeper off
*/
void
beeper_off(void)
void beeper_off (void)
{
volatile immap_t *immap = (immap_t *) CFG_IMMR;
immap->im_cpmtimer.cpmt_tgcr |= TGCR_STP1;
}
/*
* Increase or decrease the beeper volume. Volume can be set
* from off to full in 64 steps. To increase volume, the output
@ -110,8 +102,7 @@ beeper_off(void)
* change pin mode to tristate) then output a high to go back to
* tristate.
*/
void
set_beeper_volume(int steps)
void set_beeper_volume (int steps)
{
volatile immap_t *immap = (immap_t *) CFG_IMMR;
int i;
@ -123,8 +114,7 @@ set_beeper_volume(int steps)
immap->im_cpm.cp_pbodr |= (0x80000000 >> 19);
udelay (1);
}
}
else {
} else {
for (i = 0; i > (steps <= -64 ? -64 : steps); i--) {
immap->im_cpm.cp_pbdat &= ~(0x80000000 >> 19);
udelay (1);
@ -134,7 +124,6 @@ set_beeper_volume(int steps)
}
}
/*
* Check the environment to see if the beeper needs beeping.
* Controlled by a sequence of the form:
@ -146,8 +135,7 @@ set_beeper_volume(int steps)
*
* Return 1 on success, 0 on failure
*/
int
do_beeper(char *sequence)
int do_beeper (char *sequence)
{
#define DELIMITER ';'
@ -171,14 +159,14 @@ char *tp;
i = 0;
while (*p != '\0') {
while (*p != DELIMITER) {
if (i > 3) i = 0;
if (i > 3)
i = 0;
val = (int) simple_strtol (p, &tp, 0);
if (tp == p) {
printf ("%s:%d: no digits or bad format\n",
__FILE__, __LINE__);
return 0;
}
else {
} else {
args[i] = val;
}
@ -195,11 +183,11 @@ char *tp;
*/
#if 0
for (i = 0; i < 4; i++) {
printf("%s:%d:arg %d = %d\n", __FILE__, __LINE__, i, args[i]);
printf ("%s:%d:arg %d = %d\n", __FILE__, __LINE__, i,
args[i]);
}
printf ("\n");
#endif
set_beeper_frequency (args[0]);
set_beeper_volume (args[1]);
beeper_on ();
@ -209,5 +197,3 @@ char *tp;
}
return 1;
}
/* vim: set ts=4 sw=4 tw=78: */

2
board/gen860t/beeper.h
View File

@ -27,5 +27,3 @@ void beeper_on(void);
void beeper_off(void);
void set_beeper_volume(int steps);
int do_beeper(char *sequence);
/* vim: set ts=4 tw=78 sw=4: */

2
board/gen860t/fpga.c
View File

@ -376,5 +376,3 @@ int fpga_busy_fn (int cookie)
return 0;
}
#endif
/* vim: set ts=4 tw=78 sw=4: */

2
board/gen860t/fpga.h
View File

@ -41,5 +41,3 @@ extern int fpga_busy_fn(int cookie);
extern int fpga_abort_fn(int cookie );
extern int fpga_pre_config_fn(int cookie );
extern int fpga_post_config_fn(int cookie );
/* vim: set ts=4 sw=4 tw=78: */

2
board/gen860t/ioport.h
View File

@ -40,5 +40,3 @@ typedef struct {
} mpc8xx_iop_conf_t;
extern void config_mpc8xx_ioports(volatile immap_t *immr);
/* vim: set ts=4 tw=78 sw=4: */

12
board/mpl/common/kbd.c
View File

@ -197,8 +197,7 @@ int isa_kbd_init(void)
irq_install_handler(25, (interrupt_handler_t *)handle_isa_int, NULL);
isa_irq_install_handler(KBD_INTERRUPT, (interrupt_handler_t *)kbd_interrupt, NULL);
return (1);
}
else {
} else {
printf("%s\n",result);
return (-1);
}
@ -328,13 +327,13 @@ void handle_keyboard_event(unsigned char scancode)
if (!(((scancode & 0x7F) == 0x38) || /* the right ctrl key */
((scancode & 0x7F) == 0x1D) || /* the right alt key */
((scancode & 0x7F) == 0x35) || /* the right '/' key */
((scancode&0x7F)==0x1C) )) /* the right enter key */
((scancode & 0x7F) == 0x1C)))
/* the right enter key */
/* we swallow unknown e0 codes */
return;
}
/* special cntrl keys */
switch(scancode)
{
switch (scancode) {
case 0x2A:
case 0x36: /* shift pressed */
shift = 1;
@ -583,8 +582,7 @@ char * kbd_initialize(void)
status = kbd_wait_for_input();
if (status == KBD_REPLY_ACK)
break;
if (status != KBD_REPLY_RESEND)
{
if (status != KBD_REPLY_RESEND) {
PRINTF("status: %X\n",status);
return "Kbd: reset failed, no ACK";
}

62
board/pcippc2/cpc710_init_ram.c
View File

@ -28,8 +28,7 @@
#include "pcippc2.h"
#include "i2c.h"
typedef struct cpc710_mem_org_s
{
typedef struct cpc710_mem_org_s {
u8 rows;
u8 cols;
u8 banks2;
@ -37,15 +36,11 @@ typedef struct cpc710_mem_org_s
} cpc710_mem_org_t;
static int cpc710_compute_mcer (u32 * mcer,
unsigned long *
size,
unsigned int sdram);
unsigned long *size, unsigned int sdram);
static int cpc710_eeprom_checksum (unsigned int sdram);
static u8 cpc710_eeprom_read (unsigned int sdram,
unsigned int offset);
static u8 cpc710_eeprom_read (unsigned int sdram, unsigned int offset);
static u32 cpc710_mcer_mem [] =
{
static u32 cpc710_mcer_mem[] = {
0x000003f3, /* 18 lines, 4 Mb */
0x000003e3, /* 19 lines, 8 Mb */
0x000003c3, /* 20 lines, 16 Mb */
@ -56,8 +51,7 @@ static u32 cpc710_mcer_mem [] =
0x00000002, /* 25 lines, 512 Mb */
0x00000001 /* 26 lines, 1024 Mb */
};
static cpc710_mem_org_t cpc710_mem_org [] =
{
static cpc710_mem_org_t cpc710_mem_org[] = {
{0x0c, 0x09, 0x02, 0x00}, /* 0000: 12/ 9/2 */
{0x0d, 0x09, 0x02, 0x00}, /* 0000: 13/ 9/2 */
{0x0d, 0x0a, 0x02, 0x00}, /* 0000: 13/10/2 */
@ -108,8 +102,7 @@ unsigned long cpc710_ram_init (void)
/* Only the first memory bank is initialised now
*/
if (! cpc710_compute_mcer(& mcer, & bank_size, 0))
{
if (!cpc710_compute_mcer (&mcer, &bank_size, 0)) {
puts ("Unsupported SDRAM type !\n");
hang ();
}
@ -128,8 +121,7 @@ unsigned long cpc710_ram_init (void)
/* Wait until initialisation finished
*/
while (! (in32 (REG(SDRAM0, MCCR)) & 0x20000000))
{
while (!(in32 (REG (SDRAM0, MCCR)) & 0x20000000)) {
iobarrier_rw ();
}
@ -150,10 +142,7 @@ unsigned long cpc710_ram_init (void)
return memsize;
}
static int cpc710_compute_mcer (
u32 * mcer,
unsigned long * size,
unsigned int sdram)
static int cpc710_compute_mcer (u32 * mcer, unsigned long *size, unsigned int sdram)
{
u8 rows;
u8 cols;
@ -163,15 +152,12 @@ static int cpc710_compute_mcer (
unsigned int i;
cpc710_mem_org_t *org = 0;
if (! i2c_reset())
{
if (!i2c_reset ()) {
puts ("Can't reset I2C!\n");
hang ();
}
if (! cpc710_eeprom_checksum(sdram))
{
if (!cpc710_eeprom_checksum (sdram)) {
puts ("Invalid EEPROM checksum !\n");
hang ();
}
@ -184,30 +170,27 @@ static int cpc710_compute_mcer (
lines = rows + cols + banks2;
if (lines < 18 || lines > 26)
{
if (lines < 18 || lines > 26) {
/* Unsupported configuration
*/
return 0;
}
mc |= cpc710_mcer_mem[lines - 18] << 6;
for (i = 0; i < sizeof(cpc710_mem_org) / sizeof(cpc710_mem_org_t); i++)
{
for (i = 0; i < sizeof (cpc710_mem_org) / sizeof (cpc710_mem_org_t);
i++) {
cpc710_mem_org_t *corg = cpc710_mem_org + i;
if (corg->rows == rows && corg->cols == cols && corg->banks2 == banks2)
{
if (corg->rows == rows && corg->cols == cols
&& corg->banks2 == banks2) {
org = corg;
break;
}
}
if (! org)
{
if (!org) {
/* Unsupported configuration
*/
return 0;
@ -223,29 +206,24 @@ static int cpc710_compute_mcer (
return 1;
}
static int cpc710_eeprom_checksum (
unsigned int sdram)
static int cpc710_eeprom_checksum (unsigned int sdram)
{
u8 sum = 0;
unsigned int i;
for (i = 0; i < 63; i++)
{
for (i = 0; i < 63; i++) {
sum += cpc710_eeprom_read (sdram, i);
}
return sum == cpc710_eeprom_read (sdram, 63);
}
static u8 cpc710_eeprom_read (
unsigned int sdram,
unsigned int offset)
static u8 cpc710_eeprom_read (unsigned int sdram, unsigned int offset)
{
u8 dev = (sdram << 1) | 0xa0;
u8 data;
if (! i2c_read_byte(& data, dev,offset))
{
if (!i2c_read_byte (&data, dev, offset)) {
puts ("I2C error !\n");
hang ();
}

3
board/pcippc2/sconsole.h
View File

@ -26,8 +26,7 @@
#include <config.h>
typedef struct sconsole_buffer_s
{
typedef struct sconsole_buffer_s {
unsigned long size;
unsigned long max_size;
unsigned long pos;

3
board/purple/purple.c
View File

@ -184,8 +184,7 @@ static void copydwords (ulong *source, ulong *destination, ulong nlongs)
ulong temp,temp1;
ulong *dstend = destination + nlongs;
while (destination < dstend)
{
while (destination < dstend) {
temp = *source++;
/* dummy read from sdram */
temp1 = *(ulong *)0xa0000000;

3
board/purple/sconsole.h
View File

@ -26,8 +26,7 @@
#include <config.h>
typedef struct sconsole_buffer_s
{
typedef struct sconsole_buffer_s {
unsigned long size;
unsigned long max_size;
unsigned long pos;

1
board/quantum/fpga.h
View File

@ -31,4 +31,3 @@ int fpga_boot(unsigned char *fpgadata, int size);
#define ERROR_FPGA_PRG_INIT_LOW -1 /* Timeout after PRG* asserted */
#define ERROR_FPGA_PRG_INIT_HIGH -2 /* Timeout after PRG* deasserted */
#define ERROR_FPGA_PRG_DONE -3 /* Timeout after programming */
/* vim: set ts=4 sw=4 tw=78: */

39
board/snmc/qs860t/flash.c
View File

@ -79,8 +79,7 @@ unsigned long flash_init (void)
}
/* Only one bank */
if (CFG_MAX_FLASH_BANKS == 1)
{
if (CFG_MAX_FLASH_BANKS == 1) {
/* Setup offsets */
flash_get_offsets (FLASH_BASE1_PRELIM, &flash_info[0]);
@ -98,15 +97,11 @@ unsigned long flash_init (void)
#endif
size_b1 = 0 ;
flash_info[0].size = size_b0;
}
/* 2 banks */
else
{
} else { /* 2 banks */
size_b1 = flash_get_size((volatile FLASH_WORD_SIZE *)FLASH_BASE1_PRELIM, &flash_info[1]);
/* Re-do sizing to get full correct info */
if (size_b1)
{
if (size_b1) {
mtdcr(ebccfga, pb0cr);
pbcr = mfdcr(ebccfgd);
mtdcr(ebccfga, pb0cr);
@ -115,8 +110,7 @@ unsigned long flash_init (void)
mtdcr(ebccfgd, pbcr);
}
if (size_b0)
{
if (size_b0) {
mtdcr(ebccfga, pb1cr);
pbcr = mfdcr(ebccfgd);
mtdcr(ebccfga, pb1cr);
@ -616,7 +610,8 @@ ulong flash_get_size (volatile FLASH_WORD_SIZE *addr, flash_info_t *info)
int flash_erase (flash_info_t * info, int s_first, int s_last)
{
volatile FLASH_WORD_SIZE *addr=(volatile FLASH_WORD_SIZE*)(info->start[0]);
volatile FLASH_WORD_SIZE *addr =
(volatile FLASH_WORD_SIZE *) (info->start[0]);
int flag, prot, sect, l_sect, barf;
ulong start, now, last;
int rcode = 0;
@ -645,8 +640,7 @@ int flash_erase (flash_info_t *info, int s_first, int s_last)
}
if (prot) {
printf ("- Warning: %d protected sectors will not be erased!\n",
prot);
printf ("- Warning: %d protected sectors will not be erased!\n", prot);
} else {
printf ("\n");
}
@ -695,8 +689,7 @@ int flash_erase (flash_info_t *info, int s_first, int s_last)
last = start;
addr = (volatile FLASH_WORD_SIZE *) (info->start[l_sect]);
while ((addr[0] & (0x00800080 & FLASH_ID_MASK)) !=
(0x00800080&FLASH_ID_MASK) )
{
(0x00800080 & FLASH_ID_MASK)) {
if ((now = get_timer (start)) > CFG_FLASH_ERASE_TOUT) {
printf ("Timeout\n");
return 1;
@ -740,15 +733,19 @@ DONE:
barf = addr[0] & 0x003A;
#endif
if (barf) {
printf("\nFlash error in sector at %lx\n",(unsigned long)addr);
if(barf & 0x0002) printf("Block locked, not erased.\n");
printf ("\nFlash error in sector at %lx\n",
(unsigned long) addr);
if (barf & 0x0002)
printf ("Block locked, not erased.\n");
if ((barf & 0x0030) == 0x0030)
printf ("Command Sequence error.\n");
if ((barf & 0x0030) == 0x0020)
printf ("Block Erase error.\n");
if(barf & 0x0008) printf("Vpp Low error.\n");
if (barf & 0x0008)
printf ("Vpp Low error.\n");
rcode = 1;
} else printf(".");
} else
printf (".");
l_sect = sect;
}
addr = (volatile FLASH_WORD_SIZE *) info->start[0];
@ -1113,8 +1110,6 @@ static int write_short (flash_info_t *info, ulong dest, ushort data)
return (0);
}
#endif
/*-----------------------------------------------------------------------
*/
/*-----------------------------------------------------------------------*/

53
board/socrates/Makefile Normal file
View File

@ -0,0 +1,53 @@
#
# (C) Copyright 2008
# Sergei Poselenov, Emcraft Systems, sposelenov@emcraft.com.
# (C) Copyright 2001-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
include $(TOPDIR)/config.mk
LIB = $(obj)lib$(BOARD).a
#
COBJS := $(BOARD).o law.o tlb.o sdram.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS) $(SOBJS)
$(AR) $(ARFLAGS) $@ $(OBJS)
clean:
rm -f $(OBJS) $(SOBJS)
distclean: clean
rm -f $(LIB) core *.bak .depend
#########################################################################
# defines $(obj).depend target
include $(SRCTREE)/rules.mk
sinclude $(obj).depend
#########################################################################

30
board/socrates/config.mk Normal file
View File

@ -0,0 +1,30 @@
# Copyright 2004 Freescale Semiconductor.
#
# Modified by Sergei Poselenov
# (C) Copyright 2008, Emcraft Systems.
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
#
# socrates board
# default CCARBAR is at 0xff700000
# assume U-Boot is less than 256k
#
TEXT_BASE = 0xfffc0000

57
board/socrates/law.c Normal file
View File

@ -0,0 +1,57 @@
/*
* (C) Copyright 2008
* Sergei Poselenov, Emcraft Systems, sposelenov@emcraft.com.
*
* Copyright 2008 Freescale Semiconductor, Inc.
*
* (C) Copyright 2000
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <asm/fsl_law.h>
#include <asm/mmu.h>
/*
* LAW(Local Access Window) configuration:
*
* 0x0000_0000 0x7fff_ffff DDR 2G
* 0x8000_0000 0x9fff_ffff PCI1 MEM 512M
* 0xc000_0000 0xdfff_ffff RapidIO 512M
* 0xe000_0000 0xe000_ffff CCSR 1M
* 0xe200_0000 0xe2ff_ffff PCI1 IO 16M
* 0xf800_0000 0xf80f_ffff BCSR 1M
* 0xfe00_0000 0xffff_ffff FLASH (boot bank) 32M
*
* Notes:
* CCSRBAR and L2-as-SRAM don't need a configured Local Access Window.
* If flash is 8M at default position (last 8M), no LAW needed.
*/
struct law_entry law_table[] = {
SET_LAW_ENTRY(1, CFG_DDR_SDRAM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_DDR),
SET_LAW_ENTRY(2, CFG_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI),
SET_LAW_ENTRY(3, CFG_LBC_FLASH_BASE, LAW_SIZE_128M, LAW_TRGT_IF_LBC),
SET_LAW_ENTRY(4, CFG_PCI1_IO_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_PCI),
SET_LAW_ENTRY(5, CFG_RIO_MEM_BASE, LAWAR_SIZE_512M, LAW_TRGT_IF_RIO),
};
int num_law_entries = ARRAY_SIZE(law_table);

122
board/socrates/sdram.c Normal file
View File

@ -0,0 +1,122 @@
/*
* (C) Copyright 2008
* Sergei Poselenov, Emcraft Systems, sposelenov@emcraft.com.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <asm/processor.h>
#include <asm/immap_85xx.h>
#include <asm/processor.h>
#include <asm/mmu.h>
#include <spd_sdram.h>
#if !defined(CONFIG_SPD_EEPROM)
/*
* Autodetect onboard DDR SDRAM on 85xx platforms
*
* NOTE: Some of the hardcoded values are hardware dependant,
* so this should be extended for other future boards
* using this routine!
*/
long int sdram_setup(int casl)
{
volatile ccsr_ddr_t *ddr = (void *)(CFG_MPC85xx_DDR_ADDR);
/*
* Disable memory controller.
*/
ddr->cs0_config = 0;
ddr->sdram_cfg = 0;
ddr->cs0_bnds = CFG_DDR_CS0_BNDS;
ddr->cs0_config = CFG_DDR_CS0_CONFIG;
ddr->timing_cfg_0 = CFG_DDR_TIMING_0;
ddr->timing_cfg_1 = CFG_DDR_TIMING_1;
ddr->timing_cfg_2 = CFG_DDR_TIMING_2;
ddr->sdram_mode = CFG_DDR_MODE;
ddr->sdram_interval = CFG_DDR_INTERVAL;
ddr->sdram_cfg_2 = CFG_DDR_CONFIG_2;
ddr->sdram_clk_cntl = CFG_DDR_CLK_CONTROL;
asm ("sync;isync;msync");
udelay(1000);
ddr->sdram_cfg = CFG_DDR_CONFIG;
asm ("sync; isync; msync");
udelay(1000);
if (get_ram_size(0, CFG_SDRAM_SIZE<<20) == CFG_SDRAM_SIZE<<20) {
/*
* OK, size detected -> all done
*/
return CFG_SDRAM_SIZE<<20;
}
return 0; /* nothing found ! */
}
#endif
long int initdram (int board_type)
{
long dram_size = 0;
#if defined(CONFIG_SPD_EEPROM)
dram_size = spd_sdram ();
#else
dram_size = sdram_setup(CONFIG_DDR_DEFAULT_CL);
#endif
return dram_size;
}
#if defined(CFG_DRAM_TEST)
int testdram (void)
{
uint *pstart = (uint *) CFG_MEMTEST_START;
uint *pend = (uint *) CFG_MEMTEST_END;
uint *p;
printf ("SDRAM test phase 1:\n");
for (p = pstart; p < pend; p++)
*p = 0xaaaaaaaa;
for (p = pstart; p < pend; p++) {
if (*p != 0xaaaaaaaa) {
printf ("SDRAM test fails at: %08x\n", (uint) p);
return 1;
}
}
printf ("SDRAM test phase 2:\n");
for (p = pstart; p < pend; p++)
*p = 0x55555555;
for (p = pstart; p < pend; p++) {
if (*p != 0x55555555) {
printf ("SDRAM test fails at: %08x\n", (uint) p);
return 1;
}
}
printf ("SDRAM test passed.\n");
return 0;
}
#endif

211
board/socrates/socrates.c Normal file
View File

@ -0,0 +1,211 @@
/*
* (C) Copyright 2008
* Sergei Poselenov, Emcraft Systems, sposelenov@emcraft.com.
*
* Copyright 2004 Freescale Semiconductor.
* (C) Copyright 2002,2003, Motorola Inc.
* Xianghua Xiao, (X.Xiao@motorola.com)
*
* (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <pci.h>
#include <asm/processor.h>
#include <asm/immap_85xx.h>
#include <ioports.h>
#include <flash.h>
#include <libfdt.h>
#include <fdt_support.h>
DECLARE_GLOBAL_DATA_PTR;
extern flash_info_t flash_info[]; /* FLASH chips info */
void local_bus_init (void);
ulong flash_get_size (ulong base, int banknum);
int checkboard (void)
{
char *s = getenv("serial#");
puts("Board: Socrates");
if (s != NULL) {
puts(", serial# ");
puts(s);
}
putc('\n');
#ifdef CONFIG_PCI
printf ("PCI1: 32 bit, %d MHz (compiled)\n",
CONFIG_SYS_CLK_FREQ / 1000000);
#else
printf ("PCI1: disabled\n");
#endif
/*
* Initialize local bus.
*/
local_bus_init ();
return 0;
}
int misc_init_r (void)
{
volatile ccsr_lbc_t *memctl = (void *)(CFG_MPC85xx_LBC_ADDR);
/*
* Adjust flash start and offset to detected values
*/
gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
gd->bd->bi_flashoffset = 0;
/*
* Check if boot FLASH isn't max size
*/
if (gd->bd->bi_flashsize < (0 - CFG_FLASH0)) {
memctl->or0 = gd->bd->bi_flashstart | (CFG_OR0_PRELIM & 0x00007fff);
memctl->br0 = gd->bd->bi_flashstart | (CFG_BR0_PRELIM & 0x00007fff);
/*
* Re-check to get correct base address
*/
flash_get_size(gd->bd->bi_flashstart, CFG_MAX_FLASH_BANKS - 1);
}
/*
* Check if only one FLASH bank is available
*/
if (gd->bd->bi_flashsize != CFG_MAX_FLASH_BANKS * (0 - CFG_FLASH0)) {
memctl->or1 = 0;
memctl->br1 = 0;
/*
* Re-do flash protection upon new addresses
*/
flash_protect (FLAG_PROTECT_CLEAR,
gd->bd->bi_flashstart, 0xffffffff,
&flash_info[CFG_MAX_FLASH_BANKS - 1]);
/* Monitor protection ON by default */
flash_protect (FLAG_PROTECT_SET,
CFG_MONITOR_BASE, CFG_MONITOR_BASE + monitor_flash_len - 1,
&flash_info[CFG_MAX_FLASH_BANKS - 1]);
/* Environment protection ON by default */
flash_protect (FLAG_PROTECT_SET,
CFG_ENV_ADDR,
CFG_ENV_ADDR + CFG_ENV_SECT_SIZE - 1,
&flash_info[CFG_MAX_FLASH_BANKS - 1]);
/* Redundant environment protection ON by default */
flash_protect (FLAG_PROTECT_SET,
CFG_ENV_ADDR_REDUND,
CFG_ENV_ADDR_REDUND + CFG_ENV_SIZE_REDUND - 1,
&flash_info[CFG_MAX_FLASH_BANKS - 1]);
}
return 0;
}
/*
* Initialize Local Bus
*/
void local_bus_init (void)
{
volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR);
volatile ccsr_local_ecm_t *ecm = (void *)(CFG_MPC85xx_ECM_ADDR);
lbc->ltesr = 0xffffffff; /* Clear LBC error interrupts */
lbc->lteir = 0xffffffff; /* Enable LBC error interrupts */
ecm->eedr = 0xffffffff; /* Clear ecm errors */
ecm->eeer = 0xffffffff; /* Enable ecm errors */
}
#if defined(CONFIG_PCI)
/*
* Initialize PCI Devices, report devices found.
*/
#ifndef CONFIG_PCI_PNP
static struct pci_config_table pci_mpc85xxads_config_table[] = {
{PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
PCI_IDSEL_NUMBER, PCI_ANY_ID,
pci_cfgfunc_config_device, {PCI_ENET0_IOADDR,
PCI_ENET0_MEMADDR,
PCI_COMMAND_MEMORY |
PCI_COMMAND_MASTER}},
{}
};
#endif
static struct pci_controller hose = {
#ifndef CONFIG_PCI_PNP
config_table:pci_mpc85xxads_config_table,
#endif
};
#endif /* CONFIG_PCI */
void pci_init_board (void)
{
#ifdef CONFIG_PCI
pci_mpc85xx_init (&hose);
#endif /* CONFIG_PCI */
}
#ifdef CONFIG_BOARD_EARLY_INIT_R
int board_early_init_r (void)
{
#ifdef CONFIG_PS2MULT
ps2mult_early_init();
#endif /* CONFIG_PS2MULT */
return (0);
}
#endif /* CONFIG_BOARD_EARLY_INIT_R */
#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
void
ft_board_setup(void *blob, bd_t *bd)
{
u32 val[4];
int rc;
ft_cpu_setup(blob, bd);
/* Fixup NOR mapping */
val[0] = 0; /* chip select number */
val[1] = 0; /* always 0 */
val[2] = gd->bd->bi_flashstart;
val[3] = gd->bd->bi_flashsize;
rc = fdt_find_and_setprop(blob, "/localbus", "ranges",
val, sizeof(val), 1);
if (rc)
printf("Unable to update property NOR mapping, err=%s\n",
fdt_strerror(rc));
}
#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */

117
board/socrates/tlb.c Normal file
View File

@ -0,0 +1,117 @@
/*
* (C) Copyright 2008
* Sergei Poselenov, Emcraft Systems, sposelenov@emcraft.com.
*
* Copyright 2008 Freescale Semiconductor, Inc.
*
* (C) Copyright 2000
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <asm/mmu.h>
struct fsl_e_tlb_entry tlb_table[] = {
/* TLB 0 - for temp stack in cache */
SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR, CFG_INIT_RAM_ADDR,
MAS3_SX|MAS3_SW|MAS3_SR, 0,
0, 0, BOOKE_PAGESZ_4K, 0),
SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + 4 * 1024 , CFG_INIT_RAM_ADDR + 4 * 1024,
MAS3_SX|MAS3_SW|MAS3_SR, 0,
0, 0, BOOKE_PAGESZ_4K, 0),
SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + 8 * 1024 , CFG_INIT_RAM_ADDR + 8 * 1024,
MAS3_SX|MAS3_SW|MAS3_SR, 0,
0, 0, BOOKE_PAGESZ_4K, 0),
SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + 12 * 1024 , CFG_INIT_RAM_ADDR + 12 * 1024,
MAS3_SX|MAS3_SW|MAS3_SR, 0,
0, 0, BOOKE_PAGESZ_4K, 0),
/*
* TLB 0, 1: 128M Non-cacheable, guarded
* 0xf8000000 128M FLASH
* Out of reset this entry is only 4K.
*/
SET_TLB_ENTRY(1, CFG_FLASH_BASE, CFG_FLASH_BASE,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 1, BOOKE_PAGESZ_64M, 1),
SET_TLB_ENTRY(1, CFG_FLASH_BASE + 0x4000000, CFG_FLASH_BASE + 0x4000000,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 0, BOOKE_PAGESZ_64M, 1),
/*
* TLB 2: 256M Non-cacheable, guarded
* 0x80000000 256M PCI1 MEM First half
*/
SET_TLB_ENTRY(1, CFG_PCI1_MEM_PHYS, CFG_PCI1_MEM_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 2, BOOKE_PAGESZ_256M, 1),
/*
* TLB 3: 256M Non-cacheable, guarded
* 0x90000000 256M PCI1 MEM Second half
*/
SET_TLB_ENTRY(1, CFG_PCI1_MEM_PHYS + 0x10000000, CFG_PCI1_MEM_PHYS + 0x10000000,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 3, BOOKE_PAGESZ_256M, 1),
/*
* TLB 4: 256M Non-cacheable, guarded
* 0xc0000000 256M Rapid IO MEM First half
*/
SET_TLB_ENTRY(1, CFG_RIO_MEM_BASE, CFG_RIO_MEM_BASE,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 4, BOOKE_PAGESZ_256M, 1),
/*
* TLB 5: 256M Non-cacheable, guarded
* 0xd0000000 256M Rapid IO MEM Second half
*/
SET_TLB_ENTRY(1, CFG_RIO_MEM_BASE + 0x10000000, CFG_RIO_MEM_BASE + 0x10000000,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 5, BOOKE_PAGESZ_256M, 1),
/*
* TLB 6: 64M Non-cacheable, guarded
* 0xe000_0000 1M CCSRBAR
* 0xe200_0000 16M PCI1 IO
*/
SET_TLB_ENTRY(1, CFG_CCSRBAR, CFG_CCSRBAR_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 6, BOOKE_PAGESZ_64M, 1),
/*
* TLB 7+8: 512M DDR, cache disabled (needed for memory test)
* 0x00000000 512M DDR System memory
* Without SPD EEPROM configured DDR, this must be setup manually.
* Make sure the TLB count at the top of this table is correct.
* Likely it needs to be increased by two for these entries.
*/
SET_TLB_ENTRY(1, CFG_DDR_SDRAM_BASE, CFG_DDR_SDRAM_BASE,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 7, BOOKE_PAGESZ_256M, 1),
SET_TLB_ENTRY(1, CFG_DDR_SDRAM_BASE + 0x10000000, CFG_DDR_SDRAM_BASE + 0x10000000,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 8, BOOKE_PAGESZ_256M, 1),
};
int num_tlb_entries = ARRAY_SIZE(tlb_table);

150
board/socrates/u-boot.lds Normal file
View File

@ -0,0 +1,150 @@
/*
* (C) Copyright 2008
* Sergei Poselenov, Emcraft Systems, sposelenov@emcraft.com.
*
* (C) Copyright 2002,2003, Motorola,Inc.
* Xianghua Xiao, X.Xiao@motorola.com.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
OUTPUT_ARCH(powerpc)
/* Do we need any of these for elf?
__DYNAMIC = 0; */
SECTIONS
{
.resetvec 0xFFFFFFFC :
{
*(.resetvec)
} = 0xffff
.bootpg 0xFFFFF000 :
{
cpu/mpc85xx/start.o (.bootpg)
} = 0xffff
/* Read-only sections, merged into text segment: */
. = + SIZEOF_HEADERS;
.interp : { *(.interp) }
.hash : { *(.hash) }
.dynsym : { *(.dynsym) }
.dynstr : { *(.dynstr) }
.rel.text : { *(.rel.text) }
.rela.text : { *(.rela.text) }
.rel.data : { *(.rel.data) }
.rela.data : { *(.rela.data) }
.rel.rodata : { *(.rel.rodata) }
.rela.rodata : { *(.rela.rodata) }
.rel.got : { *(.rel.got) }
.rela.got : { *(.rela.got) }
.rel.ctors : { *(.rel.ctors) }
.rela.ctors : { *(.rela.ctors) }
.rel.dtors : { *(.rel.dtors) }
.rela.dtors : { *(.rela.dtors) }
.rel.bss : { *(.rel.bss) }
.rela.bss : { *(.rela.bss) }
.rel.plt : { *(.rel.plt) }
.rela.plt : { *(.rela.plt) }
.init : { *(.init) }
.plt : { *(.plt) }
.text :
{
cpu/mpc85xx/start.o (.text)
cpu/mpc85xx/traps.o (.text)
cpu/mpc85xx/interrupts.o (.text)
cpu/mpc85xx/cpu_init.o (.text)
cpu/mpc85xx/cpu.o (.text)
cpu/mpc85xx/speed.o (.text)
cpu/mpc85xx/pci.o (.text)
common/dlmalloc.o (.text)
lib_generic/crc32.o (.text)
lib_ppc/extable.o (.text)
lib_generic/zlib.o (.text)
*(.text)
*(.fixup)
*(.got1)
}
_etext = .;
PROVIDE (etext = .);
.rodata :
{
*(.rodata)
*(.rodata1)
*(.rodata.str1.4)
*(.eh_frame)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
.dtors : { *(.dtors) }
/* Read-write section, merged into data segment: */
. = (. + 0x00FF) & 0xFFFFFF00;
_erotext = .;
PROVIDE (erotext = .);
.reloc :
{
*(.got)
_GOT2_TABLE_ = .;
*(.got2)
_FIXUP_TABLE_ = .;
*(.fixup)
}
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2;
__fixup_entries = (. - _FIXUP_TABLE_) >> 2;
.data :
{
*(.data)
*(.data1)
*(.sdata)
*(.sdata2)
*(.dynamic)
CONSTRUCTORS
}
_edata = .;
PROVIDE (edata = .);
. = .;
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
. = .;
__start___ex_table = .;
__ex_table : { *(__ex_table) }
__stop___ex_table = .;
. = ALIGN(256);
__init_begin = .;
.text.init : { *(.text.init) }
.data.init : { *(.data.init) }
. = ALIGN(256);
__init_end = .;
__bss_start = .;
.bss (NOLOAD) :
{
*(.sbss) *(.scommon)
*(.dynbss)
*(.bss)
*(COMMON)
}
_end = . ;
PROVIDE (end = .);
}

3
board/trab/tsc2000.h
View File

@ -111,8 +111,7 @@
#define TSC2000_DELAY_BASE 500
#define TSC2000_NO_SENSOR -0x10000
#define ERROR_BATTERY 220 /* must be adjusted, if R68 is changed on
* TRAB */
#define ERROR_BATTERY 220 /* must be adjusted, if R68 is changed on TRAB */
void tsc2000_write(unsigned short, unsigned short);
unsigned short tsc2000_read (unsigned short);

4
common/cmd_fdc.c
View File

@ -46,14 +46,12 @@
#define FALSE 0
#endif
/*#if defined(CONFIG_CMD_DATE) */
/*#include <rtc.h> */
/*#endif */
#if defined(CONFIG_CMD_FDC) || defined(CONFIG_CMD_FDOS)
typedef struct {
int flags; /* connected drives ect */
unsigned long blnr; /* Logical block nr */
@ -64,6 +62,7 @@ typedef struct {
uchar result[11]; /* status information */
uchar resultlen; /* lenght of result */
} FDC_COMMAND_STRUCT;
/* flags: only the lower 8bit used:
* bit 0 if set drive 0 is present
* bit 1 if set drive 1 is present
@ -75,7 +74,6 @@ typedef struct {
* bit 7 if set disk in drive 4 is inserted
*/
/* cmd indexes */
#define COMMAND 0
#define DRIVE 1

4
common/cmd_log.c
View File

@ -107,7 +107,7 @@ void logbuff_init_ptrs (void)
if ((s = getenv ("loglevel")) != NULL)
console_loglevel = (int)simple_strtoul (s, NULL, 10);
gd->post_log_word |= LOGBUFF_INITIALIZED;
gd->flags |= GD_FLG_LOGINIT;
}
void logbuff_reset (void)
@ -168,7 +168,7 @@ static void logbuff_puts (const char *s)
void logbuff_log(char *msg)
{
if ((gd->post_log_word & LOGBUFF_INITIALIZED)) {
if ((gd->flags & GD_FLG_LOGINIT)) {
logbuff_printk (msg);
} else {
/* Can happen only for pre-relocated errors as logging */

4
common/command.c
View File

@ -196,9 +196,7 @@ do_test (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
expr = !expr;
#if 0
printf(": returns %d\n", expr);
#endif
debug (": returns %d\n", expr);
return expr;
}

1
common/hush.c
View File

@ -1,4 +1,3 @@
/* vi: set sw=4 ts=4: */
/*
* sh.c -- a prototype Bourne shell grammar parser
* Intended to follow the original Thompson and Ritchie

44
common/usb.c
View File

@ -48,6 +48,7 @@
#include <command.h>
#include <asm/processor.h>
#include <linux/ctype.h>
#include <asm/byteorder.h>
#if defined(CONFIG_CMD_USB)
@ -177,10 +178,10 @@ int usb_control_msg(struct usb_device *dev, unsigned int pipe,
/* set setup command */
setup_packet.requesttype = requesttype;
setup_packet.request = request;
setup_packet.value = swap_16(value);
setup_packet.index = swap_16(index);
setup_packet.length = swap_16(size);
USB_PRINTF("usb_control_msg: request: 0x%X, requesttype: 0x%X\nvalue 0x%X index 0x%X length 0x%X\n",
setup_packet.value = cpu_to_le16(value);
setup_packet.index = cpu_to_le16(index);
setup_packet.length = cpu_to_le16(size);
USB_PRINTF("usb_control_msg: request: 0x%X, requesttype: 0x%X, value 0x%X index 0x%X length 0x%X\n",
request,requesttype,value,index,size);
dev->status=USB_ST_NOT_PROC; /*not yet processed */
@ -300,7 +301,7 @@ int usb_parse_config(struct usb_device *dev, unsigned char *buffer, int cfgno)
return -1;
}
memcpy(&dev->config, buffer, buffer[0]);
dev->config.wTotalLength = swap_16(dev->config.wTotalLength);
le16_to_cpus(&(dev->config.wTotalLength));
dev->config.no_of_if = 0;
index = dev->config.bLength;
@ -329,8 +330,7 @@ int usb_parse_config(struct usb_device *dev, unsigned char *buffer, int cfgno)
dev->config.if_desc[ifno].no_of_ep++; /* found an endpoint */
memcpy(&dev->config.if_desc[ifno].ep_desc[epno],
&buffer[index], buffer[index]);
dev->config.if_desc[ifno].ep_desc[epno].wMaxPacketSize =
swap_16(dev->config.if_desc[ifno].ep_desc[epno].wMaxPacketSize);
le16_to_cpus(&(dev->config.if_desc[ifno].ep_desc[epno].wMaxPacketSize));
USB_PRINTF("if %d, ep %d\n", ifno, epno);
break;
default:
@ -413,7 +413,7 @@ int usb_get_configuration_no(struct usb_device *dev,unsigned char *buffer,int cf
printf("config descriptor too short (expected %i, got %i)\n",8,result);
return -1;
}
tmp=swap_16(config->wTotalLength);
tmp = le16_to_cpu(config->wTotalLength);
if (tmp > USB_BUFSIZ) {
USB_PRINTF("usb_get_configuration_no: failed to get descriptor - too long: %d\n",
@ -816,10 +816,10 @@ int usb_new_device(struct usb_device *dev)
return 1;
}
/* correct le values */
dev->descriptor.bcdUSB=swap_16(dev->descriptor.bcdUSB);
dev->descriptor.idVendor=swap_16(dev->descriptor.idVendor);
dev->descriptor.idProduct=swap_16(dev->descriptor.idProduct);
dev->descriptor.bcdDevice=swap_16(dev->descriptor.bcdDevice);
le16_to_cpus(&dev->descriptor.bcdUSB);
le16_to_cpus(&dev->descriptor.idVendor);
le16_to_cpus(&dev->descriptor.idProduct);
le16_to_cpus(&dev->descriptor.bcdDevice);
/* only support for one config for now */
usb_get_configuration_no(dev,&tmpbuf[0],0);
usb_parse_config(dev,&tmpbuf[0],0);
@ -979,8 +979,8 @@ static int hub_port_reset(struct usb_device *dev, int port,
USB_HUB_PRINTF("get_port_status failed status %lX\n",dev->status);
return -1;
}
portstatus = swap_16(portsts.wPortStatus);
portchange = swap_16(portsts.wPortChange);
portstatus = le16_to_cpu(portsts.wPortStatus);
portchange = le16_to_cpu(portsts.wPortChange);
USB_HUB_PRINTF("portstatus %x, change %x, %s\n", portstatus ,portchange,
portstatus&(1<<USB_PORT_FEAT_LOWSPEED) ? "Low Speed" : "High Speed");
USB_HUB_PRINTF("STAT_C_CONNECTION = %d STAT_CONNECTION = %d USB_PORT_STAT_ENABLE %d\n",
@ -1024,8 +1024,8 @@ void usb_hub_port_connect_change(struct usb_device *dev, int port)
return;
}
portstatus = swap_16(portsts.wPortStatus);
portchange = swap_16(portsts.wPortChange);
portstatus = le16_to_cpu(portsts.wPortStatus);
portchange = le16_to_cpu(portsts.wPortChange);
USB_HUB_PRINTF("portstatus %x, change %x, %s\n", portstatus, portchange,
portstatus&(1<<USB_PORT_FEAT_LOWSPEED) ? "Low Speed" : "High Speed");
@ -1099,7 +1099,7 @@ int usb_hub_configure(struct usb_device *dev)
}
memcpy((unsigned char *)&hub->desc,buffer,descriptor->bLength);
/* adjust 16bit values */
hub->desc.wHubCharacteristics=swap_16(descriptor->wHubCharacteristics);
hub->desc.wHubCharacteristics = le16_to_cpu(descriptor->wHubCharacteristics);
/* set the bitmap */
bitmap=(unsigned char *)&hub->desc.DeviceRemovable[0];
memset(bitmap,0xff,(USB_MAXCHILDREN+1+7)/8); /* devices not removable by default */
@ -1161,11 +1161,11 @@ int usb_hub_configure(struct usb_device *dev)
}
hubsts = (struct usb_hub_status *)buffer;
USB_HUB_PRINTF("get_hub_status returned status %X, change %X\n",
swap_16(hubsts->wHubStatus),swap_16(hubsts->wHubChange));
le16_to_cpu(hubsts->wHubStatus),le16_to_cpu(hubsts->wHubChange));
USB_HUB_PRINTF("local power source is %s\n",
(swap_16(hubsts->wHubStatus) & HUB_STATUS_LOCAL_POWER) ? "lost (inactive)" : "good");
(le16_to_cpu(hubsts->wHubStatus) & HUB_STATUS_LOCAL_POWER) ? "lost (inactive)" : "good");
USB_HUB_PRINTF("%sover-current condition exists\n",
(swap_16(hubsts->wHubStatus) & HUB_STATUS_OVERCURRENT) ? "" : "no ");
(le16_to_cpu(hubsts->wHubStatus) & HUB_STATUS_OVERCURRENT) ? "" : "no ");
usb_hub_power_on(hub);
for (i = 0; i < dev->maxchild; i++) {
struct usb_port_status portsts;
@ -1175,8 +1175,8 @@ int usb_hub_configure(struct usb_device *dev)
USB_HUB_PRINTF("get_port_status failed\n");
continue;
}
portstatus = swap_16(portsts.wPortStatus);
portchange = swap_16(portsts.wPortChange);
portstatus = le16_to_cpu(portsts.wPortStatus);
portchange = le16_to_cpu(portsts.wPortChange);
USB_HUB_PRINTF("Port %d Status %X Change %X\n",i+1,portstatus,portchange);
if (portchange & USB_PORT_STAT_C_CONNECTION) {
USB_HUB_PRINTF("port %d connection change\n", i + 1);

11
common/usb_kbd.c
View File

@ -26,6 +26,7 @@
*/
#include <common.h>
#include <devices.h>
#include <asm/byteorder.h>
#ifdef CONFIG_USB_KEYBOARD
@ -475,14 +476,14 @@ static int fetch_item(unsigned char *start,unsigned char *end, struct hid_item *
break;
case 2:
if ((end - start) >= 2) {
item->data.u16 = swap_16((unsigned short *)start);
item->data.u16 = le16_to_cpu((unsigned short *)start);
start+=2;
return item->size;
}
case 3:
item->size++;
if ((end - start) >= 4) {
item->data.u32 = swap_32((unsigned long *)start);
item->data.u32 = le32_to_cpu((unsigned long *)start);
start+=4;
return item->size;
}
@ -705,15 +706,15 @@ static int usb_kbd_get_hid_desc(struct usb_device *dev)
}
index=head->bLength;
config=(struct usb_config_descriptor *)&buffer[0];
len=swap_16(config->wTotalLength);
len=le16_to_cpu(config->wTotalLength);
/* Ok the first entry must be a configuration entry, now process the others */
head=(struct usb_descriptor_header *)&buffer[index];
while(index+1 < len) {
if(head->bDescriptorType==USB_DT_HID) {
printf("HID desc found\n");
memcpy(&usb_kbd_hid_desc,&buffer[index],buffer[index]);
usb_kbd_hid_desc.bcdHID=swap_16(usb_kbd_hid_desc.bcdHID);
usb_kbd_hid_desc.wDescriptorLength=swap_16(usb_kbd_hid_desc.wDescriptorLength);
le16_to_cpus(&usb_kbd_hid_desc.bcdHID);
le16_to_cpus(&usb_kbd_hid_desc.wDescriptorLength);
usb_kbd_display_hid(&usb_kbd_hid_desc);
len=0;
break;

28
common/usb_storage.c
View File

@ -52,6 +52,7 @@
#include <common.h>
#include <command.h>
#include <asm/byteorder.h>
#include <asm/processor.h>
@ -474,9 +475,9 @@ int usb_stor_BBB_comdat(ccb *srb, struct us_data *us)
/* always OUT to the ep */
pipe = usb_sndbulkpipe(us->pusb_dev, us->ep_out);
cbw.dCBWSignature = swap_32(CBWSIGNATURE);
cbw.dCBWTag = swap_32(CBWTag++);
cbw.dCBWDataTransferLength = swap_32(srb->datalen);
cbw.dCBWSignature = cpu_to_le32(CBWSIGNATURE);
cbw.dCBWTag = cpu_to_le32(CBWTag++);
cbw.dCBWDataTransferLength = cpu_to_le32(srb->datalen);
cbw.bCBWFlags = (dir_in? CBWFLAGS_IN : CBWFLAGS_OUT);
cbw.bCBWLUN = srb->lun;
cbw.bCDBLength = srb->cmdlen;
@ -692,14 +693,14 @@ int usb_stor_BBB_transport(ccb *srb, struct us_data *us)
printf("\n");
#endif
/* misuse pipe to get the residue */
pipe = swap_32(csw.dCSWDataResidue);
pipe = le32_to_cpu(csw.dCSWDataResidue);
if (pipe == 0 && srb->datalen != 0 && srb->datalen - data_actlen != 0)
pipe = srb->datalen - data_actlen;
if (CSWSIGNATURE != swap_32(csw.dCSWSignature)) {
if (CSWSIGNATURE != le32_to_cpu(csw.dCSWSignature)) {
USB_STOR_PRINTF("!CSWSIGNATURE\n");
usb_stor_BBB_reset(us);
return USB_STOR_TRANSPORT_FAILED;
} else if ((CBWTag - 1) != swap_32(csw.dCSWTag)) {
} else if ((CBWTag - 1) != le32_to_cpu(csw.dCSWTag)) {
USB_STOR_PRINTF("!Tag\n");
usb_stor_BBB_reset(us);
return USB_STOR_TRANSPORT_FAILED;
@ -1222,18 +1223,9 @@ int usb_stor_get_info(struct usb_device *dev,struct us_data *ss,block_dev_desc_t
if(cap[0]>(0x200000 * 10)) /* greater than 10 GByte */
cap[0]>>=16;
#endif
#ifdef LITTLEENDIAN
cap[0] = ((unsigned long)(
(((unsigned long)(cap[0]) & (unsigned long)0x000000ffUL) << 24) |
(((unsigned long)(cap[0]) & (unsigned long)0x0000ff00UL) << 8) |
(((unsigned long)(cap[0]) & (unsigned long)0x00ff0000UL) >> 8) |
(((unsigned long)(cap[0]) & (unsigned long)0xff000000UL) >> 24) ));
cap[1] = ((unsigned long)(
(((unsigned long)(cap[1]) & (unsigned long)0x000000ffUL) << 24) |
(((unsigned long)(cap[1]) & (unsigned long)0x0000ff00UL) << 8) |
(((unsigned long)(cap[1]) & (unsigned long)0x00ff0000UL) >> 8) |
(((unsigned long)(cap[1]) & (unsigned long)0xff000000UL) >> 24) ));
#endif
cap[0] = cpu_to_be32(cap[0]);
cap[1] = cpu_to_be32(cap[1]);
/* this assumes bigendian! */
cap[0] += 1;
capacity = &cap[0];

13
cpu/arm920t/s3c24x0/usb_ohci.h
View File

@ -386,21 +386,19 @@ static ed_t * ep_add_ed(struct usb_device * usb_dev, unsigned long pipe);
/* +1 so we can align the storage */
td_t gtd[NUM_TD + 1];
/* pointers to aligned storage */
td_t *ptd;
/* TDs ... */
static inline struct td *
td_alloc (struct usb_device *usb_dev)
static inline struct td *td_alloc (struct usb_device *usb_dev)
{
int i;
struct td *td;
td = NULL;
for (i = 0; i < NUM_TD; i++)
{
if (ptd[i].usb_dev == NULL)
{
for (i = 0; i < NUM_TD; i++) {
if (ptd[i].usb_dev == NULL) {
td = &ptd[i];
td->usb_dev = usb_dev;
break;
@ -410,8 +408,7 @@ td_alloc (struct usb_device *usb_dev)
return td;
}
static inline void
ed_free (struct ed *ed)
static inline void ed_free (struct ed *ed)
{
ed->usb_dev = NULL;
}

19
cpu/arm926ejs/davinci/ether.c
View File

@ -538,18 +538,17 @@ static int tx_send_loop = 0;
static int dm644x_eth_send_packet (volatile void *packet, int length)
{
int ret_status = -1;
tx_send_loop = 0;
/* Return error if no link */
if (!phy.get_link_speed(active_phy_addr))
{
if (!phy.get_link_speed (active_phy_addr)) {
printf ("WARN: emac_send_packet: No link\n");
return (ret_status);
}
/* Check packet size and if < EMAC_MIN_ETHERNET_PKT_SIZE, pad it up */
if (length < EMAC_MIN_ETHERNET_PKT_SIZE)
{
if (length < EMAC_MIN_ETHERNET_PKT_SIZE) {
length = EMAC_MIN_ETHERNET_PKT_SIZE;
}
@ -597,18 +596,21 @@ static int dm644x_eth_rcv_packet(void)
/* Error in packet - discard it and requeue desc */
printf ("WARN: emac_rcv_pkt: Error in packet\n");
} else {
NetReceive(rx_curr_desc->buffer, (rx_curr_desc->buff_off_len & 0xffff));
NetReceive (rx_curr_desc->buffer,
(rx_curr_desc->buff_off_len & 0xffff));
ret = rx_curr_desc->buff_off_len & 0xffff;
}
/* Ack received packet descriptor */
adap_emac->RX0CP = (unsigned int) rx_curr_desc;
curr_desc = rx_curr_desc;
emac_rx_active_head = (volatile emac_desc *)rx_curr_desc->next;
emac_rx_active_head =
(volatile emac_desc *) rx_curr_desc->next;
if (status & EMAC_CPPI_EOQ_BIT) {
if (emac_rx_active_head) {
adap_emac->RX0HDP = (unsigned int)emac_rx_active_head;
adap_emac->RX0HDP =
(unsigned int) emac_rx_active_head;
} else {
emac_rx_queue_active = 0;
printf ("INFO:emac_rcv_packet: RX Queue not active\n");
@ -625,7 +627,8 @@ static int dm644x_eth_rcv_packet(void)
emac_rx_active_head = curr_desc;
emac_rx_active_tail = curr_desc;
if (emac_rx_queue_active != 0) {
adap_emac->RX0HDP = (unsigned int)emac_rx_active_head;
adap_emac->RX0HDP =
(unsigned int) emac_rx_active_head;
printf ("INFO: emac_rcv_pkt: active queue head = 0, HDP fired\n");
emac_rx_queue_active = 1;
}

11
cpu/mpc85xx/cpu.c
View File

@ -174,19 +174,24 @@ int do_reset (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[])
{
uint pvr;
uint ver;
unsigned long val, msr;
pvr = get_pvr();
ver = PVR_VER(pvr);
if (ver & 1){
/* e500 v2 core has reset control register */
volatile unsigned int * rstcr;
rstcr = (volatile unsigned int *)(CFG_IMMR + 0xE00B0);
*rstcr = 0x2; /* HRESET_REQ */
}else{
udelay(100);
}
/*
* Fallthrough if the code above failed
* Initiate hard reset in debug control register DBCR0
* Make sure MSR[DE] = 1
*/
unsigned long val, msr;
msr = mfmsr ();
msr |= MSR_DE;
@ -195,7 +200,7 @@ int do_reset (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[])
val = mfspr(DBCR0);
val |= 0x70000000;
mtspr(DBCR0,val);
}
return 1;
}

6
doc/README.generic_usb_ohci
View File

@ -51,6 +51,12 @@ You'll need to define
CONFIG_PCI_OHCI
If you have several USB PCI controllers, define
CONFIG_PCI_OHCI_DEVNO: number of the OHCI device in PCI list
If undefined, the first instance found in PCI space will be used.
PCI Controllers need to do byte swapping on register accesses, so they
should to define:

170
drivers/block/sym53c8xx.c
View File

@ -122,60 +122,143 @@ void handle_scsi_int(void);
void scsi_print_error (ccb * pccb)
{
int i;
printf("SCSI Error: Target %d LUN %d Command %02X\n",pccb->target, pccb->lun, pccb->cmd[0]);
printf ("SCSI Error: Target %d LUN %d Command %02X\n", pccb->target,
pccb->lun, pccb->cmd[0]);
printf (" CCB: ");
for (i = 0; i < pccb->cmdlen; i++)
printf ("%02X ", pccb->cmd[i]);
printf ("(len=%d)\n", pccb->cmdlen);
printf (" Cntrl: ");
switch (pccb->contr_stat) {
case SIR_COMPLETE: printf("Complete (no Error)\n"); break;
case SIR_SEL_ATN_NO_MSG_OUT: printf("Selected with ATN no MSG out phase\n"); break;
case SIR_CMD_OUT_ILL_PH: printf("Command out illegal phase\n"); break;
case SIR_MSG_RECEIVED: printf("MSG received Error\n"); break;
case SIR_DATA_IN_ERR: printf("Data in Error\n"); break;
case SIR_DATA_OUT_ERR: printf("Data out Error\n"); break;
case SIR_SCRIPT_ERROR: printf("Script Error\n"); break;
case SIR_MSG_OUT_NO_CMD: printf("MSG out no Command phase\n"); break;
case SIR_MSG_OVER7: printf("MSG in over 7 bytes\n"); break;
case INT_ON_FY: printf("Interrupt on fly\n"); break;
case SCSI_SEL_TIME_OUT: printf("SCSI Selection Timeout\n"); break;
case SCSI_HNS_TIME_OUT: printf("SCSI Handshake Timeout\n"); break;
case SCSI_MA_TIME_OUT: printf("SCSI Phase Error\n"); break;
case SCSI_UNEXP_DIS: printf("SCSI unexpected disconnect\n"); break;
default: printf("unknown status %lx\n",pccb->contr_stat); break;
case SIR_COMPLETE:
printf ("Complete (no Error)\n");
break;
case SIR_SEL_ATN_NO_MSG_OUT:
printf ("Selected with ATN no MSG out phase\n");
break;
case SIR_CMD_OUT_ILL_PH:
printf ("Command out illegal phase\n");
break;
case SIR_MSG_RECEIVED:
printf ("MSG received Error\n");
break;
case SIR_DATA_IN_ERR:
printf ("Data in Error\n");
break;
case SIR_DATA_OUT_ERR:
printf ("Data out Error\n");
break;
case SIR_SCRIPT_ERROR:
printf ("Script Error\n");
break;
case SIR_MSG_OUT_NO_CMD:
printf ("MSG out no Command phase\n");
break;
case SIR_MSG_OVER7:
printf ("MSG in over 7 bytes\n");
break;
case INT_ON_FY:
printf ("Interrupt on fly\n");
break;
case SCSI_SEL_TIME_OUT:
printf ("SCSI Selection Timeout\n");
break;
case SCSI_HNS_TIME_OUT:
printf ("SCSI Handshake Timeout\n");
break;
case SCSI_MA_TIME_OUT:
printf ("SCSI Phase Error\n");
break;
case SCSI_UNEXP_DIS:
printf ("SCSI unexpected disconnect\n");
break;
default:
printf ("unknown status %lx\n", pccb->contr_stat);
break;
}
printf (" Sense: SK %x (", pccb->sense_buf[2] & 0x0f);
switch (pccb->sense_buf[2] & 0xf) {
case SENSE_NO_SENSE: printf("No Sense)"); break;
case SENSE_RECOVERED_ERROR: printf("Recovered Error)"); break;
case SENSE_NOT_READY: printf("Not Ready)"); break;
case SENSE_MEDIUM_ERROR: printf("Medium Error)"); break;
case SENSE_HARDWARE_ERROR: printf("Hardware Error)"); break;
case SENSE_ILLEGAL_REQUEST: printf("Illegal request)"); break;
case SENSE_UNIT_ATTENTION: printf("Unit Attention)"); break;
case SENSE_DATA_PROTECT: printf("Data Protect)"); break;
case SENSE_BLANK_CHECK: printf("Blank check)"); break;
case SENSE_VENDOR_SPECIFIC: printf("Vendor specific)"); break;
case SENSE_COPY_ABORTED: printf("Copy aborted)"); break;
case SENSE_ABORTED_COMMAND: printf("Aborted Command)"); break;
case SENSE_VOLUME_OVERFLOW: printf("Volume overflow)"); break;
case SENSE_MISCOMPARE: printf("Misscompare\n"); break;
default: printf("Illegal Sensecode\n"); break;
case SENSE_NO_SENSE:
printf ("No Sense)");
break;
case SENSE_RECOVERED_ERROR:
printf ("Recovered Error)");
break;
case SENSE_NOT_READY:
printf ("Not Ready)");
break;
case SENSE_MEDIUM_ERROR:
printf ("Medium Error)");
break;
case SENSE_HARDWARE_ERROR:
printf ("Hardware Error)");
break;
case SENSE_ILLEGAL_REQUEST:
printf ("Illegal request)");
break;
case SENSE_UNIT_ATTENTION:
printf ("Unit Attention)");
break;
case SENSE_DATA_PROTECT:
printf ("Data Protect)");
break;
case SENSE_BLANK_CHECK:
printf ("Blank check)");
break;
case SENSE_VENDOR_SPECIFIC:
printf ("Vendor specific)");
break;
case SENSE_COPY_ABORTED:
printf ("Copy aborted)");
break;
case SENSE_ABORTED_COMMAND:
printf ("Aborted Command)");
break;
case SENSE_VOLUME_OVERFLOW:
printf ("Volume overflow)");
break;
case SENSE_MISCOMPARE:
printf ("Misscompare\n");
break;
default:
printf ("Illegal Sensecode\n");
break;
}
printf(" ASC %x ASCQ %x\n",pccb->sense_buf[12],pccb->sense_buf[13]);
printf (" ASC %x ASCQ %x\n", pccb->sense_buf[12],
pccb->sense_buf[13]);
printf (" Status: ");
switch (pccb->status) {
case S_GOOD : printf("Good\n"); break;
case S_CHECK_COND: printf("Check condition\n"); break;
case S_COND_MET: printf("Condition Met\n"); break;
case S_BUSY: printf("Busy\n"); break;
case S_INT: printf("Intermediate\n"); break;
case S_INT_COND_MET: printf("Intermediate condition met\n"); break;
case S_CONFLICT: printf("Reservation conflict\n"); break;
case S_TERMINATED: printf("Command terminated\n"); break;
case S_QUEUE_FULL: printf("Task set full\n"); break;
default: printf("unknown: %02X\n",pccb->status); break;
case S_GOOD:
printf ("Good\n");
break;
case S_CHECK_COND:
printf ("Check condition\n");
break;
case S_COND_MET:
printf ("Condition Met\n");
break;
case S_BUSY:
printf ("Busy\n");
break;
case S_INT:
printf ("Intermediate\n");
break;
case S_INT_COND_MET:
printf ("Intermediate condition met\n");
break;
case S_CONFLICT:
printf ("Reservation conflict\n");
break;
case S_TERMINATED:
printf ("Command terminated\n");
break;
case S_QUEUE_FULL:
printf ("Task set full\n");
break;
default:
printf ("unknown: %02X\n", pccb->status);
break;
}
}
@ -252,8 +335,7 @@ void handle_scsi_int(void)
if((stat & DIP)==DIP) { /* DMA Interrupt pending */
stat1=scsi_read_byte(DSTAT);
#ifdef SCSI_SINGLE_STEP
if((stat1 & SSI)==SSI)
{
if((stat1 & SSI)==SSI) {
tt=in32r(scsi_mem_addr+DSP);
if(((tt)>=start_script_select) && ((tt)<start_script_select+len_script_select)) {
printf("select %d\n",(tt-start_script_select)>>2);

3
drivers/net/dc2114x.c
View File

@ -761,8 +761,7 @@ static void update_srom(struct eth_device *dev, bd_t *bis)
eeprom[0x0b] = ((bis->bi_enetaddr[3] & 0xff) << 8) | (bis->bi_enetaddr[2] & 0xff);
eeprom[0x0c] = ((bis->bi_enetaddr[5] & 0xff) << 8) | (bis->bi_enetaddr[4] & 0xff);
for (i=0; i<0x40; i++)
{
for (i=0; i<0x40; i++) {
write_srom(dev, DE4X5_APROM, i, eeprom[i]);
}
}

3
drivers/net/rtl8019.h
View File

@ -30,7 +30,6 @@
#include <asm/types.h>
#include <config.h>
#ifdef CONFIG_DRIVER_RTL8019
#define RTL8019_REG_00 (RTL8019_BASE + 0x00)
@ -94,7 +93,6 @@
#define RTL8019_DMA_DATA RTL8019_REG_10
#define RTL8019_RESET RTL8019_REG_1f
#define RTL8019_PAGE0 0x22
#define RTL8019_PAGE1 0x62
#define RTL8019_PAGE0DMAWRITE 0x12
@ -113,5 +111,4 @@
#define RTL8019_PSTOP 0x80
#define RTL8019_TPSTART 0x40
#endif /*end of CONFIG_DRIVER_RTL8019*/

1
drivers/net/sk98lin/h/skgepnmi.h
View File

@ -1091,7 +1091,6 @@ typedef struct s_PnmiData {
SK_PNMI_VCT_TIMER VctTimeout[SK_MAX_MACS];
} SK_PNMI;
/*
* Function prototypes
*/

3
drivers/net/sk98lin/skgeinit.c
View File

@ -1264,8 +1264,7 @@ int Port) /* Port Index (MAC_1 + n) */
if (pPrt->PRxQSize == SK_MIN_RXQ_SIZE) {
RxQType = SK_RX_SRAM_Q; /* small Rx Queue */
}
else {
} else {
RxQType = SK_RX_BRAM_Q; /* big Rx Queue */
}

3
drivers/net/sk98lin/skproc.c
View File

@ -89,8 +89,7 @@
extern SK_AC *pACList;
extern struct net_device *SkGeRootDev;
extern char * SkNumber(
char * str,
extern char *SkNumber (char *str,
long long num,
int base,
int size,

11
drivers/usb/usb_ohci.c
View File

@ -53,6 +53,9 @@
#if defined(CONFIG_PCI_OHCI)
# include <pci.h>
#if !defined(CONFIG_PCI_OHCI_DEVNO)
#define CONFIG_PCI_OHCI_DEVNO 0
#endif
#endif
#include <malloc.h>
@ -1218,9 +1221,9 @@ pkt_print(NULL, dev, pipe, buffer, transfer_len, cmd, "SUB(rh)", usb_pipein(pipe
}
bmRType_bReq = cmd->requesttype | (cmd->request << 8);
wValue = cpu_to_le16 (cmd->value);
wIndex = cpu_to_le16 (cmd->index);
wLength = cpu_to_le16 (cmd->length);
wValue = le16_to_cpu (cmd->value);
wIndex = le16_to_cpu (cmd->index);
wLength = le16_to_cpu (cmd->length);
info("Root-Hub: adr: %2x cmd(%1x): %08x %04x %04x %04x",
dev->devnum, 8, bmRType_bReq, wValue, wIndex, wLength);
@ -1818,7 +1821,7 @@ int usb_lowlevel_init(void)
gohci.sleeping = 0;
gohci.irq = -1;
#ifdef CONFIG_PCI_OHCI
pdev = pci_find_devices(ohci_pci_ids, 0);
pdev = pci_find_devices(ohci_pci_ids, CONFIG_PCI_OHCI_DEVNO);
if (pdev != -1) {
u16 vid, did;

1
fs/reiserfs/mode_string.c
View File

@ -1,4 +1,3 @@
/* vi: set sw=4 ts=4: */
/*
* mode_string implementation for busybox
*

1
include/asm-arm/arch-pxa/mmc.h
View File

@ -203,5 +203,4 @@ typedef struct mmc_csd
ecc:2;
} mmc_csd_t;
#endif /* __MMC_PXA_P_H__ */

2
include/asm-arm/global_data.h
View File

@ -61,6 +61,8 @@ typedef struct global_data {
#define GD_FLG_DEVINIT 0x00002 /* Devices have been initialized */
#define GD_FLG_SILENT 0x00004 /* Silent mode */
#define GD_FLG_POSTFAIL 0x00008 /* Critical POST test failed */
#define GD_FLG_POSTSTOP 0x00010 /* POST seqeunce aborted */
#define GD_FLG_LOGINIT 0x00020 /* Log Buffer has been initialized */
#define DECLARE_GLOBAL_DATA_PTR register volatile gd_t *gd asm ("r8")

2
include/asm-avr32/global_data.h
View File

@ -52,6 +52,8 @@ typedef struct global_data {
#define GD_FLG_DEVINIT 0x00002 /* Devices have been initialized */
#define GD_FLG_SILENT 0x00004 /* Silent mode */
#define GD_FLG_POSTFAIL 0x00008 /* Critical POST test failed */
#define GD_FLG_POSTSTOP 0x00010 /* POST seqeunce aborted */
#define GD_FLG_LOGINIT 0x00020 /* Log Buf has been initialized */
#define DECLARE_GLOBAL_DATA_PTR register gd_t *gd asm("r5")

2
include/asm-blackfin/global_data.h
View File

@ -62,6 +62,8 @@ typedef struct global_data {
#define GD_FLG_DEVINIT 0x00002 /* Devices have been initialized */
#define GD_FLG_SILENT 0x00004 /* Silent mode */
#define GD_FLG_POSTFAIL 0x00008 /* Critical POST test failed */
#define GD_FLG_POSTSTOP 0x00010 /* POST seqeunce aborted */
#define GD_FLG_LOGINIT 0x00020 /* Log Buf has been initialized */
#define DECLARE_GLOBAL_DATA_PTR register gd_t * volatile gd asm ("P5")

2
include/asm-i386/global_data.h
View File

@ -55,6 +55,8 @@ typedef struct {
#define GD_FLG_DEVINIT 0x00002 /* Devices have been initialized */
#define GD_FLG_SILENT 0x00004 /* Silent mode */
#define GD_FLG_POSTFAIL 0x00008 /* Critical POST test failed */
#define GD_FLG_POSTSTOP 0x00010 /* POST seqeunce aborted */
#define GD_FLG_LOGINIT 0x00020 /* Log Buffer has been initialized */
extern gd_t *global_data;

2
include/asm-m68k/global_data.h
View File

@ -73,6 +73,8 @@ typedef struct global_data {
#define GD_FLG_DEVINIT 0x00002 /* Devices have been initialized */
#define GD_FLG_SILENT 0x00004 /* Silent mode */
#define GD_FLG_POSTFAIL 0x00008 /* Critical POST test failed */
#define GD_FLG_POSTSTOP 0x00010 /* POST seqeunce aborted */
#define GD_FLG_LOGINIT 0x00020 /* Log Buffer has been initialized */
#if 0
extern gd_t *global_data;

2
include/asm-microblaze/global_data.h
View File

@ -53,6 +53,8 @@ typedef struct global_data {
#define GD_FLG_DEVINIT 0x00002 /* Devices have been initialized */
#define GD_FLG_SILENT 0x00004 /* Silent mode */
#define GD_FLG_POSTFAIL 0x00008 /* Critical POST test failed */
#define GD_FLG_POSTSTOP 0x00010 /* POST seqeunce aborted */
#define GD_FLG_LOGINIT 0x00020 /* Log Buffer has been initialized */
#define DECLARE_GLOBAL_DATA_PTR register volatile gd_t *gd asm ("r31")

2
include/asm-mips/global_data.h
View File

@ -55,6 +55,8 @@ typedef struct global_data {
#define GD_FLG_DEVINIT 0x00002 /* Devices have been initialized */
#define GD_FLG_SILENT 0x00004 /* Silent mode */
#define GD_FLG_POSTFAIL 0x00008 /* Critical POST test failed */
#define GD_FLG_POSTSTOP 0x00010 /* POST seqeunce aborted */
#define GD_FLG_LOGINIT 0x00020 /* Log Buf has been initialized */
#define DECLARE_GLOBAL_DATA_PTR register volatile gd_t *gd asm ("k0")

2
include/asm-nios/global_data.h
View File

@ -46,6 +46,8 @@ typedef struct global_data {
#define GD_FLG_DEVINIT 0x00002 /* Devices have been initialized */
#define GD_FLG_SILENT 0x00004 /* Silent mode */
#define GD_FLG_POSTFAIL 0x00008 /* Critical POST test failed */
#define GD_FLG_POSTSTOP 0x00010 /* POST seqeunce aborted */
#define GD_FLG_LOGINIT 0x00020 /* Log Buffer has been initialized */
#define DECLARE_GLOBAL_DATA_PTR register gd_t *gd asm ("%g7")

2
include/asm-nios2/global_data.h
View File

@ -45,6 +45,8 @@ typedef struct global_data {
#define GD_FLG_DEVINIT 0x00002 /* Devices have been initialized */
#define GD_FLG_SILENT 0x00004 /* Silent mode */
#define GD_FLG_POSTFAIL 0x00008 /* Critical POST test failed */
#define GD_FLG_POSTSTOP 0x00010 /* POST seqeunce aborted */
#define GD_FLG_LOGINIT 0x00020 /* Log Buffer has been initialized */
#define DECLARE_GLOBAL_DATA_PTR register gd_t *gd asm ("r15")

2
include/asm-ppc/global_data.h
View File

@ -168,6 +168,8 @@ typedef struct global_data {
#define GD_FLG_DEVINIT 0x00002 /* Devices have been initialized */
#define GD_FLG_SILENT 0x00004 /* Silent mode */
#define GD_FLG_POSTFAIL 0x00008 /* Critical POST test failed */
#define GD_FLG_POSTSTOP 0x00010 /* POST seqeunce aborted */
#define GD_FLG_LOGINIT 0x00020 /* Log Buffer has been initialized */
#if 1
#define DECLARE_GLOBAL_DATA_PTR register volatile gd_t *gd asm ("r2")

2
include/asm-sh/global_data.h
View File

@ -45,6 +45,8 @@ typedef struct global_data
#define GD_FLG_DEVINIT 0x00002 /* Devices have been initialized */
#define GD_FLG_SILENT 0x00004 /* Silent mode */
#define GD_FLG_POSTFAIL 0x00008 /* Critical POST test failed */
#define GD_FLG_POSTSTOP 0x00010 /* POST seqeunce aborted */
#define GD_FLG_LOGINIT 0x00020 /* Log Buffer has been initialized */
#define DECLARE_GLOBAL_DATA_PTR register gd_t *gd asm ("r13")

3
include/asm-sparc/global_data.h
View File

@ -79,6 +79,9 @@ typedef struct global_data {
#define GD_FLG_RELOC 0x00001 /* Code was relocated to RAM */
#define GD_FLG_DEVINIT 0x00002 /* Devices have been initialized */
#define GD_FLG_SILENT 0x00004 /* Silent mode */
#define GD_FLG_POSTFAIL 0x00008 /* Critical POST test failed */
#define GD_FLG_POSTSTOP 0x00010 /* POST seqeunce aborted */
#define GD_FLG_LOGINIT 0x00020 /* Log Buffer has been initialized */
#define DECLARE_GLOBAL_DATA_PTR register volatile gd_t *gd asm ("%g7")

2
include/configs/GEN860T.h
View File

@ -760,5 +760,3 @@
#endif
#endif /* __CONFIG_GEN860T_H */
/* vim: set ts=4 tw=78 ai shiftwidth=4: */

5
include/configs/MVS1.h
View File

@ -46,7 +46,10 @@
#define CONFIG_BAUDRATE 115200 /* console baudrate */
#define CONFIG_BOOTDELAY 5 /* autoboot after this many seconds */
#define CONFIG_PREBOOT "echo;echo To mount root over NFS use \"run bootnet\";echo To mount root from FLASH use \"run bootflash\";echo"
#define CONFIG_PREBOOT "echo;" \
"echo To mount root over NFS use \"run bootnet\";" \
"echo To mount root from FLASH use \"run bootflash\";" \
"echo"
#define CONFIG_BOOTARGS "root=/dev/mtdblock2 rw"
#define CONFIG_BOOTCOMMAND \
"bootp; " \

41
include/configs/ads5121.h
View File

@ -45,14 +45,25 @@
*/
#define CONFIG_E300 1 /* E300 Family */
#define CONFIG_MPC512X 1 /* MPC512X family */
#define CONFIG_FSL_DIU_FB 1 /* FSL DIU */
/* video */
#undef CONFIG_VIDEO
#if defined(CONFIG_VIDEO)
#define CONFIG_CFB_CONSOLE
#define CONFIG_VGA_AS_SINGLE_DEVICE
#endif
/* CONFIG_PCI is defined at config time */
#define CFG_MPC512X_CLKIN 66000000 /* in Hz */
#define CONFIG_BOARD_EARLY_INIT_F /* call board_early_init_f() */
#define CONFIG_MISC_INIT_R
#define CFG_IMMR 0x80000000
#define CFG_DIU_ADDR (CFG_IMMR+0x2100)
#define CFG_MEMTEST_START 0x00200000 /* memtest region */
#define CFG_MEMTEST_END 0x00400000
@ -127,23 +138,23 @@
#define CFG_MICRON_OCD_DEFAULT 0x01010780
/* DDR Priority Manager Configuration */
#define CFG_MDDRCGRP_PM_CFG1 0x000777AA
#define CFG_MDDRCGRP_PM_CFG2 0x00000055
#define CFG_MDDRCGRP_HIPRIO_CFG 0x00000000
#define CFG_MDDRCGRP_LUT0_MU 0x11111117
#define CFG_MDDRCGRP_LUT0_ML 0x7777777A
#define CFG_MDDRCGRP_LUT1_MU 0x4444EEEE
#define CFG_MDDRCGRP_LUT1_ML 0xEEEEEEEE
#define CFG_MDDRCGRP_PM_CFG1 0x00077777
#define CFG_MDDRCGRP_PM_CFG2 0x00000000
#define CFG_MDDRCGRP_HIPRIO_CFG 0x00000001
#define CFG_MDDRCGRP_LUT0_MU 0xFFEEDDCC
#define CFG_MDDRCGRP_LUT0_ML 0xBBAAAAAA
#define CFG_MDDRCGRP_LUT1_MU 0x66666666
#define CFG_MDDRCGRP_LUT1_ML 0x55555555
#define CFG_MDDRCGRP_LUT2_MU 0x44444444
#define CFG_MDDRCGRP_LUT2_ML 0x44444444
#define CFG_MDDRCGRP_LUT3_MU 0x55555555
#define CFG_MDDRCGRP_LUT3_ML 0x55555558
#define CFG_MDDRCGRP_LUT4_MU 0x11111111
#define CFG_MDDRCGRP_LUT4_ML 0x1111117C
#define CFG_MDDRCGRP_LUT0_AU 0x33333377
#define CFG_MDDRCGRP_LUT0_AL 0x7777EEEE
#define CFG_MDDRCGRP_LUT1_AU 0x11111111
#define CFG_MDDRCGRP_LUT1_AL 0x11111111
#define CFG_MDDRCGRP_LUT4_ML 0x11111122
#define CFG_MDDRCGRP_LUT0_AU 0xaaaaaaaa
#define CFG_MDDRCGRP_LUT0_AL 0xaaaaaaaa
#define CFG_MDDRCGRP_LUT1_AU 0x66666666
#define CFG_MDDRCGRP_LUT1_AL 0x66666666
#define CFG_MDDRCGRP_LUT2_AU 0x11111111
#define CFG_MDDRCGRP_LUT2_AL 0x11111111
#define CFG_MDDRCGRP_LUT3_AU 0x11111111
@ -189,7 +200,11 @@
#define CFG_MONITOR_BASE TEXT_BASE /* Start of monitor */
#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
#define CFG_MALLOC_LEN (512 * 1024) /* Reserved for malloc */
#ifdef CONFIG_FSL_DIU_FB
#define CFG_MALLOC_LEN (6 * 1024 * 1024) /* Reserved for malloc */
#else
#define CFG_MALLOC_LEN (512 * 1024)
#endif
/*
* Serial Port

0
include/configs/apollon.h Executable file → Normal file
View File

3
include/configs/bf561-ezkit.h
View File

@ -169,7 +169,6 @@
""
#endif
/*
* BOOTP options
*/
@ -178,7 +177,6 @@
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME
/*
* Command line configuration.
*/
@ -193,7 +191,6 @@
#define CONFIG_CMD_DHCP
#endif
/*
* Console settings
*/

6
include/configs/lwmon5.h
View File

@ -88,15 +88,20 @@
/* unused GPT0 COMP reg */
#define CFG_MEM_TOP_HIDE (4 << 10) /* don't use last 4kbytes */
/* 440EPx errata CHIP 11 */
#define CFG_OCM_SIZE (16 << 10)
/* Additional registers for watchdog timer post test */
#define CFG_WATCHDOG_TIME_ADDR (CFG_PERIPHERAL_BASE + GPT0_MASK2)
#define CFG_WATCHDOG_FLAGS_ADDR (CFG_PERIPHERAL_BASE + GPT0_MASK1)
#define CFG_DSPIC_TEST_ADDR CFG_WATCHDOG_FLAGS_ADDR
#define CFG_OCM_STATUS_ADDR CFG_WATCHDOG_FLAGS_ADDR
#define CFG_WATCHDOG_MAGIC 0x12480000
#define CFG_WATCHDOG_MAGIC_MASK 0xFFFF0000
#define CFG_DSPIC_TEST_MASK 0x00000001
#define CFG_OCM_STATUS_OK 0x00009A00
#define CFG_OCM_STATUS_FAIL 0x0000A300
#define CFG_OCM_STATUS_MASK 0x0000FF00
/*-----------------------------------------------------------------------
* Serial Port
@ -162,6 +167,7 @@
CFG_POST_FPU | \
CFG_POST_I2C | \
CFG_POST_MEMORY | \
CFG_POST_OCM | \
CFG_POST_RTC | \
CFG_POST_SPR | \
CFG_POST_UART | \

3
include/configs/modnet50.h
View File

@ -90,7 +90,8 @@
/*#define CONFIG_BOOTDELAY 10*/
/* args and cmd for uClinux-image @ 0x10020000, ramdisk-image @ 0x100a0000 */
#define CONFIG_BOOTCOMMAND "bootm 0x10020000 0x100a0000"
#define CONFIG_BOOTARGS "console=ttyS0,38400 initrd=0x100a0040,530K root=/dev/ram keepinitrd"
#define CONFIG_BOOTARGS "console=ttyS0,38400 initrd=0x100a0040,530K " \
"root=/dev/ram keepinitrd"
#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */

4
include/configs/sbc2410x.h
View File

@ -106,7 +106,9 @@
#define CONFIG_BOOTDELAY 3
#define CONFIG_BOOTARGS "console=ttySAC0 root=/dev/nfs nfsroot=192.168.0.1:/friendly-arm/rootfs_netserv ip=192.168.0.69:192.168.0.1:192.168.0.1:255.255.255.0:debian:eth0:off"
#define CONFIG_BOOTARGS "console=ttySAC0 root=/dev/nfs " \
"nfsroot=192.168.0.1:/friendly-arm/rootfs_netserv " \
"ip=192.168.0.69:192.168.0.1:192.168.0.1:255.255.255.0:debian:eth0:off"
#define CONFIG_ETHADDR 08:00:3e:26:0a:5b
#define CONFIG_NETMASK 255.255.255.0
#define CONFIG_IPADDR 192.168.0.69

8
include/configs/sc520_spunk.h
View File

@ -88,8 +88,12 @@
#define CONFIG_BOOTDELAY 15
#define CONFIG_BOOTARGS "root=/dev/mtdblock1 console=ttyS0,9600 mtdparts=phys:7936k(root),256k(uboot) "
#define CONFIG_BOOTCOMMAND "setenv bootargs root=/dev/nfs ip=autoconf console=ttyS0,9600 mtdparts=phys:7808k(root),128k(env),256k(uboot); bootp; bootm"
#define CONFIG_BOOTARGS "root=/dev/mtdblock1 console=ttyS0,9600 " \
"mtdparts=phys:7936k(root),256k(uboot) "
#define CONFIG_BOOTCOMMAND "setenv bootargs root=/dev/nfs ip=autoconf " \
"console=ttyS0,9600 " \
"mtdparts=phys:7808k(root),128k(env),256k(uboot);" \
"bootp;bootm"
#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */

8
include/configs/smdk2400.h
View File

@ -114,17 +114,9 @@
#define CONFIG_BOOTDELAY 3
#if 0
#define CONFIG_BOOTARGS "root=ramfs devfs=mount console=ttySA0,9600"
#define CONFIG_ETHADDR 08:00:3e:26:0a:5b
#endif
#define CONFIG_NETMASK 255.255.255.0
#define CONFIG_IPADDR 134.98.93.36
#define CONFIG_SERVERIP 134.98.93.22
#if 0
#define CONFIG_BOOTFILE "elinos-lart"
#define CONFIG_BOOTCOMMAND "tftp; bootm"
#endif
#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */

422
include/configs/socrates.h Normal file
View File

@ -0,0 +1,422 @@
/*
* (C) Copyright 2008
* Sergei Poselenov, Emcraft Systems, sposelenov@emcraft.com.
*
* Wolfgang Denk <wd@denx.de>
* Copyright 2004 Freescale Semiconductor.
* (C) Copyright 2002,2003 Motorola,Inc.
* Xianghua Xiao <X.Xiao@motorola.com>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
/*
* Socrates
*/
#ifndef __CONFIG_H
#define __CONFIG_H
/* High Level Configuration Options */
#define CONFIG_BOOKE 1 /* BOOKE */
#define CONFIG_E500 1 /* BOOKE e500 family */
#define CONFIG_MPC85xx 1 /* MPC8540/60/55/41 */
#define CONFIG_MPC8544 1
#define CONFIG_SOCRATES 1
#define CONFIG_PCI
#define CONFIG_TSEC_ENET /* tsec ethernet support */
#define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */
#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
/*
* Only possible on E500 Version 2 or newer cores.
*/
#define CONFIG_ENABLE_36BIT_PHYS 1
/*
* sysclk for MPC85xx
*
* Two valid values are:
* 33000000
* 66000000
*
* Most PCI cards are still 33Mhz, so in the presence of PCI, 33MHz
* is likely the desired value here, so that is now the default.
* The board, however, can run at 66MHz. In any event, this value
* must match the settings of some switches. Details can be found
* in the README.mpc85xxads.
*/
#ifndef CONFIG_SYS_CLK_FREQ
#define CONFIG_SYS_CLK_FREQ 66666666
#endif
/*
* These can be toggled for performance analysis, otherwise use default.
*/
#define CONFIG_L2_CACHE /* toggle L2 cache */
#define CONFIG_BTB /* toggle branch predition */
#define CONFIG_ADDR_STREAMING /* toggle addr streaming */
#define CFG_INIT_DBCR DBCR_IDM /* Enable Debug Exceptions */
#undef CFG_DRAM_TEST /* memory test, takes time */
#define CFG_MEMTEST_START 0x00000000
#define CFG_MEMTEST_END 0x10000000
/*
* Base addresses -- Note these are effective addresses where the
* actual resources get mapped (not physical addresses)
*/
#define CFG_CCSRBAR_DEFAULT 0xFF700000 /* CCSRBAR Default */
#define CFG_CCSRBAR 0xE0000000 /* relocated CCSRBAR */
#define CFG_CCSRBAR_PHYS CFG_CCSRBAR /* physical addr of CCSRBAR */
#define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */
/*
* DDR Setup
*/
#define CFG_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory */
#define CFG_SDRAM_BASE CFG_DDR_SDRAM_BASE
#define CONFIG_DDR_DEFAULT_CL 30 /* CAS latency 3 */
/* Hardcoded values, to use instead of SPD */
#define CFG_DDR_CS0_BNDS 0x0000000f
#define CFG_DDR_CS0_CONFIG 0x80010102
#define CFG_DDR_TIMING_0 0x00260802
#define CFG_DDR_TIMING_1 0x3935D322
#define CFG_DDR_TIMING_2 0x14904CC8
#define CFG_DDR_MODE 0x00480432
#define CFG_DDR_INTERVAL 0x030C0100
#define CFG_DDR_CONFIG_2 0x04400000
#define CFG_DDR_CONFIG 0xC3008000
#define CFG_DDR_CLK_CONTROL 0x03800000
#define CFG_SDRAM_SIZE 256 /* in Megs */
#define CONFIG_SPD_EEPROM 1 /* Use SPD EEPROM for DDR setup*/
#define SPD_EEPROM_ADDRESS 0x50 /* DDR DIMM */
#define MPC85xx_DDR_SDRAM_CLK_CNTL /* 85xx has clock control reg */
/*
* Flash on the Local Bus
*/
/*
* Flash on the LocalBus
*/
#define CFG_LBC_CACHE_BASE 0xf0000000 /* Localbus cacheable */
#define CFG_FLASH0 0xFE000000
#define CFG_FLASH1 0xFC000000
#define CFG_FLASH_BANKS_LIST { CFG_FLASH1, CFG_FLASH0 }
#define CFG_LBC_FLASH_BASE CFG_FLASH1 /* Localbus flash start */
#define CFG_FLASH_BASE CFG_LBC_FLASH_BASE /* start of FLASH */
#define CFG_BR0_PRELIM 0xfe001001 /* port size 16bit */
#define CFG_OR0_PRELIM 0xfe000ff7 /* 32MB Flash */
#define CFG_BR1_PRELIM 0xfc001001 /* port size 16bit */
#define CFG_OR1_PRELIM 0xfe000ff7 /* 32MB Flash */
#define CFG_FLASH_CFI /* flash is CFI compat. */
#define CFG_FLASH_CFI_DRIVER /* Use common CFI driver*/
#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector */
#define CFG_MAX_FLASH_BANKS 2 /* number of banks */
#define CFG_MAX_FLASH_SECT 256 /* sectors per device */
#undef CFG_FLASH_CHECKSUM
#define CFG_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */
#define CFG_LBC_LCRR 0x00030008 /* LB clock ratio reg */
#define CFG_LBC_LBCR 0x00000000 /* LB config reg */
#define CFG_LBC_LSRT 0x20000000 /* LB sdram refresh timer */
#define CFG_LBC_MRTPR 0x20000000 /* LB refresh timer presc.*/
#define CONFIG_L1_INIT_RAM
#define CFG_INIT_RAM_LOCK 1
#define CFG_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */
#define CFG_INIT_RAM_END 0x4000 /* End used area in RAM */
#define CFG_GBL_DATA_SIZE 128 /* num bytes initial data*/
#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256kB for Mon*/
#define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */
/* Serial Port */
#define CONFIG_CONS_INDEX 1
#undef CONFIG_SERIAL_SOFTWARE_FIFO
#define CFG_NS16550
#define CFG_NS16550_SERIAL
#define CFG_NS16550_REG_SIZE 1
#define CFG_NS16550_CLK get_bus_freq(0)
#define CFG_NS16550_COM1 (CFG_CCSRBAR+0x4500)
#define CFG_NS16550_COM2 (CFG_CCSRBAR+0x4600)
#define CONFIG_BAUDRATE 115200
#define CFG_BAUDRATE_TABLE \
{300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
#define CFG_HUSH_PARSER 1 /* Use the HUSH parser */
#ifdef CFG_HUSH_PARSER
#define CFG_PROMPT_HUSH_PS2 "> "
#endif
/*
* I2C
*/
#define CONFIG_FSL_I2C /* Use FSL common I2C driver */
#define CONFIG_HARD_I2C /* I2C with hardware support */
#undef CONFIG_SOFT_I2C /* I2C bit-banged */
#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
#define CFG_I2C_SLAVE 0x7F
#define CFG_I2C_NOPROBES {0x48} /* Don't probe these addrs */
#define CFG_I2C_OFFSET 0x3000
/* I2C RTC */
#define CONFIG_RTC_RX8025 /* Use Epson rx8025 rtc via i2c */
#define CFG_I2C_RTC_ADDR 0x32 /* at address 0x32 */
/* I2C temp sensor */
/* Socrates uses Maxim's DS75, which is compatible with LM75 */
#define CONFIG_DTT_LM75 1
#define CONFIG_DTT_SENSORS {4} /* Sensor addresses */
#define CFG_DTT_MAX_TEMP 125
#define CFG_DTT_LOW_TEMP -55
#define CFG_DTT_HYSTERESIS 3
#define CFG_EEPROM_PAGE_WRITE_ENABLE /* necessary for the LM75 chip */
#define CFG_EEPROM_PAGE_WRITE_BITS 4
/* RapidIO MMU */
#define CFG_RIO_MEM_BASE 0xc0000000 /* base address */
#define CFG_RIO_MEM_PHYS CFG_RIO_MEM_BASE
#define CFG_RIO_MEM_SIZE 0x20000000 /* 128M */
/*
* General PCI
* Memory space is mapped 1-1.
*/
#define CFG_PCI_PHYS 0x80000000 /* 1G PCI TLB */
#define CFG_PCI1_MEM_BASE 0x80000000
#define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE
#define CFG_PCI1_MEM_SIZE 0x20000000 /* 512M */
#define CFG_PCI1_IO_BASE 0xE2000000
#define CFG_PCI1_IO_PHYS CFG_PCI1_IO_BASE
#define CFG_PCI1_IO_SIZE 0x01000000 /* 16M */
#if defined(CONFIG_PCI)
#define CONFIG_PCI_PNP /* do pci plug-and-play */
#define CONFIG_EEPRO100
#undef CONFIG_TULIP
#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
#define CFG_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */
#endif /* CONFIG_PCI */
#define CONFIG_NET_MULTI 1
#define CONFIG_MII 1 /* MII PHY management */
#define CONFIG_TSEC1 1
#define CONFIG_TSEC1_NAME "TSEC0"
#define CONFIG_TSEC3 1
#define CONFIG_TSEC3_NAME "TSEC1"
#undef CONFIG_MPC85XX_FEC
#define TSEC1_PHY_ADDR 0
#define TSEC3_PHY_ADDR 1
#define TSEC1_PHYIDX 0
#define TSEC3_PHYIDX 0
#define TSEC1_FLAGS TSEC_GIGABIT
#define TSEC3_FLAGS TSEC_GIGABIT
/* Options are: TSEC[0,1] */
#define CONFIG_ETHPRIME "TSEC0"
#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
#define CONFIG_HAS_ETH0
#define CONFIG_HAS_ETH1
/*
* Environment
*/
#define CFG_ENV_IS_IN_FLASH 1
#define CFG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */
#define CFG_ENV_ADDR (CFG_MONITOR_BASE - CFG_ENV_SECT_SIZE)
#define CFG_ENV_SIZE 0x4000
#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR-CFG_ENV_SECT_SIZE)
#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
#define CONFIG_TIMESTAMP /* Print image info with ts */
/*
* BOOTP options
*/
#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME
/*
* Command line configuration.
*/
#include <config_cmd_default.h>
#define CONFIG_CMD_DATE
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_DTT
#undef CONFIG_CMD_EEPROM
#define CONFIG_CMD_I2C
#define CONFIG_CMD_MII
#define CONFIG_CMD_NFS
#define CONFIG_CMD_PING
#define CONFIG_CMD_SNTP
#define CONFIG_CMD_USB
#if defined(CONFIG_PCI)
#define CONFIG_CMD_PCI
#endif
#undef CONFIG_WATCHDOG /* watchdog disabled */
/*
* Miscellaneous configurable options
*/
#define CFG_LONGHELP /* undef to save memory */
#define CFG_LOAD_ADDR 0x2000000 /* default load address */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
#endif
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buf Size */
#define CFG_MAXARGS 16 /* max number of command args */
#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
#define CFG_HZ 1000 /* decrementer freq: 1ms ticks */
/*
* For booting Linux, the board info and command line data
* have to be in the first 8 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization.
*/
#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
/*
* Internal Definitions
*
* Boot Flags
*/
#define BOOTFLAG_COLD 0x01 /* Power-On: Boot from FLASH */
#define BOOTFLAG_WARM 0x02 /* Software reboot */
#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port*/
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
#endif
#define CONFIG_LOADADDR 200000 /* default addr for tftp & bootm*/
#define CONFIG_BOOTDELAY 5 /* -1 disables auto-boot */
#define CONFIG_PREBOOT "echo;" \
"echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
"echo"
#undef CONFIG_BOOTARGS /* the boot command will set bootargs */
#define CONFIG_EXTRA_ENV_SETTINGS \
"bootfile=$hostname/uImage\0" \
"netdev=eth0\0" \
"consdev=ttyS0\0" \
"hostname=socrates\0" \
"nfsargs=setenv bootargs root=/dev/nfs rw " \
"nfsroot=$serverip:$rootpath\0" \
"ramargs=setenv bootargs root=/dev/ram rw\0" \
"addip=setenv bootargs $bootargs " \
"ip=$ipaddr:$serverip:$gatewayip:$netmask" \
":$hostname:$netdev:off panic=1\0" \
"addcons=setenv bootargs $bootargs " \
"console=$consdev,$baudrate\0" \
"flash_self=run ramargs addip addcons;" \
"bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \
"flash_nfs=run nfsargs addip addcons;" \
"bootm ${kernel_addr} - ${fdt_addr}\0" \
"net_nfs=tftp ${kernel_addr_r} ${bootfile}; " \
"tftp ${fdt_addr_r} ${fdt_file}; " \
"run nfsargs addip addcons;" \
"bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \
"fdt_file=$hostname/socrates.dtb\0" \
"fdt_addr_r=B00000\0" \
"fdt_addr=FC1E0000\0" \
"rootpath=/opt/eldk/ppc_85xx\0" \
"kernel_addr=FC000000\0" \
"kernel_addr_r=200000\0" \
"ramdisk_addr=FC200000\0" \
"ramdisk_addr_r=400000\0" \
"load=tftp 100000 $hostname/u-boot.bin\0" \
"update=protect off fffc0000 ffffffff;era fffc0000 ffffffff;" \
"cp.b 100000 fffc0000 40000;" \
"setenv filesize;saveenv\0" \
"upd=run load update\0" \
""
#define CONFIG_BOOTCOMMAND "run flash_self"
/* pass open firmware flat tree */
#define CONFIG_OF_LIBFDT 1
#define CONFIG_OF_BOARD_SETUP 1
/* USB support */
#define CONFIG_USB_OHCI_NEW 1
#define CONFIG_PCI_OHCI 1
#define CONFIG_PCI_OHCI_DEVNO 3 /* Number in PCI list */
#define CFG_USB_OHCI_MAX_ROOT_PORTS 15
#define CFG_USB_OHCI_SLOT_NAME "ohci_pci"
#define CFG_OHCI_SWAP_REG_ACCESS 1
#define CONFIG_DOS_PARTITION 1
#define CONFIG_USB_STORAGE 1
#endif /* __CONFIG_H */

2
include/logbuff.h
View File

@ -31,8 +31,6 @@
#define LOGBUFF_OVERHEAD (4096) /* Logbuffer overhead for extra info */
#define LOGBUFF_RESERVE (LOGBUFF_LEN+LOGBUFF_OVERHEAD)
#define LOGBUFF_INITIALIZED (1<<31)
/* The mapping used here has to be the same as in setup_ext_logbuff ()
in linux/kernel/printk */

4
include/post.h
View File

@ -43,6 +43,7 @@
#define POST_PREREL 0x1000 /* test runs before relocation */
#define POST_CRITICAL 0x2000 /* Use failbootcmd if test failed */
#define POST_STOP 0x4000 /* Interrupt POST sequence on fail */
#define POST_MEM (POST_RAM | POST_ROM)
#define POST_ALWAYS (POST_NORMAL | \
@ -94,7 +95,7 @@ extern int post_hotkeys_pressed(void);
#define CFG_POST_SPR 0x00000400
#define CFG_POST_SYSMON 0x00000800
#define CFG_POST_DSP 0x00001000
#define CFG_POST_CODEC 0x00002000
#define CFG_POST_OCM 0x00002000
#define CFG_POST_FPU 0x00004000
#define CFG_POST_ECC 0x00008000
#define CFG_POST_BSPEC1 0x00010000
@ -102,6 +103,7 @@ extern int post_hotkeys_pressed(void);
#define CFG_POST_BSPEC3 0x00040000
#define CFG_POST_BSPEC4 0x00080000
#define CFG_POST_BSPEC5 0x00100000
#define CFG_POST_CODEC 0x00200000
#endif /* CONFIG_POST */

2
include/virtex2.h
View File

@ -116,5 +116,3 @@ typedef struct {
{ Xilinx_Virtex2, iface, XILINX_XC2V10000_SIZE, fn_table, cookie }
#endif /* _VIRTEX2_H_ */
/* vim: set ts=4 tw=78: */

1
post/cpu/ppc4xx/Makefile
View File

@ -29,6 +29,7 @@ COBJS-$(CONFIG_HAS_POST) += cache.o
COBJS-$(CONFIG_HAS_POST) += denali_ecc.o
COBJS-$(CONFIG_HAS_POST) += ether.o
COBJS-$(CONFIG_HAS_POST) += fpu.o
COBJS-$(CONFIG_HAS_POST) += ocm.o
COBJS-$(CONFIG_HAS_POST) += spr.o
COBJS-$(CONFIG_HAS_POST) += uart.o
COBJS-$(CONFIG_HAS_POST) += watchdog.o

89
post/cpu/ppc4xx/ocm.c Normal file
View File

@ -0,0 +1,89 @@
/*
* (C) Copyright 2008 Ilya Yanok, EmCraft Systems, yanok@emcraft.com
*
* Developed for DENX Software Engineering GmbH
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
/*
* This test attempts to verify on-chip memory (OCM). Result is written
* to the scratch register and if test succeed it won't be run till next
* power on.
*/
#include <post.h>
#include <asm/io.h>
DECLARE_GLOBAL_DATA_PTR;
#define OCM_TEST_PATTERN1 0x55555555
#define OCM_TEST_PATTERN2 0xAAAAAAAA
#if CONFIG_POST & CFG_POST_OCM
static uint ocm_status_read(void)
{
return in_be32((void *)CFG_OCM_STATUS_ADDR) &
CFG_OCM_STATUS_MASK;
}
static void ocm_status_write(uint value)
{
out_be32((void *)CFG_OCM_STATUS_ADDR, value |
(in_be32((void *)CFG_OCM_STATUS_ADDR) &
~CFG_OCM_STATUS_MASK));
}
static inline int ocm_test_word(uint value, uint *address)
{
uint read_value;
*address = value;
sync();
read_value = *address;
return (read_value != value);
}
int ocm_post_test(int flags)
{
uint old_value;
int ret = 0;
uint *address = (uint*)CFG_OCM_BASE;
if (ocm_status_read() == CFG_OCM_STATUS_OK)
return 0;
for (; address < (uint*)(CFG_OCM_BASE + CFG_OCM_SIZE); address++) {
old_value = *address;
if (ocm_test_word(OCM_TEST_PATTERN1, address) ||
ocm_test_word(OCM_TEST_PATTERN2, address)) {
ret = 1;
*address = old_value;
printf("OCM POST failed at %p!\n", address);
break;
}
*address = old_value;
}
ocm_status_write(ret ? CFG_OCM_STATUS_FAIL : CFG_OCM_STATUS_OK);
return ret;
}
#endif /* CONFIG_POST & CFG_POST_OCM */

15
post/post.c
View File

@ -238,14 +238,20 @@ static int post_run_single (struct post_test *test,
if (test_flags & POST_PREREL) {
if ((*test->test) (flags) == 0)
post_log_mark_succ ( test->testid );
else if (test_flags & POST_CRITICAL)
else {
if (test_flags & POST_CRITICAL)
gd->flags |= GD_FLG_POSTFAIL;
if (test_flags & POST_STOP)
gd->flags |= GD_FLG_POSTSTOP;
}
} else {
if ((*test->test) (flags) != 0) {
post_log ("FAILED\n");
show_boot_progress (-32);
if (test_flags & POST_CRITICAL)
gd->flags |= GD_FLG_POSTFAIL;
if (test_flags & POST_STOP)
gd->flags |= GD_FLG_POSTSTOP;
}
else
post_log ("PASSED\n");
@ -271,6 +277,9 @@ int post_run (char *name, int flags)
if (name == NULL) {
unsigned int last;
if (gd->flags & GD_FLG_POSTSTOP)
return 0;
if (post_bootmode_get (&last) & POST_POWERTEST) {
if (last & POST_FAIL_SAVE) {
last &= ~POST_FAIL_SAVE;
@ -285,6 +294,8 @@ int post_run (char *name, int flags)
flags | POST_REBOOT, last);
for (i = last + 1; i < post_list_size; i++) {
if (gd->flags & GD_FLG_POSTSTOP)
break;
post_run_single (post_list + i,
test_flags[i],
flags, i);
@ -292,6 +303,8 @@ int post_run (char *name, int flags)
}
} else {
for (i = 0; i < post_list_size; i++) {
if (gd->flags & GD_FLG_POSTSTOP)
break;
post_run_single (post_list + i,
test_flags[i],
flags, i);

15
post/tests.c
View File

@ -29,6 +29,7 @@
#include <post.h>
extern int ocm_post_test (int flags);
extern int cache_post_test (int flags);
extern int watchdog_post_test (int flags);
extern int i2c_post_test (int flags);
@ -60,6 +61,18 @@ extern void sysmon_reloc (void);
struct post_test post_list[] =
{
#if CONFIG_POST & CFG_POST_OCM
{
"OCM test",
"ocm",
"This test checks on chip memory (OCM).",
POST_ROM | POST_ALWAYS | POST_PREREL | POST_CRITICAL | POST_STOP,
&ocm_post_test,
NULL,
NULL,
CFG_POST_OCM
},
#endif
#if CONFIG_POST & CFG_POST_CACHE
{
"Cache test",
@ -270,7 +283,7 @@ struct post_test post_list[] =
#if CONFIG_POST & CFG_POST_BSPEC4
CONFIG_POST_BSPEC4,
#endif
#if CONFIG_POST & CFG_POST_BSPEC4
#if CONFIG_POST & CFG_POST_BSPEC5
CONFIG_POST_BSPEC5,
#endif
};