mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-09-29 16:10:24 +09:00
Merge git://git.denx.de/u-boot-arc
This commit is contained in:
commit
10918c03a9
2
Kconfig
2
Kconfig
@ -139,7 +139,7 @@ config SYS_EXTRA_OPTIONS
|
|||||||
new boards should not use this option.
|
new boards should not use this option.
|
||||||
|
|
||||||
config SYS_TEXT_BASE
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config SYS_TEXT_BASE
|
||||||
depends on SPARC
|
depends on SPARC || ARC
|
||||||
hex "Text Base"
|
hex "Text Base"
|
||||||
help
|
help
|
||||||
TODO: Move CONFIG_SYS_TEXT_BASE for all the architecture
|
TODO: Move CONFIG_SYS_TEXT_BASE for all the architecture
|
||||||
|
@ -4,6 +4,7 @@ choice
|
|||||||
|
|
||||||
config ARC
|
config ARC
|
||||||
bool "ARC architecture"
|
bool "ARC architecture"
|
||||||
|
select HAVE_PRIVATE_LIBGCC
|
||||||
|
|
||||||
config ARM
|
config ARM
|
||||||
bool "ARM architecture"
|
bool "ARM architecture"
|
||||||
|
@ -4,9 +4,77 @@ menu "ARC architecture"
|
|||||||
config SYS_ARCH
|
config SYS_ARCH
|
||||||
default "arc"
|
default "arc"
|
||||||
|
|
||||||
|
config USE_PRIVATE_LIBGCC
|
||||||
|
default y
|
||||||
|
|
||||||
config SYS_CPU
|
config SYS_CPU
|
||||||
default "arcv1"
|
default "arcv1"
|
||||||
|
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||||||
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choice
|
||||||
|
prompt "CPU selection"
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||||||
|
default CPU_ARC770D
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||||||
|
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||||||
|
config CPU_ARC750D
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||||||
|
bool "ARC 750D"
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||||||
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select ARC_MMU_V2
|
||||||
|
help
|
||||||
|
Choose this option to build an U-Boot for ARC750D CPU.
|
||||||
|
|
||||||
|
config CPU_ARC770D
|
||||||
|
bool "ARC 770D"
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||||||
|
select ARC_MMU_V3
|
||||||
|
help
|
||||||
|
Choose this option to build an U-Boot for ARC770D CPU.
|
||||||
|
|
||||||
|
endchoice
|
||||||
|
|
||||||
|
choice
|
||||||
|
prompt "MMU Version"
|
||||||
|
default ARC_MMU_V3 if CPU_ARC770D
|
||||||
|
default ARC_MMU_V2 if CPU_ARC750D
|
||||||
|
|
||||||
|
config ARC_MMU_V2
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||||||
|
bool "MMU v2"
|
||||||
|
depends on CPU_ARC750D
|
||||||
|
help
|
||||||
|
Fixed the deficiency of v1 - possible thrashing in memcpy sceanrio
|
||||||
|
when 2 D-TLB and 1 I-TLB entries index into same 2way set.
|
||||||
|
|
||||||
|
config ARC_MMU_V3
|
||||||
|
bool "MMU v3"
|
||||||
|
depends on CPU_ARC770D
|
||||||
|
help
|
||||||
|
Introduced with ARC700 4.10: New Features
|
||||||
|
Variable Page size (1k-16k), var JTLB size 128 x (2 or 4)
|
||||||
|
Shared Address Spaces (SASID)
|
||||||
|
|
||||||
|
endchoice
|
||||||
|
|
||||||
|
config CPU_BIG_ENDIAN
|
||||||
|
bool "Enable Big Endian Mode"
|
||||||
|
default n
|
||||||
|
help
|
||||||
|
Build kernel for Big Endian Mode of ARC CPU
|
||||||
|
|
||||||
|
config SYS_ICACHE_OFF
|
||||||
|
bool "Do not use Instruction Cache"
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||||||
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default n
|
||||||
|
|
||||||
|
config SYS_DCACHE_OFF
|
||||||
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bool "Do not use Data Cache"
|
||||||
|
default n
|
||||||
|
|
||||||
|
config ARC_CACHE_LINE_SHIFT
|
||||||
|
int "Cache Line Length (as power of 2)"
|
||||||
|
range 5 7
|
||||||
|
default "6"
|
||||||
|
depends on !SYS_DCACHE_OFF || !SYS_DCACHE_OFF
|
||||||
|
help
|
||||||
|
Starting with ARC700 4.9, Cache line length is configurable,
|
||||||
|
This option specifies "N", with Line-len = 2 power N
|
||||||
|
So line lengths of 32, 64, 128 are specified by 5,6,7, respectively
|
||||||
|
Linux only supports same line lengths for I and D caches.
|
||||||
|
|
||||||
choice
|
choice
|
||||||
prompt "Target select"
|
prompt "Target select"
|
||||||
|
|
||||||
@ -16,9 +84,6 @@ config TARGET_TB100
|
|||||||
config TARGET_ARCANGEL4
|
config TARGET_ARCANGEL4
|
||||||
bool "Support arcangel4"
|
bool "Support arcangel4"
|
||||||
|
|
||||||
config TARGET_ARCANGEL4_BE
|
|
||||||
bool "Support arcangel4-be"
|
|
||||||
|
|
||||||
config TARGET_AXS101
|
config TARGET_AXS101
|
||||||
bool "Support axs101"
|
bool "Support axs101"
|
||||||
|
|
||||||
|
@ -4,17 +4,22 @@
|
|||||||
# SPDX-License-Identifier: GPL-2.0+
|
# SPDX-License-Identifier: GPL-2.0+
|
||||||
#
|
#
|
||||||
|
|
||||||
ifndef CONFIG_SYS_BIG_ENDIAN
|
ifndef CONFIG_CPU_BIG_ENDIAN
|
||||||
CONFIG_SYS_LITTLE_ENDIAN = 1
|
CONFIG_SYS_LITTLE_ENDIAN = 1
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||||||
|
else
|
||||||
|
CONFIG_SYS_BIG_ENDIAN = 1
|
||||||
endif
|
endif
|
||||||
|
|
||||||
ifdef CONFIG_SYS_LITTLE_ENDIAN
|
ifdef CONFIG_SYS_LITTLE_ENDIAN
|
||||||
ARC_CROSS_COMPILE := arc-buildroot-linux-uclibc-
|
ARC_CROSS_COMPILE := arc-buildroot-linux-uclibc-
|
||||||
|
PLATFORM_LDFLAGS += -EL
|
||||||
|
PLATFORM_CPPFLAGS += -mlittle-endian
|
||||||
endif
|
endif
|
||||||
|
|
||||||
ifdef CONFIG_SYS_BIG_ENDIAN
|
ifdef CONFIG_SYS_BIG_ENDIAN
|
||||||
ARC_CROSS_COMPILE := arceb-buildroot-linux-uclibc-
|
ARC_CROSS_COMPILE := arceb-buildroot-linux-uclibc-
|
||||||
PLATFORM_LDFLAGS += -EB
|
PLATFORM_LDFLAGS += -EB
|
||||||
|
PLATFORM_CPPFLAGS += -mbig-endian
|
||||||
endif
|
endif
|
||||||
|
|
||||||
ifeq ($(CROSS_COMPILE),)
|
ifeq ($(CROSS_COMPILE),)
|
||||||
@ -25,6 +30,14 @@ ifdef CONFIG_ARC_MMU_VER
|
|||||||
CONFIG_MMU = 1
|
CONFIG_MMU = 1
|
||||||
endif
|
endif
|
||||||
|
|
||||||
|
ifdef CONFIG_CPU_ARC750D
|
||||||
|
PLATFORM_CPPFLAGS += -marc700
|
||||||
|
endif
|
||||||
|
|
||||||
|
ifdef CONFIG_CPU_ARC770D
|
||||||
|
PLATFORM_CPPFLAGS += -marc700 -mlock -mswape
|
||||||
|
endif
|
||||||
|
|
||||||
PLATFORM_CPPFLAGS += -ffixed-r25 -D__ARC__ -gdwarf-2
|
PLATFORM_CPPFLAGS += -ffixed-r25 -D__ARC__ -gdwarf-2
|
||||||
|
|
||||||
# Needed for relocation
|
# Needed for relocation
|
||||||
|
@ -1,7 +0,0 @@
|
|||||||
#
|
|
||||||
# Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved.
|
|
||||||
#
|
|
||||||
# SPDX-License-Identifier: GPL-2.0+
|
|
||||||
#
|
|
||||||
|
|
||||||
PLATFORM_CPPFLAGS += -mA7
|
|
@ -7,6 +7,8 @@
|
|||||||
#ifndef _ASM_ARC_ARCREGS_H
|
#ifndef _ASM_ARC_ARCREGS_H
|
||||||
#define _ASM_ARC_ARCREGS_H
|
#define _ASM_ARC_ARCREGS_H
|
||||||
|
|
||||||
|
#include <asm/cache.h>
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* ARC architecture has additional address space - auxiliary registers.
|
* ARC architecture has additional address space - auxiliary registers.
|
||||||
* These registers are mostly used for configuration purposes.
|
* These registers are mostly used for configuration purposes.
|
||||||
@ -21,7 +23,7 @@
|
|||||||
#define ARC_AUX_IC_IVIC 0x10
|
#define ARC_AUX_IC_IVIC 0x10
|
||||||
#define ARC_AUX_IC_CTRL 0x11
|
#define ARC_AUX_IC_CTRL 0x11
|
||||||
#define ARC_AUX_IC_IVIL 0x19
|
#define ARC_AUX_IC_IVIL 0x19
|
||||||
#if (CONFIG_ARC_MMU_VER > 2)
|
#if (CONFIG_ARC_MMU_VER == 3)
|
||||||
#define ARC_AUX_IC_PTAG 0x1E
|
#define ARC_AUX_IC_PTAG 0x1E
|
||||||
#endif
|
#endif
|
||||||
#define ARC_BCR_IC_BUILD 0x77
|
#define ARC_BCR_IC_BUILD 0x77
|
||||||
@ -40,7 +42,7 @@
|
|||||||
#define ARC_AUX_DC_IVDL 0x4A
|
#define ARC_AUX_DC_IVDL 0x4A
|
||||||
#define ARC_AUX_DC_FLSH 0x4B
|
#define ARC_AUX_DC_FLSH 0x4B
|
||||||
#define ARC_AUX_DC_FLDL 0x4C
|
#define ARC_AUX_DC_FLDL 0x4C
|
||||||
#if (CONFIG_ARC_MMU_VER > 2)
|
#if (CONFIG_ARC_MMU_VER == 3)
|
||||||
#define ARC_AUX_DC_PTAG 0x5C
|
#define ARC_AUX_DC_PTAG 0x5C
|
||||||
#endif
|
#endif
|
||||||
#define ARC_BCR_DC_BUILD 0x72
|
#define ARC_BCR_DC_BUILD 0x72
|
||||||
|
@ -9,15 +9,18 @@
|
|||||||
|
|
||||||
#include <config.h>
|
#include <config.h>
|
||||||
|
|
||||||
/*
|
#ifdef CONFIG_ARC_CACHE_LINE_SHIFT
|
||||||
* The current upper bound for ARC L1 data cache line sizes is 128 bytes.
|
#define CONFIG_SYS_CACHELINE_SIZE (1 << CONFIG_ARC_CACHE_LINE_SHIFT)
|
||||||
* We use that value for aligning DMA buffers unless the board config has
|
#define ARCH_DMA_MINALIGN CONFIG_SYS_CACHELINE_SIZE
|
||||||
* specified an alternate cache line size.
|
|
||||||
*/
|
|
||||||
#ifdef CONFIG_SYS_CACHELINE_SIZE
|
|
||||||
#define ARCH_DMA_MINALIGN CONFIG_SYS_CACHELINE_SIZE
|
|
||||||
#else
|
#else
|
||||||
#define ARCH_DMA_MINALIGN 128
|
/* Satisfy users of ARCH_DMA_MINALIGN */
|
||||||
|
#define ARCH_DMA_MINALIGN 128
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if defined(CONFIG_ARC_MMU_V2)
|
||||||
|
#define CONFIG_ARC_MMU_VER 2
|
||||||
|
#elif defined(CONFIG_ARC_MMU_V3)
|
||||||
|
#define CONFIG_ARC_MMU_VER 3
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
#endif /* __ASM_ARC_CACHE_H */
|
#endif /* __ASM_ARC_CACHE_H */
|
||||||
|
@ -7,8 +7,10 @@
|
|||||||
#ifndef __ASM_ARC_CONFIG_H_
|
#ifndef __ASM_ARC_CONFIG_H_
|
||||||
#define __ASM_ARC_CONFIG_H_
|
#define __ASM_ARC_CONFIG_H_
|
||||||
|
|
||||||
|
#define CONFIG_SYS_GENERIC_BOARD
|
||||||
#define CONFIG_SYS_GENERIC_GLOBAL_DATA
|
#define CONFIG_SYS_GENERIC_GLOBAL_DATA
|
||||||
#define CONFIG_SYS_BOOT_RAMDISK_HIGH
|
#define CONFIG_SYS_BOOT_RAMDISK_HIGH
|
||||||
|
#define CONFIG_ARCH_EARLY_INIT_R
|
||||||
|
|
||||||
#define CONFIG_LMB
|
#define CONFIG_LMB
|
||||||
|
|
||||||
|
@ -20,3 +20,5 @@ obj-y += reset.o
|
|||||||
obj-y += timer.o
|
obj-y += timer.o
|
||||||
|
|
||||||
obj-$(CONFIG_CMD_BOOTM) += bootm.o
|
obj-$(CONFIG_CMD_BOOTM) += bootm.o
|
||||||
|
|
||||||
|
lib-$(CONFIG_USE_PRIVATE_LIBGCC) += _millicodethunk.o libgcc2.o
|
||||||
|
226
arch/arc/lib/_millicodethunk.S
Normal file
226
arch/arc/lib/_millicodethunk.S
Normal file
@ -0,0 +1,226 @@
|
|||||||
|
/*
|
||||||
|
* Copyright (C) 1995, 1997, 2007-2013 Free Software Foundation, Inc.
|
||||||
|
*
|
||||||
|
* SPDX-License-Identifier: GPL-2.0+
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* ANSI concatenation macros. */
|
||||||
|
|
||||||
|
#define CONCAT1(a, b) CONCAT2(a, b)
|
||||||
|
#define CONCAT2(a, b) a ## b
|
||||||
|
|
||||||
|
/* Use the right prefix for global labels. */
|
||||||
|
|
||||||
|
#define SYM(x) CONCAT1 (__USER_LABEL_PREFIX__, x)
|
||||||
|
|
||||||
|
#ifndef WORKING_ASSEMBLER
|
||||||
|
#define abs_l abs
|
||||||
|
#define asl_l asl
|
||||||
|
#define mov_l mov
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#define FUNC(X) .type SYM(X),@function
|
||||||
|
#define HIDDEN_FUNC(X) FUNC(X)` .hidden X
|
||||||
|
#define ENDFUNC0(X) .Lfe_##X: .size X,.Lfe_##X-X
|
||||||
|
#define ENDFUNC(X) ENDFUNC0(X)
|
||||||
|
|
||||||
|
.section .text
|
||||||
|
.align 4
|
||||||
|
.global SYM(__st_r13_to_r15)
|
||||||
|
.global SYM(__st_r13_to_r16)
|
||||||
|
.global SYM(__st_r13_to_r17)
|
||||||
|
.global SYM(__st_r13_to_r18)
|
||||||
|
.global SYM(__st_r13_to_r19)
|
||||||
|
.global SYM(__st_r13_to_r20)
|
||||||
|
.global SYM(__st_r13_to_r21)
|
||||||
|
.global SYM(__st_r13_to_r22)
|
||||||
|
.global SYM(__st_r13_to_r23)
|
||||||
|
.global SYM(__st_r13_to_r24)
|
||||||
|
.global SYM(__st_r13_to_r25)
|
||||||
|
HIDDEN_FUNC(__st_r13_to_r15)
|
||||||
|
HIDDEN_FUNC(__st_r13_to_r16)
|
||||||
|
HIDDEN_FUNC(__st_r13_to_r17)
|
||||||
|
HIDDEN_FUNC(__st_r13_to_r18)
|
||||||
|
HIDDEN_FUNC(__st_r13_to_r19)
|
||||||
|
HIDDEN_FUNC(__st_r13_to_r20)
|
||||||
|
HIDDEN_FUNC(__st_r13_to_r21)
|
||||||
|
HIDDEN_FUNC(__st_r13_to_r22)
|
||||||
|
HIDDEN_FUNC(__st_r13_to_r23)
|
||||||
|
HIDDEN_FUNC(__st_r13_to_r24)
|
||||||
|
HIDDEN_FUNC(__st_r13_to_r25)
|
||||||
|
.align 4
|
||||||
|
SYM(__st_r13_to_r25):
|
||||||
|
st r25, [sp,48]
|
||||||
|
SYM(__st_r13_to_r24):
|
||||||
|
st r24, [sp,44]
|
||||||
|
SYM(__st_r13_to_r23):
|
||||||
|
st r23, [sp,40]
|
||||||
|
SYM(__st_r13_to_r22):
|
||||||
|
st r22, [sp,36]
|
||||||
|
SYM(__st_r13_to_r21):
|
||||||
|
st r21, [sp,32]
|
||||||
|
SYM(__st_r13_to_r20):
|
||||||
|
st r20, [sp,28]
|
||||||
|
SYM(__st_r13_to_r19):
|
||||||
|
st r19, [sp,24]
|
||||||
|
SYM(__st_r13_to_r18):
|
||||||
|
st r18, [sp,20]
|
||||||
|
SYM(__st_r13_to_r17):
|
||||||
|
st r17, [sp,16]
|
||||||
|
SYM(__st_r13_to_r16):
|
||||||
|
st r16, [sp,12]
|
||||||
|
SYM(__st_r13_to_r15):
|
||||||
|
#ifdef __ARC700__
|
||||||
|
st r15, [sp,8] ; minimum function size to avoid stall: 6 bytes.
|
||||||
|
#else
|
||||||
|
st_s r15, [sp,8]
|
||||||
|
#endif
|
||||||
|
st_s r14, [sp,4]
|
||||||
|
j_s.d [%blink]
|
||||||
|
st_s r13, [sp,0]
|
||||||
|
ENDFUNC(__st_r13_to_r15)
|
||||||
|
ENDFUNC(__st_r13_to_r16)
|
||||||
|
ENDFUNC(__st_r13_to_r17)
|
||||||
|
ENDFUNC(__st_r13_to_r18)
|
||||||
|
ENDFUNC(__st_r13_to_r19)
|
||||||
|
ENDFUNC(__st_r13_to_r20)
|
||||||
|
ENDFUNC(__st_r13_to_r21)
|
||||||
|
ENDFUNC(__st_r13_to_r22)
|
||||||
|
ENDFUNC(__st_r13_to_r23)
|
||||||
|
ENDFUNC(__st_r13_to_r24)
|
||||||
|
ENDFUNC(__st_r13_to_r25)
|
||||||
|
|
||||||
|
.section .text
|
||||||
|
.align 4
|
||||||
|
; ==================================
|
||||||
|
; the loads
|
||||||
|
|
||||||
|
.global SYM(__ld_r13_to_r15)
|
||||||
|
.global SYM(__ld_r13_to_r16)
|
||||||
|
.global SYM(__ld_r13_to_r17)
|
||||||
|
.global SYM(__ld_r13_to_r18)
|
||||||
|
.global SYM(__ld_r13_to_r19)
|
||||||
|
.global SYM(__ld_r13_to_r20)
|
||||||
|
.global SYM(__ld_r13_to_r21)
|
||||||
|
.global SYM(__ld_r13_to_r22)
|
||||||
|
.global SYM(__ld_r13_to_r23)
|
||||||
|
.global SYM(__ld_r13_to_r24)
|
||||||
|
.global SYM(__ld_r13_to_r25)
|
||||||
|
HIDDEN_FUNC(__ld_r13_to_r15)
|
||||||
|
HIDDEN_FUNC(__ld_r13_to_r16)
|
||||||
|
HIDDEN_FUNC(__ld_r13_to_r17)
|
||||||
|
HIDDEN_FUNC(__ld_r13_to_r18)
|
||||||
|
HIDDEN_FUNC(__ld_r13_to_r19)
|
||||||
|
HIDDEN_FUNC(__ld_r13_to_r20)
|
||||||
|
HIDDEN_FUNC(__ld_r13_to_r21)
|
||||||
|
HIDDEN_FUNC(__ld_r13_to_r22)
|
||||||
|
HIDDEN_FUNC(__ld_r13_to_r23)
|
||||||
|
HIDDEN_FUNC(__ld_r13_to_r24)
|
||||||
|
HIDDEN_FUNC(__ld_r13_to_r25)
|
||||||
|
SYM(__ld_r13_to_r25):
|
||||||
|
ld r25, [sp,48]
|
||||||
|
SYM(__ld_r13_to_r24):
|
||||||
|
ld r24, [sp,44]
|
||||||
|
SYM(__ld_r13_to_r23):
|
||||||
|
ld r23, [sp,40]
|
||||||
|
SYM(__ld_r13_to_r22):
|
||||||
|
ld r22, [sp,36]
|
||||||
|
SYM(__ld_r13_to_r21):
|
||||||
|
ld r21, [sp,32]
|
||||||
|
SYM(__ld_r13_to_r20):
|
||||||
|
ld r20, [sp,28]
|
||||||
|
SYM(__ld_r13_to_r19):
|
||||||
|
ld r19, [sp,24]
|
||||||
|
SYM(__ld_r13_to_r18):
|
||||||
|
ld r18, [sp,20]
|
||||||
|
SYM(__ld_r13_to_r17):
|
||||||
|
ld r17, [sp,16]
|
||||||
|
SYM(__ld_r13_to_r16):
|
||||||
|
ld r16, [sp,12]
|
||||||
|
SYM(__ld_r13_to_r15):
|
||||||
|
#ifdef __ARC700__
|
||||||
|
ld r15, [sp,8] ; minimum function size to avoid stall: 6 bytes.
|
||||||
|
#else
|
||||||
|
ld_s r15, [sp,8]
|
||||||
|
#endif
|
||||||
|
ld_s r14, [sp,4]
|
||||||
|
j_s.d [%blink]
|
||||||
|
ld_s r13, [sp,0]
|
||||||
|
ENDFUNC(__ld_r13_to_r15)
|
||||||
|
ENDFUNC(__ld_r13_to_r16)
|
||||||
|
ENDFUNC(__ld_r13_to_r17)
|
||||||
|
ENDFUNC(__ld_r13_to_r18)
|
||||||
|
ENDFUNC(__ld_r13_to_r19)
|
||||||
|
ENDFUNC(__ld_r13_to_r20)
|
||||||
|
ENDFUNC(__ld_r13_to_r21)
|
||||||
|
ENDFUNC(__ld_r13_to_r22)
|
||||||
|
ENDFUNC(__ld_r13_to_r23)
|
||||||
|
ENDFUNC(__ld_r13_to_r24)
|
||||||
|
ENDFUNC(__ld_r13_to_r25)
|
||||||
|
|
||||||
|
.global SYM(__ld_r13_to_r14_ret)
|
||||||
|
.global SYM(__ld_r13_to_r15_ret)
|
||||||
|
.global SYM(__ld_r13_to_r16_ret)
|
||||||
|
.global SYM(__ld_r13_to_r17_ret)
|
||||||
|
.global SYM(__ld_r13_to_r18_ret)
|
||||||
|
.global SYM(__ld_r13_to_r19_ret)
|
||||||
|
.global SYM(__ld_r13_to_r20_ret)
|
||||||
|
.global SYM(__ld_r13_to_r21_ret)
|
||||||
|
.global SYM(__ld_r13_to_r22_ret)
|
||||||
|
.global SYM(__ld_r13_to_r23_ret)
|
||||||
|
.global SYM(__ld_r13_to_r24_ret)
|
||||||
|
.global SYM(__ld_r13_to_r25_ret)
|
||||||
|
HIDDEN_FUNC(__ld_r13_to_r14_ret)
|
||||||
|
HIDDEN_FUNC(__ld_r13_to_r15_ret)
|
||||||
|
HIDDEN_FUNC(__ld_r13_to_r16_ret)
|
||||||
|
HIDDEN_FUNC(__ld_r13_to_r17_ret)
|
||||||
|
HIDDEN_FUNC(__ld_r13_to_r18_ret)
|
||||||
|
HIDDEN_FUNC(__ld_r13_to_r19_ret)
|
||||||
|
HIDDEN_FUNC(__ld_r13_to_r20_ret)
|
||||||
|
HIDDEN_FUNC(__ld_r13_to_r21_ret)
|
||||||
|
HIDDEN_FUNC(__ld_r13_to_r22_ret)
|
||||||
|
HIDDEN_FUNC(__ld_r13_to_r23_ret)
|
||||||
|
HIDDEN_FUNC(__ld_r13_to_r24_ret)
|
||||||
|
HIDDEN_FUNC(__ld_r13_to_r25_ret)
|
||||||
|
.section .text
|
||||||
|
.align 4
|
||||||
|
SYM(__ld_r13_to_r25_ret):
|
||||||
|
ld r25, [sp,48]
|
||||||
|
SYM(__ld_r13_to_r24_ret):
|
||||||
|
ld r24, [sp,44]
|
||||||
|
SYM(__ld_r13_to_r23_ret):
|
||||||
|
ld r23, [sp,40]
|
||||||
|
SYM(__ld_r13_to_r22_ret):
|
||||||
|
ld r22, [sp,36]
|
||||||
|
SYM(__ld_r13_to_r21_ret):
|
||||||
|
ld r21, [sp,32]
|
||||||
|
SYM(__ld_r13_to_r20_ret):
|
||||||
|
ld r20, [sp,28]
|
||||||
|
SYM(__ld_r13_to_r19_ret):
|
||||||
|
ld r19, [sp,24]
|
||||||
|
SYM(__ld_r13_to_r18_ret):
|
||||||
|
ld r18, [sp,20]
|
||||||
|
SYM(__ld_r13_to_r17_ret):
|
||||||
|
ld r17, [sp,16]
|
||||||
|
SYM(__ld_r13_to_r16_ret):
|
||||||
|
ld r16, [sp,12]
|
||||||
|
SYM(__ld_r13_to_r15_ret):
|
||||||
|
ld r15, [sp,8]
|
||||||
|
SYM(__ld_r13_to_r14_ret):
|
||||||
|
ld blink,[sp,r12]
|
||||||
|
ld_s r14, [sp,4]
|
||||||
|
ld.ab r13, [sp,r12]
|
||||||
|
j_s.d [%blink]
|
||||||
|
add_s sp,sp,4
|
||||||
|
ENDFUNC(__ld_r13_to_r14_ret)
|
||||||
|
ENDFUNC(__ld_r13_to_r15_ret)
|
||||||
|
ENDFUNC(__ld_r13_to_r16_ret)
|
||||||
|
ENDFUNC(__ld_r13_to_r17_ret)
|
||||||
|
ENDFUNC(__ld_r13_to_r18_ret)
|
||||||
|
ENDFUNC(__ld_r13_to_r19_ret)
|
||||||
|
ENDFUNC(__ld_r13_to_r20_ret)
|
||||||
|
ENDFUNC(__ld_r13_to_r21_ret)
|
||||||
|
ENDFUNC(__ld_r13_to_r22_ret)
|
||||||
|
ENDFUNC(__ld_r13_to_r23_ret)
|
||||||
|
ENDFUNC(__ld_r13_to_r24_ret)
|
||||||
|
ENDFUNC(__ld_r13_to_r25_ret)
|
@ -6,6 +6,7 @@
|
|||||||
|
|
||||||
#include <config.h>
|
#include <config.h>
|
||||||
#include <asm/arcregs.h>
|
#include <asm/arcregs.h>
|
||||||
|
#include <asm/cache.h>
|
||||||
|
|
||||||
/* Bit values in IC_CTRL */
|
/* Bit values in IC_CTRL */
|
||||||
#define IC_CTRL_CACHE_DISABLE (1 << 0)
|
#define IC_CTRL_CACHE_DISABLE (1 << 0)
|
||||||
@ -101,7 +102,7 @@ void flush_dcache_all(void)
|
|||||||
#ifndef CONFIG_SYS_DCACHE_OFF
|
#ifndef CONFIG_SYS_DCACHE_OFF
|
||||||
static void dcache_flush_line(unsigned addr)
|
static void dcache_flush_line(unsigned addr)
|
||||||
{
|
{
|
||||||
#if (CONFIG_ARC_MMU_VER > 2)
|
#if (CONFIG_ARC_MMU_VER == 3)
|
||||||
write_aux_reg(ARC_AUX_DC_PTAG, addr);
|
write_aux_reg(ARC_AUX_DC_PTAG, addr);
|
||||||
#endif
|
#endif
|
||||||
write_aux_reg(ARC_AUX_DC_FLDL, addr);
|
write_aux_reg(ARC_AUX_DC_FLDL, addr);
|
||||||
@ -115,7 +116,7 @@ static void dcache_flush_line(unsigned addr)
|
|||||||
* Invalidate I$ for addresses range just flushed from D$.
|
* Invalidate I$ for addresses range just flushed from D$.
|
||||||
* If we try to execute data flushed above it will be valid/correct
|
* If we try to execute data flushed above it will be valid/correct
|
||||||
*/
|
*/
|
||||||
#if (CONFIG_ARC_MMU_VER > 2)
|
#if (CONFIG_ARC_MMU_VER == 3)
|
||||||
write_aux_reg(ARC_AUX_IC_PTAG, addr);
|
write_aux_reg(ARC_AUX_IC_PTAG, addr);
|
||||||
#endif
|
#endif
|
||||||
write_aux_reg(ARC_AUX_IC_IVIL, addr);
|
write_aux_reg(ARC_AUX_IC_IVIL, addr);
|
||||||
@ -145,7 +146,7 @@ void invalidate_dcache_range(unsigned long start, unsigned long end)
|
|||||||
end = end & (~(CONFIG_SYS_CACHELINE_SIZE - 1));
|
end = end & (~(CONFIG_SYS_CACHELINE_SIZE - 1));
|
||||||
|
|
||||||
for (addr = start; addr <= end; addr += CONFIG_SYS_CACHELINE_SIZE) {
|
for (addr = start; addr <= end; addr += CONFIG_SYS_CACHELINE_SIZE) {
|
||||||
#if (CONFIG_ARC_MMU_VER > 2)
|
#if (CONFIG_ARC_MMU_VER == 3)
|
||||||
write_aux_reg(ARC_AUX_DC_PTAG, addr);
|
write_aux_reg(ARC_AUX_DC_PTAG, addr);
|
||||||
#endif
|
#endif
|
||||||
write_aux_reg(ARC_AUX_DC_IVDL, addr);
|
write_aux_reg(ARC_AUX_DC_IVDL, addr);
|
||||||
|
161
arch/arc/lib/libgcc2.c
Normal file
161
arch/arc/lib/libgcc2.c
Normal file
@ -0,0 +1,161 @@
|
|||||||
|
/*
|
||||||
|
* Copyright (C) 1989-2013 Free Software Foundation, Inc.
|
||||||
|
*
|
||||||
|
* SPDX-License-Identifier: GPL-2.0+
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include "libgcc2.h"
|
||||||
|
|
||||||
|
DWtype
|
||||||
|
__ashldi3(DWtype u, shift_count_type b)
|
||||||
|
{
|
||||||
|
if (b == 0)
|
||||||
|
return u;
|
||||||
|
|
||||||
|
const DWunion uu = {.ll = u};
|
||||||
|
const shift_count_type bm = W_TYPE_SIZE - b;
|
||||||
|
DWunion w;
|
||||||
|
|
||||||
|
if (bm <= 0) {
|
||||||
|
w.s.low = 0;
|
||||||
|
w.s.high = (UWtype)uu.s.low << -bm;
|
||||||
|
} else {
|
||||||
|
const UWtype carries = (UWtype) uu.s.low >> bm;
|
||||||
|
|
||||||
|
w.s.low = (UWtype)uu.s.low << b;
|
||||||
|
w.s.high = ((UWtype)uu.s.high << b) | carries;
|
||||||
|
}
|
||||||
|
|
||||||
|
return w.ll;
|
||||||
|
}
|
||||||
|
|
||||||
|
DWtype
|
||||||
|
__ashrdi3(DWtype u, shift_count_type b)
|
||||||
|
{
|
||||||
|
if (b == 0)
|
||||||
|
return u;
|
||||||
|
|
||||||
|
const DWunion uu = {.ll = u};
|
||||||
|
const shift_count_type bm = W_TYPE_SIZE - b;
|
||||||
|
DWunion w;
|
||||||
|
|
||||||
|
if (bm <= 0) {
|
||||||
|
/* w.s.high = 1..1 or 0..0 */
|
||||||
|
w.s.high = uu.s.high >> (W_TYPE_SIZE - 1);
|
||||||
|
w.s.low = uu.s.high >> -bm;
|
||||||
|
} else {
|
||||||
|
const UWtype carries = (UWtype) uu.s.high << bm;
|
||||||
|
|
||||||
|
w.s.high = uu.s.high >> b;
|
||||||
|
w.s.low = ((UWtype)uu.s.low >> b) | carries;
|
||||||
|
}
|
||||||
|
|
||||||
|
return w.ll;
|
||||||
|
}
|
||||||
|
|
||||||
|
DWtype
|
||||||
|
__lshrdi3(DWtype u, shift_count_type b)
|
||||||
|
{
|
||||||
|
if (b == 0)
|
||||||
|
return u;
|
||||||
|
|
||||||
|
const DWunion uu = {.ll = u};
|
||||||
|
const shift_count_type bm = W_TYPE_SIZE - b;
|
||||||
|
DWunion w;
|
||||||
|
|
||||||
|
if (bm <= 0) {
|
||||||
|
w.s.high = 0;
|
||||||
|
w.s.low = (UWtype)uu.s.high >> -bm;
|
||||||
|
} else {
|
||||||
|
const UWtype carries = (UWtype)uu.s.high << bm;
|
||||||
|
|
||||||
|
w.s.high = (UWtype)uu.s.high >> b;
|
||||||
|
w.s.low = ((UWtype)uu.s.low >> b) | carries;
|
||||||
|
}
|
||||||
|
|
||||||
|
return w.ll;
|
||||||
|
}
|
||||||
|
|
||||||
|
unsigned long
|
||||||
|
udivmodsi4(unsigned long num, unsigned long den, int modwanted)
|
||||||
|
{
|
||||||
|
unsigned long bit = 1;
|
||||||
|
unsigned long res = 0;
|
||||||
|
|
||||||
|
while (den < num && bit && !(den & (1L<<31))) {
|
||||||
|
den <<= 1;
|
||||||
|
bit <<= 1;
|
||||||
|
}
|
||||||
|
|
||||||
|
while (bit) {
|
||||||
|
if (num >= den) {
|
||||||
|
num -= den;
|
||||||
|
res |= bit;
|
||||||
|
}
|
||||||
|
bit >>= 1;
|
||||||
|
den >>= 1;
|
||||||
|
}
|
||||||
|
|
||||||
|
if (modwanted)
|
||||||
|
return num;
|
||||||
|
|
||||||
|
return res;
|
||||||
|
}
|
||||||
|
|
||||||
|
long
|
||||||
|
__divsi3(long a, long b)
|
||||||
|
{
|
||||||
|
int neg = 0;
|
||||||
|
long res;
|
||||||
|
|
||||||
|
if (a < 0) {
|
||||||
|
a = -a;
|
||||||
|
neg = !neg;
|
||||||
|
}
|
||||||
|
|
||||||
|
if (b < 0) {
|
||||||
|
b = -b;
|
||||||
|
neg = !neg;
|
||||||
|
}
|
||||||
|
|
||||||
|
res = udivmodsi4(a, b, 0);
|
||||||
|
|
||||||
|
if (neg)
|
||||||
|
res = -res;
|
||||||
|
|
||||||
|
return res;
|
||||||
|
}
|
||||||
|
|
||||||
|
long
|
||||||
|
__modsi3(long a, long b)
|
||||||
|
{
|
||||||
|
int neg = 0;
|
||||||
|
long res;
|
||||||
|
|
||||||
|
if (a < 0) {
|
||||||
|
a = -a;
|
||||||
|
neg = 1;
|
||||||
|
}
|
||||||
|
|
||||||
|
if (b < 0)
|
||||||
|
b = -b;
|
||||||
|
|
||||||
|
res = udivmodsi4(a, b, 1);
|
||||||
|
|
||||||
|
if (neg)
|
||||||
|
res = -res;
|
||||||
|
|
||||||
|
return res;
|
||||||
|
}
|
||||||
|
|
||||||
|
long
|
||||||
|
__udivsi3(long a, long b)
|
||||||
|
{
|
||||||
|
return udivmodsi4(a, b, 0);
|
||||||
|
}
|
||||||
|
|
||||||
|
long
|
||||||
|
__umodsi3(long a, long b)
|
||||||
|
{
|
||||||
|
return udivmodsi4(a, b, 1);
|
||||||
|
}
|
132
arch/arc/lib/libgcc2.h
Normal file
132
arch/arc/lib/libgcc2.h
Normal file
@ -0,0 +1,132 @@
|
|||||||
|
/*
|
||||||
|
* Copyright (C) 1989-2013 Free Software Foundation, Inc.
|
||||||
|
*
|
||||||
|
* SPDX-License-Identifier: GPL-2.0+
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef __ASM_LIBGCC_H
|
||||||
|
#define __ASM_LIBGCC_H
|
||||||
|
|
||||||
|
#define UNITS_PER_WORD 4 /* for ARC */
|
||||||
|
#define BITS_PER_UNIT 8 /* for ARC */
|
||||||
|
|
||||||
|
#define W_TYPE_SIZE (4 * BITS_PER_UNIT)
|
||||||
|
|
||||||
|
#define MIN_UNITS_PER_WORD UNITS_PER_WORD
|
||||||
|
|
||||||
|
/* Work out the largest "word" size that we can deal with on this target. */
|
||||||
|
#if MIN_UNITS_PER_WORD > 4
|
||||||
|
# define LIBGCC2_MAX_UNITS_PER_WORD 8
|
||||||
|
#elif (MIN_UNITS_PER_WORD > 2 \
|
||||||
|
|| (MIN_UNITS_PER_WORD > 1 && __SIZEOF_LONG_LONG__ > 4))
|
||||||
|
# define LIBGCC2_MAX_UNITS_PER_WORD 4
|
||||||
|
#else
|
||||||
|
# define LIBGCC2_MAX_UNITS_PER_WORD MIN_UNITS_PER_WORD
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* Work out what word size we are using for this compilation.
|
||||||
|
The value can be set on the command line. */
|
||||||
|
#ifndef LIBGCC2_UNITS_PER_WORD
|
||||||
|
#define LIBGCC2_UNITS_PER_WORD LIBGCC2_MAX_UNITS_PER_WORD
|
||||||
|
#endif
|
||||||
|
|
||||||
|
typedef int QItype __attribute__ ((mode (QI)));
|
||||||
|
typedef unsigned int UQItype __attribute__ ((mode (QI)));
|
||||||
|
typedef int HItype __attribute__ ((mode (HI)));
|
||||||
|
typedef unsigned int UHItype __attribute__ ((mode (HI)));
|
||||||
|
#if MIN_UNITS_PER_WORD > 1
|
||||||
|
/* These typedefs are usually forbidden on dsp's with UNITS_PER_WORD 1. */
|
||||||
|
typedef int SItype __attribute__ ((mode (SI)));
|
||||||
|
typedef unsigned int USItype __attribute__ ((mode (SI)));
|
||||||
|
#if __SIZEOF_LONG_LONG__ > 4
|
||||||
|
/* These typedefs are usually forbidden on archs with UNITS_PER_WORD 2. */
|
||||||
|
typedef int DItype __attribute__ ((mode (DI)));
|
||||||
|
typedef unsigned int UDItype __attribute__ ((mode (DI)));
|
||||||
|
#if MIN_UNITS_PER_WORD > 4
|
||||||
|
/* These typedefs are usually forbidden on archs with UNITS_PER_WORD 4. */
|
||||||
|
typedef int TItype __attribute__ ((mode (TI)));
|
||||||
|
typedef unsigned int UTItype __attribute__ ((mode (TI)));
|
||||||
|
#endif
|
||||||
|
#endif
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if LIBGCC2_UNITS_PER_WORD == 8
|
||||||
|
#define W_TYPE_SIZE (8 * BITS_PER_UNIT)
|
||||||
|
#define Wtype DItype
|
||||||
|
#define UWtype UDItype
|
||||||
|
#define HWtype DItype
|
||||||
|
#define UHWtype UDItype
|
||||||
|
#define DWtype TItype
|
||||||
|
#define UDWtype UTItype
|
||||||
|
#ifdef LIBGCC2_GNU_PREFIX
|
||||||
|
#define __NW(a,b) __gnu_ ## a ## di ## b
|
||||||
|
#define __NDW(a,b) __gnu_ ## a ## ti ## b
|
||||||
|
#else
|
||||||
|
#define __NW(a,b) __ ## a ## di ## b
|
||||||
|
#define __NDW(a,b) __ ## a ## ti ## b
|
||||||
|
#endif
|
||||||
|
#elif LIBGCC2_UNITS_PER_WORD == 4
|
||||||
|
#define W_TYPE_SIZE (4 * BITS_PER_UNIT)
|
||||||
|
#define Wtype SItype
|
||||||
|
#define UWtype USItype
|
||||||
|
#define HWtype SItype
|
||||||
|
#define UHWtype USItype
|
||||||
|
#define DWtype DItype
|
||||||
|
#define UDWtype UDItype
|
||||||
|
#ifdef LIBGCC2_GNU_PREFIX
|
||||||
|
#define __NW(a,b) __gnu_ ## a ## si ## b
|
||||||
|
#define __NDW(a,b) __gnu_ ## a ## di ## b
|
||||||
|
#else
|
||||||
|
#define __NW(a,b) __ ## a ## si ## b
|
||||||
|
#define __NDW(a,b) __ ## a ## di ## b
|
||||||
|
#endif
|
||||||
|
#elif LIBGCC2_UNITS_PER_WORD == 2
|
||||||
|
#define W_TYPE_SIZE (2 * BITS_PER_UNIT)
|
||||||
|
#define Wtype HItype
|
||||||
|
#define UWtype UHItype
|
||||||
|
#define HWtype HItype
|
||||||
|
#define UHWtype UHItype
|
||||||
|
#define DWtype SItype
|
||||||
|
#define UDWtype USItype
|
||||||
|
#ifdef LIBGCC2_GNU_PREFIX
|
||||||
|
#define __NW(a,b) __gnu_ ## a ## hi ## b
|
||||||
|
#define __NDW(a,b) __gnu_ ## a ## si ## b
|
||||||
|
#else
|
||||||
|
#define __NW(a,b) __ ## a ## hi ## b
|
||||||
|
#define __NDW(a,b) __ ## a ## si ## b
|
||||||
|
#endif
|
||||||
|
#else
|
||||||
|
#define W_TYPE_SIZE BITS_PER_UNIT
|
||||||
|
#define Wtype QItype
|
||||||
|
#define UWtype UQItype
|
||||||
|
#define HWtype QItype
|
||||||
|
#define UHWtype UQItype
|
||||||
|
#define DWtype HItype
|
||||||
|
#define UDWtype UHItype
|
||||||
|
#ifdef LIBGCC2_GNU_PREFIX
|
||||||
|
#define __NW(a,b) __gnu_ ## a ## qi ## b
|
||||||
|
#define __NDW(a,b) __gnu_ ## a ## hi ## b
|
||||||
|
#else
|
||||||
|
#define __NW(a,b) __ ## a ## qi ## b
|
||||||
|
#define __NDW(a,b) __ ## a ## hi ## b
|
||||||
|
#endif
|
||||||
|
#endif
|
||||||
|
|
||||||
|
typedef int shift_count_type __attribute__((mode (__libgcc_shift_count__)));
|
||||||
|
|
||||||
|
#if __BYTE_ORDER__ != __ORDER_LITTLE_ENDIAN__
|
||||||
|
struct DWstruct {Wtype high, low;};
|
||||||
|
#else
|
||||||
|
struct DWstruct {Wtype low, high;};
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* We need this union to unpack/pack DImode values, since we don't have
|
||||||
|
any arithmetic yet. Incoming DImode parameters are stored into the
|
||||||
|
`ll' field, and the unpacked result is read from the struct `s'. */
|
||||||
|
|
||||||
|
typedef union {
|
||||||
|
struct DWstruct s;
|
||||||
|
DWtype ll;
|
||||||
|
} DWunion;
|
||||||
|
|
||||||
|
#endif /* __ASM_LIBGCC_H */
|
@ -29,6 +29,7 @@ memcmp:
|
|||||||
ld.a %r4, [%r0, 8]
|
ld.a %r4, [%r0, 8]
|
||||||
ld.a %r5, [%r1, 8]
|
ld.a %r5, [%r1, 8]
|
||||||
brne WORD2, %r12, .Lodd
|
brne WORD2, %r12, .Lodd
|
||||||
|
nop
|
||||||
.Loop_end:
|
.Loop_end:
|
||||||
asl_s SHIFT, SHIFT, 3
|
asl_s SHIFT, SHIFT, 3
|
||||||
bhs_s .Last_cmp
|
bhs_s .Last_cmp
|
||||||
@ -105,6 +106,7 @@ memcmp:
|
|||||||
ldb.a %r4, [%r0, 2]
|
ldb.a %r4, [%r0, 2]
|
||||||
ldb.a %r5, [%r1, 2]
|
ldb.a %r5, [%r1, 2]
|
||||||
brne %r3, %r12, .Lbyte_odd
|
brne %r3, %r12, .Lbyte_odd
|
||||||
|
nop
|
||||||
.Lbyte_end:
|
.Lbyte_end:
|
||||||
bcc .Lbyte_even
|
bcc .Lbyte_even
|
||||||
brne %r4, %r5, .Lbyte_even
|
brne %r4, %r5, .Lbyte_even
|
||||||
|
@ -7,13 +7,3 @@ config SYS_CONFIG_NAME
|
|||||||
default "arcangel4"
|
default "arcangel4"
|
||||||
|
|
||||||
endif
|
endif
|
||||||
|
|
||||||
if TARGET_ARCANGEL4_BE
|
|
||||||
|
|
||||||
config SYS_VENDOR
|
|
||||||
default "synopsys"
|
|
||||||
|
|
||||||
config SYS_CONFIG_NAME
|
|
||||||
default "arcangel4-be"
|
|
||||||
|
|
||||||
endif
|
|
||||||
|
@ -3,5 +3,4 @@ M: Alexey Brodkin <abrodkin@synopsys.com>
|
|||||||
S: Maintained
|
S: Maintained
|
||||||
F: include/configs/arcangel4.h
|
F: include/configs/arcangel4.h
|
||||||
F: configs/arcangel4_defconfig
|
F: configs/arcangel4_defconfig
|
||||||
F: include/configs/arcangel4-be.h
|
|
||||||
F: configs/arcangel4-be_defconfig
|
F: configs/arcangel4-be_defconfig
|
||||||
|
@ -1,3 +1,5 @@
|
|||||||
CONFIG_ARC=y
|
CONFIG_ARC=y
|
||||||
CONFIG_TARGET_ARCANGEL4_BE=y
|
CONFIG_TARGET_ARCANGEL4=y
|
||||||
CONFIG_SYS_CLK_FREQ=70000000
|
CONFIG_SYS_CLK_FREQ=70000000
|
||||||
|
CONFIG_CPU_BIG_ENDIAN=y
|
||||||
|
CONFIG_SYS_TEXT_BASE=0x81000000
|
||||||
|
@ -1,3 +1,4 @@
|
|||||||
CONFIG_ARC=y
|
CONFIG_ARC=y
|
||||||
CONFIG_TARGET_ARCANGEL4=y
|
CONFIG_TARGET_ARCANGEL4=y
|
||||||
CONFIG_SYS_CLK_FREQ=70000000
|
CONFIG_SYS_CLK_FREQ=70000000
|
||||||
|
CONFIG_SYS_TEXT_BASE=0x81000000
|
||||||
|
@ -1,3 +1,6 @@
|
|||||||
CONFIG_ARC=y
|
CONFIG_ARC=y
|
||||||
CONFIG_TARGET_AXS101=y
|
CONFIG_TARGET_AXS101=y
|
||||||
CONFIG_SYS_CLK_FREQ=750000000
|
CONFIG_SYS_CLK_FREQ=750000000
|
||||||
|
CONFIG_ARC_CACHE_LINE_SHIFT=5
|
||||||
|
CONFIG_SYS_DCACHE_OFF=y
|
||||||
|
CONFIG_SYS_TEXT_BASE=0x81000000
|
@ -1,3 +1,5 @@
|
|||||||
CONFIG_ARC=y
|
CONFIG_ARC=y
|
||||||
CONFIG_TARGET_TB100=y
|
CONFIG_TARGET_TB100=y
|
||||||
CONFIG_SYS_CLK_FREQ=500000000
|
CONFIG_SYS_CLK_FREQ=500000000
|
||||||
|
CONFIG_ARC_CACHE_LINE_SHIFT=5
|
||||||
|
CONFIG_SYS_TEXT_BASE=0x84000000
|
||||||
|
@ -1,91 +0,0 @@
|
|||||||
/*
|
|
||||||
* Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved.
|
|
||||||
*
|
|
||||||
* SPDX-License-Identifier: GPL-2.0+
|
|
||||||
*/
|
|
||||||
|
|
||||||
#ifndef _CONFIG_ARCANGEL4_H_
|
|
||||||
#define _CONFIG_ARCANGEL4_H_
|
|
||||||
|
|
||||||
/*
|
|
||||||
* CPU configuration
|
|
||||||
*/
|
|
||||||
#define CONFIG_SYS_BIG_ENDIAN
|
|
||||||
#define CONFIG_ARC700
|
|
||||||
#define CONFIG_ARC_MMU_VER 3
|
|
||||||
#define CONFIG_SYS_CACHELINE_SIZE 64
|
|
||||||
#define CONFIG_SYS_TIMER_RATE CONFIG_SYS_CLK_FREQ
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Board configuration
|
|
||||||
*/
|
|
||||||
#define CONFIG_SYS_GENERIC_BOARD
|
|
||||||
#define CONFIG_SKIP_LOWLEVEL_INIT /* U-Boot is in RAM already */
|
|
||||||
|
|
||||||
#define CONFIG_ARCH_EARLY_INIT_R
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Memory configuration
|
|
||||||
*/
|
|
||||||
#define CONFIG_SYS_TEXT_BASE 0x81000000
|
|
||||||
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
|
|
||||||
|
|
||||||
#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000
|
|
||||||
#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
|
|
||||||
#define CONFIG_SYS_SDRAM_SIZE 0x10000000 /* 256 Mb */
|
|
||||||
|
|
||||||
#define CONFIG_SYS_INIT_SP_ADDR \
|
|
||||||
(CONFIG_SYS_SDRAM_BASE + 0x1000 - GENERATED_GBL_DATA_SIZE)
|
|
||||||
|
|
||||||
#define CONFIG_SYS_MALLOC_LEN 0x200000 /* 2 MB */
|
|
||||||
#define CONFIG_SYS_BOOTM_LEN 0x2000000 /* 32 MB */
|
|
||||||
#define CONFIG_SYS_LOAD_ADDR 0x82000000
|
|
||||||
|
|
||||||
#define CONFIG_SYS_NO_FLASH
|
|
||||||
|
|
||||||
/*
|
|
||||||
* UART configuration
|
|
||||||
*
|
|
||||||
*/
|
|
||||||
#define CONFIG_ARC_SERIAL
|
|
||||||
#define CONFIG_ARC_UART_BASE 0xC0FC1000
|
|
||||||
#define CONFIG_BAUDRATE 115200
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Command line configuration
|
|
||||||
*/
|
|
||||||
#include <config_cmd_default.h>
|
|
||||||
|
|
||||||
#define CONFIG_CMD_ELF
|
|
||||||
|
|
||||||
#define CONFIG_OF_LIBFDT
|
|
||||||
|
|
||||||
#define CONFIG_AUTO_COMPLETE
|
|
||||||
#define CONFIG_SYS_MAXARGS 16
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Environment settings
|
|
||||||
*/
|
|
||||||
#define CONFIG_ENV_IS_NOWHERE
|
|
||||||
#define CONFIG_ENV_SIZE 0x00200 /* 512 bytes */
|
|
||||||
#define CONFIG_ENV_OFFSET 0
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Environment configuration
|
|
||||||
*/
|
|
||||||
#define CONFIG_BOOTDELAY 3
|
|
||||||
#define CONFIG_BOOTFILE "uImage"
|
|
||||||
#define CONFIG_BOOTARGS "console=ttyARC0,115200n8"
|
|
||||||
#define CONFIG_LOADADDR CONFIG_SYS_LOAD_ADDR
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Console configuration
|
|
||||||
*/
|
|
||||||
#define CONFIG_SYS_LONGHELP
|
|
||||||
#define CONFIG_SYS_PROMPT "arcangel4# "
|
|
||||||
#define CONFIG_SYS_CBSIZE 256
|
|
||||||
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
|
|
||||||
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
|
|
||||||
sizeof(CONFIG_SYS_PROMPT) + 16)
|
|
||||||
|
|
||||||
#endif /* _CONFIG_ARCANGEL4_H_ */
|
|
@ -10,23 +10,11 @@
|
|||||||
/*
|
/*
|
||||||
* CPU configuration
|
* CPU configuration
|
||||||
*/
|
*/
|
||||||
#define CONFIG_ARC700
|
|
||||||
#define CONFIG_ARC_MMU_VER 3
|
|
||||||
#define CONFIG_SYS_CACHELINE_SIZE 64
|
|
||||||
#define CONFIG_SYS_TIMER_RATE CONFIG_SYS_CLK_FREQ
|
#define CONFIG_SYS_TIMER_RATE CONFIG_SYS_CLK_FREQ
|
||||||
|
|
||||||
/*
|
|
||||||
* Board configuration
|
|
||||||
*/
|
|
||||||
#define CONFIG_SYS_GENERIC_BOARD
|
|
||||||
#define CONFIG_SKIP_LOWLEVEL_INIT /* U-Boot is in RAM already */
|
|
||||||
|
|
||||||
#define CONFIG_ARCH_EARLY_INIT_R
|
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* Memory configuration
|
* Memory configuration
|
||||||
*/
|
*/
|
||||||
#define CONFIG_SYS_TEXT_BASE 0x81000000
|
|
||||||
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
|
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
|
||||||
|
|
||||||
#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000
|
#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000
|
||||||
|
@ -10,22 +10,8 @@
|
|||||||
/*
|
/*
|
||||||
* CPU configuration
|
* CPU configuration
|
||||||
*/
|
*/
|
||||||
#define CONFIG_ARC700
|
|
||||||
#define CONFIG_ARC_MMU_VER 3
|
|
||||||
#define CONFIG_SYS_CACHELINE_SIZE 32
|
|
||||||
#define CONFIG_SYS_TIMER_RATE CONFIG_SYS_CLK_FREQ
|
#define CONFIG_SYS_TIMER_RATE CONFIG_SYS_CLK_FREQ
|
||||||
|
|
||||||
/* NAND controller DMA doesn't work correctly with D$ enabled */
|
|
||||||
#define CONFIG_SYS_DCACHE_OFF
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Board configuration
|
|
||||||
*/
|
|
||||||
#define CONFIG_SYS_GENERIC_BOARD
|
|
||||||
#define CONFIG_SKIP_LOWLEVEL_INIT /* U-Boot is in RAM already */
|
|
||||||
|
|
||||||
#define CONFIG_ARCH_EARLY_INIT_R
|
|
||||||
|
|
||||||
#define ARC_FPGA_PERIPHERAL_BASE 0xE0000000
|
#define ARC_FPGA_PERIPHERAL_BASE 0xE0000000
|
||||||
#define ARC_APB_PERIPHERAL_BASE 0xF0000000
|
#define ARC_APB_PERIPHERAL_BASE 0xF0000000
|
||||||
#define ARC_DWMMC_BASE (ARC_FPGA_PERIPHERAL_BASE + 0x15000)
|
#define ARC_DWMMC_BASE (ARC_FPGA_PERIPHERAL_BASE + 0x15000)
|
||||||
@ -34,7 +20,6 @@
|
|||||||
/*
|
/*
|
||||||
* Memory configuration
|
* Memory configuration
|
||||||
*/
|
*/
|
||||||
#define CONFIG_SYS_TEXT_BASE 0x81000000
|
|
||||||
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
|
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
|
||||||
|
|
||||||
#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000
|
#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000
|
||||||
|
@ -12,21 +12,11 @@
|
|||||||
/*
|
/*
|
||||||
* CPU configuration
|
* CPU configuration
|
||||||
*/
|
*/
|
||||||
#define CONFIG_ARC700
|
|
||||||
#define CONFIG_ARC_MMU_VER 3
|
|
||||||
#define CONFIG_SYS_CACHELINE_SIZE 32
|
|
||||||
#define CONFIG_SYS_TIMER_RATE CONFIG_SYS_CLK_FREQ
|
#define CONFIG_SYS_TIMER_RATE CONFIG_SYS_CLK_FREQ
|
||||||
|
|
||||||
/*
|
|
||||||
* Board configuration
|
|
||||||
*/
|
|
||||||
#define CONFIG_SYS_GENERIC_BOARD
|
|
||||||
#define CONFIG_ARCH_EARLY_INIT_R
|
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* Memory configuration
|
* Memory configuration
|
||||||
*/
|
*/
|
||||||
#define CONFIG_SYS_TEXT_BASE 0x84000000
|
|
||||||
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
|
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
|
||||||
|
|
||||||
#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000
|
#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000
|
||||||
|
Loading…
Reference in New Issue
Block a user