From 109076f86225374098d92baca3f5393afd157699 Mon Sep 17 00:00:00 2001
From: Fabio Estevam <fabio.estevam@nxp.com>
Date: Wed, 3 Jan 2018 12:55:35 -0200
Subject: [PATCH] mx6memcal: spl: Also take i.MX6ULL into account

i.MX6ULL also does not support 64-bit DDR bus, so add it to the
check logic.

Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
(cherry picked from commit 941fcabfa762c2a8b26238ec5cce520253d7388b)
---
 board/freescale/mx6memcal/spl.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/board/freescale/mx6memcal/spl.c b/board/freescale/mx6memcal/spl.c
index 8ee89ff116..e8b992c2b6 100644
--- a/board/freescale/mx6memcal/spl.c
+++ b/board/freescale/mx6memcal/spl.c
@@ -419,6 +419,7 @@ void board_init_f(ulong dummy)
 	if (sysinfo.dsize != 1) {
 		if (is_cpu_type(MXC_CPU_MX6SX) ||
 		    is_cpu_type(MXC_CPU_MX6UL) ||
+		    is_cpu_type(MXC_CPU_MX6ULL) ||
 		    is_cpu_type(MXC_CPU_MX6SL)) {
 			printf("cpu type 0x%x doesn't support 64-bit bus\n",
 			       get_cpu_type());