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https://github.com/brain-hackers/u-boot-brain
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spl: socfpga: Implement fpga bitstream loading with socfpga loadfs
Add support for loading FPGA bitstream to get DDR up running before U-Boot is loaded into DDR. Boot device initialization, generic firmware loader and SPL FAT support are required for this whole mechanism to work. Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
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@ -126,6 +126,7 @@ int fpgamgr_program_finish(void);
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int is_fpgamgr_user_mode(void);
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int is_fpgamgr_user_mode(void);
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int fpgamgr_wait_early_user_mode(void);
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int fpgamgr_wait_early_user_mode(void);
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const char *get_fpga_filename(void);
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const char *get_fpga_filename(void);
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int is_fpgamgr_early_user_mode(void);
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int socfpga_loadfs(fpga_fs_info *fpga_fsinfo, const void *buf, size_t bsize,
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int socfpga_loadfs(fpga_fs_info *fpga_fsinfo, const void *buf, size_t bsize,
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u32 offset);
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u32 offset);
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void fpgamgr_program(const void *buf, size_t bsize, u32 offset);
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void fpgamgr_program(const void *buf, size_t bsize, u32 offset);
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@ -1,6 +1,6 @@
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// SPDX-License-Identifier: GPL-2.0+
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// SPDX-License-Identifier: GPL-2.0+
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/*
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/*
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* Copyright (C) 2012 Altera Corporation <www.altera.com>
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* Copyright (C) 2012-2019 Altera Corporation <www.altera.com>
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*/
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*/
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#include <common.h>
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#include <common.h>
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@ -23,6 +23,11 @@
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#include <fdtdec.h>
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#include <fdtdec.h>
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#include <watchdog.h>
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#include <watchdog.h>
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#include <asm/arch/pinmux.h>
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#include <asm/arch/pinmux.h>
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#include <asm/arch/fpga_manager.h>
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#include <mmc.h>
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#include <memalign.h>
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#define FPGA_BUFSIZ 16 * 1024
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DECLARE_GLOBAL_DATA_PTR;
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DECLARE_GLOBAL_DATA_PTR;
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@ -68,11 +73,35 @@ u32 spl_boot_mode(const u32 boot_device)
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void spl_board_init(void)
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void spl_board_init(void)
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{
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{
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ALLOC_CACHE_ALIGN_BUFFER(char, buf, FPGA_BUFSIZ);
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/* enable console uart printing */
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/* enable console uart printing */
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preloader_console_init();
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preloader_console_init();
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WATCHDOG_RESET();
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WATCHDOG_RESET();
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arch_early_init_r();
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arch_early_init_r();
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/* If the full FPGA is already loaded, ie.from EPCQ, config fpga pins */
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if (is_fpgamgr_user_mode()) {
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int ret = config_pins(gd->fdt_blob, "shared");
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if (ret)
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return;
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ret = config_pins(gd->fdt_blob, "fpga");
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if (ret)
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return;
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} else if (!is_fpgamgr_early_user_mode()) {
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/* Program IOSSM(early IO release) or full FPGA */
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fpgamgr_program(buf, FPGA_BUFSIZ, 0);
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}
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/* If the IOSSM/full FPGA is already loaded, start DDR */
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if (is_fpgamgr_early_user_mode() || is_fpgamgr_user_mode())
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ddr_calibration_sequence();
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if (!is_fpgamgr_user_mode())
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fpgamgr_program(buf, FPGA_BUFSIZ, 0);
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}
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}
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void board_init_f(ulong dummy)
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void board_init_f(ulong dummy)
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@ -69,7 +69,7 @@ static int wait_for_user_mode(void)
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1, FPGA_TIMEOUT_MSEC, false);
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1, FPGA_TIMEOUT_MSEC, false);
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}
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}
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static int is_fpgamgr_early_user_mode(void)
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int is_fpgamgr_early_user_mode(void)
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{
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{
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return (readl(&fpga_manager_base->imgcfg_stat) &
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return (readl(&fpga_manager_base->imgcfg_stat) &
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ALT_FPGAMGR_IMGCFG_STAT_F2S_EARLY_USERMODE_SET_MSK) != 0;
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ALT_FPGAMGR_IMGCFG_STAT_F2S_EARLY_USERMODE_SET_MSK) != 0;
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