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ddr: marvell: a38x: Sync code with Marvell mv-ddr-marvell repository
This syncs drivers/ddr/marvell/a38x/ with the master branch of repository https://github.com/MarvellEmbeddedProcessors/mv-ddr-marvell.git up to the commit 7c351731d196 ("Merge pull request #29 from pali/sync-a38x-uboot"). This patch was created by following steps: 1. Replace all a38x files in U-Boot tree by files from upstream github Marvell mv-ddr-marvell repository. 2. Run following command to omit portions not relevant for a38x and ddr3: files=drivers/ddr/marvell/a38x/* sed 's/#if defined(CONFIG_ARMADA_38X) || defined(CONFIG_ARMADA_39X)/#ifdef TRUE/' -i $files unifdef -m -UMV_DDR -UMV_DDR_ATF -UCONFIG_DDR4 -UCONFIG_APN806 \ -UCONFIG_MC_STATIC -UCONFIG_MC_STATIC_PRINT -UCONFIG_PHY_STATIC \ -UCONFIG_PHY_STATIC_PRINT -UCONFIG_CUSTOMER_BOARD_SUPPORT \ -UCONFIG_A3700 -UA3900 -UA80X0 -UA70X0 -DTRUE $files 3. Manually omit SPDX-License-Identifier changes from this patch as upstream license in upstream github repository contains long license texts and U-Boot is using just SPDX-License-Identifier. After applying this patch, a38x ddr3 code in upstream Marvell github repository and in U-Boot would be fully identical. So in future applying above steps could be used to sync code again. The only change in this patch is removal of dead code and some fixes with include files. Signed-off-by: Pali Rohár <pali@kernel.org> Tested-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
This commit is contained in:
Pali Rohár
Stefan Roese
parent
a5fc099081
commit
107c3391b9
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@ -6,7 +6,6 @@
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#include "ddr3_init.h"
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#include "mv_ddr_training_db.h"
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#include "mv_ddr_regs.h"
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#include <log.h>
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u8 is_reg_dump = 0;
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u8 debug_pbs = DEBUG_LEVEL_ERROR;
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@ -77,9 +77,6 @@ int ddr3_init(void)
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return status;
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}
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#if defined(CONFIG_PHY_STATIC_PRINT)
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mv_ddr_phy_static_print();
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#endif
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/* Post MC/PHY initializations */
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mv_ddr_post_training_soc_config(ddr_type);
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@ -7,8 +7,6 @@
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#include "mv_ddr_common.h"
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#include "mv_ddr_training_db.h"
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#include "mv_ddr_regs.h"
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#include <log.h>
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#include <linux/delay.h>
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#define GET_CS_FROM_MASK(mask) (cs_mask2_num[mask])
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#define CS_CBE_VALUE(cs_num) (cs_cbe_reg[cs_num])
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@ -207,7 +205,6 @@ static int ddr3_tip_pad_inv(void)
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if (tm->interface_params[0].as_bus_params[sphy].
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is_ck_swap == 1 && sphy == 0) {
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/* TODO: move this code to per platform one */
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#if defined(CONFIG_ARMADA_38X) || defined(CONFIG_ARMADA_39X)
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/* clock swap for both cs0 and cs1 */
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data = (INVERT_PAD << INV_PAD2_OFFS |
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INVERT_PAD << INV_PAD6_OFFS |
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@ -219,9 +216,6 @@ static int ddr3_tip_pad_inv(void)
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DDR_PHY_CONTROL,
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PHY_CTRL_PHY_REG,
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data, data);
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#else /* !CONFIG_ARMADA_38X && !CONFIG_ARMADA_39X */
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#pragma message "unknown platform to configure ddr clock swap"
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#endif
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}
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}
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@ -2014,9 +2008,7 @@ int ddr3_tip_adll_regs_bypass(u32 dev_num, u32 reg_val1, u32 reg_val2)
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static int ddr3_tip_ddr3_training_main_flow(u32 dev_num)
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{
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/* TODO: enable this functionality for other platforms */
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#if defined(CONFIG_ARMADA_38X) || defined(CONFIG_ARMADA_39X)
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struct init_cntr_param init_cntr_prm;
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#endif
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int ret = MV_OK;
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int adll_bypass_flag = 0;
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u32 if_id;
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@ -2050,7 +2042,6 @@ static int ddr3_tip_ddr3_training_main_flow(u32 dev_num)
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}
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/* TODO: enable this functionality for other platforms */
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#if defined(CONFIG_ARMADA_38X) || defined(CONFIG_ARMADA_39X)
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if (is_adll_calib_before_init != 0) {
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DEBUG_TRAINING_IP(DEBUG_LEVEL_INFO,
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("with adll calib before init\n"));
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@ -2081,7 +2072,6 @@ static int ddr3_tip_ddr3_training_main_flow(u32 dev_num)
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return MV_FAIL;
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}
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}
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#endif
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ret = adll_calibration(dev_num, ACCESS_TYPE_MULTICAST, 0, freq);
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if (ret != MV_OK) {
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@ -2905,3 +2895,4 @@ unsigned int mv_ddr_misl_phy_odt_n_get(void)
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return odt_n;
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}
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@ -6,8 +6,6 @@
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#include "ddr3_init.h"
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#include "mv_ddr_regs.h"
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#include "ddr_training_ip_db.h"
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#include <image.h>
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#include <linux/delay.h>
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#define PATTERN_1 0x55555555
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#define PATTERN_2 0xaaaaaaaa
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@ -614,9 +612,9 @@ int ddr3_tip_load_pattern_to_odpg(u32 dev_num, enum hws_access_type access_type,
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MASK_ALL_BITS));
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}
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CHECK_STATUS(ddr3_tip_if_write(dev_num, access_type, if_id,
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ODPG_DATA_BUFFER_OFFS_REG,
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load_addr, MASK_ALL_BITS));
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CHECK_STATUS(ddr3_tip_if_write
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(dev_num, access_type, if_id,
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ODPG_DATA_BUFFER_OFFS_REG, load_addr, MASK_ALL_BITS));
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return MV_OK;
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}
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@ -7,7 +7,6 @@
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#include "mv_ddr_training_db.h"
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#include "ddr_training_ip_db.h"
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#include "mv_ddr_regs.h"
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#include <linux/delay.h>
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#define WL_ITERATION_NUM 10
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@ -13,9 +13,7 @@
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#include <asm/arch/cpu.h>
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#include <asm/arch/soc.h>
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#if defined(CONFIG_ARMADA_38X) || defined(CONFIG_ARMADA_39X)
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#define INTER_REGS_BASE SOC_REGS_PHY_BASE
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#endif
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/*
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* MV_DEBUG_INIT need to be defines, otherwise the output of the
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@ -8,7 +8,6 @@
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#include "mv_ddr_training_db.h"
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#include "mv_ddr_regs.h"
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#include "mv_ddr_sys_env_lib.h"
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#include <linux/delay.h>
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#define DDR_INTERFACES_NUM 1
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#define DDR_INTERFACE_OCTETS_NUM 5
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@ -6,6 +6,8 @@
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#ifndef _MV_DDR_PLAT_H
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#define _MV_DDR_PLAT_H
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#include <linux/delay.h>
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#define MAX_DEVICE_NUM 1
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#define MAX_INTERFACE_NUM 1
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#define MAX_BUS_NUM 5
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@ -78,20 +78,6 @@ enum suspend_wakeup_status {
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* set '-2'
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* If suspend to RAM is not supported set '-1'
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*/
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#ifdef CONFIG_CUSTOMER_BOARD_SUPPORT
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#ifdef CONFIG_ARMADA_38X
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#define MV_BOARD_WAKEUP_GPIO_INFO { \
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{A38X_CUSTOMER_BOARD_ID0, -1 }, \
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{A38X_CUSTOMER_BOARD_ID0, -1 }, \
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};
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#else
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#define MV_BOARD_WAKEUP_GPIO_INFO { \
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{A39X_CUSTOMER_BOARD_ID0, -1 }, \
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{A39X_CUSTOMER_BOARD_ID0, -1 }, \
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};
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#endif /* CONFIG_ARMADA_38X */
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#else
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#ifdef CONFIG_ARMADA_38X
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#define MV_BOARD_WAKEUP_GPIO_INFO { \
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@ -109,7 +95,6 @@ enum suspend_wakeup_status {
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{A39X_DB_69XX_ID, -1 }, \
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};
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#endif /* CONFIG_ARMADA_38X */
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#endif /* CONFIG_CUSTOMER_BOARD_SUPPORT */
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enum suspend_wakeup_status mv_ddr_sys_env_suspend_wakeup_check(void);
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u32 mv_ddr_sys_env_get_cs_ena_from_reg(void);
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@ -347,10 +347,8 @@ void ddr3_new_tip_ecc_scrub(void)
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for (cs_c = 0; cs_c < max_cs; cs_c++)
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cs_ena |= 1 << cs_c;
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#if defined(CONFIG_ARMADA_38X) || defined(CONFIG_ARMADA_39X)
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/* all chip-selects are of same size */
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ddr3_calc_mem_cs_size(0, &cs_mem_size_mb);
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#endif
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cs_mem_size = cs_mem_size_mb * _1M;
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mv_sys_xor_init(max_cs, cs_ena, cs_mem_size, 0);
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total_mem_size = max_cs * cs_mem_size;
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