arm: actions: add S700 SoC device tree
This patch adds .dtsi file(sync with Linux 5.5-rc6 with hash "b3a987b0264d") and required binding for S700 SoC that is a 64-bit Quad-core ARM Cortex-A53 cores. It also provisions dts file to be built based on selected platform(CONFIG_MACH_S900/S700). Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Amit Singh Tomar <amittomer25@gmail.com>
This commit is contained in:
Amit Singh Tomar
Tom Rini
parent
8b520ac153
commit
1050eaa082
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@ -66,6 +66,8 @@ dtb-$(CONFIG_KIRKWOOD) += \
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dtb-$(CONFIG_MACH_S900) += \
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bubblegum_96.dtb
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dtb-$(CONFIG_MACH_S700) += \
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s700-cubieboard7.dtb
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dtb-$(CONFIG_ROCKCHIP_PX30) += \
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px30-evb.dtb \
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@ -0,0 +1,248 @@
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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright (c) 2017 Andreas Färber
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*/
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#include <dt-bindings/clock/actions,s700-cmu.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/reset/actions,s700-reset.h>
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/ {
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compatible = "actions,s700";
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interrupt-parent = <&gic>;
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#address-cells = <2>;
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#size-cells = <2>;
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cpus {
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#address-cells = <2>;
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#size-cells = <0>;
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cpu0: cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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reg = <0x0 0x0>;
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enable-method = "psci";
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};
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cpu1: cpu@1 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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reg = <0x0 0x1>;
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enable-method = "psci";
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};
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cpu2: cpu@2 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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reg = <0x0 0x2>;
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enable-method = "psci";
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};
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cpu3: cpu@3 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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reg = <0x0 0x3>;
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enable-method = "psci";
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};
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};
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reserved-memory {
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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secmon@1f000000 {
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reg = <0x0 0x1f000000 0x0 0x1000000>;
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no-map;
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};
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};
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psci {
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compatible = "arm,psci-0.2";
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method = "smc";
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};
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arm-pmu {
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compatible = "arm,cortex-a53-pmu";
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interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
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};
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timer {
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compatible = "arm,armv8-timer";
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interrupts = <GIC_PPI 13
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(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 14
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(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 11
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(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 10
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(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
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};
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hosc: hosc {
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compatible = "fixed-clock";
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clock-frequency = <24000000>;
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#clock-cells = <0>;
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};
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losc: losc {
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compatible = "fixed-clock";
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clock-frequency = <32768>;
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#clock-cells = <0>;
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};
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soc {
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compatible = "simple-bus";
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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gic: interrupt-controller@e00f1000 {
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compatible = "arm,gic-400";
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reg = <0x0 0xe00f1000 0x0 0x1000>,
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<0x0 0xe00f2000 0x0 0x2000>,
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<0x0 0xe00f4000 0x0 0x2000>,
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<0x0 0xe00f6000 0x0 0x2000>;
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interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
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interrupt-controller;
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#interrupt-cells = <3>;
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};
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uart0: serial@e0120000 {
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compatible = "actions,s900-uart", "actions,owl-uart";
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reg = <0x0 0xe0120000 0x0 0x2000>;
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clocks = <&cmu CLK_UART0>;
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interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
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status = "disabled";
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};
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uart1: serial@e0122000 {
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compatible = "actions,s900-uart", "actions,owl-uart";
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reg = <0x0 0xe0122000 0x0 0x2000>;
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clocks = <&cmu CLK_UART1>;
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interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
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status = "disabled";
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};
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uart2: serial@e0124000 {
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compatible = "actions,s900-uart", "actions,owl-uart";
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reg = <0x0 0xe0124000 0x0 0x2000>;
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clocks = <&cmu CLK_UART2>;
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interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
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status = "disabled";
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};
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uart3: serial@e0126000 {
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compatible = "actions,s900-uart", "actions,owl-uart";
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reg = <0x0 0xe0126000 0x0 0x2000>;
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clocks = <&cmu CLK_UART3>;
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interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
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status = "disabled";
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};
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uart4: serial@e0128000 {
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compatible = "actions,s900-uart", "actions,owl-uart";
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reg = <0x0 0xe0128000 0x0 0x2000>;
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clocks = <&cmu CLK_UART4>;
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interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
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status = "disabled";
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};
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uart5: serial@e012a000 {
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compatible = "actions,s900-uart", "actions,owl-uart";
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reg = <0x0 0xe012a000 0x0 0x2000>;
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clocks = <&cmu CLK_UART5>;
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interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
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status = "disabled";
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};
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uart6: serial@e012c000 {
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compatible = "actions,s900-uart", "actions,owl-uart";
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reg = <0x0 0xe012c000 0x0 0x2000>;
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clocks = <&cmu CLK_UART6>;
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interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
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status = "disabled";
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};
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cmu: clock-controller@e0168000 {
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compatible = "actions,s700-cmu";
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reg = <0x0 0xe0168000 0x0 0x1000>;
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clocks = <&hosc>, <&losc>;
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#clock-cells = <1>;
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#reset-cells = <1>;
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};
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i2c0: i2c@e0170000 {
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compatible = "actions,s700-i2c";
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reg = <0 0xe0170000 0 0x1000>;
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clocks = <&cmu CLK_I2C0>;
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interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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i2c1: i2c@e0174000 {
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compatible = "actions,s700-i2c";
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reg = <0 0xe0174000 0 0x1000>;
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clocks = <&cmu CLK_I2C1>;
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interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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i2c2: i2c@e0178000 {
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compatible = "actions,s700-i2c";
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reg = <0 0xe0178000 0 0x1000>;
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clocks = <&cmu CLK_I2C2>;
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interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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i2c3: i2c@e017c000 {
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compatible = "actions,s700-i2c";
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reg = <0 0xe017c000 0 0x1000>;
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clocks = <&cmu CLK_I2C3>;
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interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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sps: power-controller@e01b0100 {
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compatible = "actions,s700-sps";
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reg = <0x0 0xe01b0100 0x0 0x100>;
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#power-domain-cells = <1>;
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};
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timer: timer@e024c000 {
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compatible = "actions,s700-timer";
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reg = <0x0 0xe024c000 0x0 0x4000>;
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interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "timer1";
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};
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pinctrl: pinctrl@e01b0000 {
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compatible = "actions,s700-pinctrl";
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reg = <0x0 0xe01b0000 0x0 0x1000>;
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clocks = <&cmu CLK_GPIO>;
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gpio-controller;
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gpio-ranges = <&pinctrl 0 0 136>;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
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};
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};
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};
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@ -0,0 +1,118 @@
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/* SPDX-License-Identifier: GPL-2.0
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*
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* Device Tree binding constants for Actions Semi S700 Clock Management Unit
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*
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* Copyright (c) 2014 Actions Semi Inc.
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* Author: David Liu <liuwei@actions-semi.com>
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*
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* Author: Pathiban Nallathambi <pn@denx.de>
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* Author: Saravanan Sekar <sravanhome@gmail.com>
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*/
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#ifndef __DT_BINDINGS_CLOCK_S700_H
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#define __DT_BINDINGS_CLOCK_S700_H
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#define CLK_NONE 0
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/* pll clocks */
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#define CLK_CORE_PLL 1
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#define CLK_DEV_PLL 2
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#define CLK_DDR_PLL 3
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#define CLK_NAND_PLL 4
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#define CLK_DISPLAY_PLL 5
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#define CLK_TVOUT_PLL 6
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#define CLK_CVBS_PLL 7
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#define CLK_AUDIO_PLL 8
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#define CLK_ETHERNET_PLL 9
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/* system clock */
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#define CLK_CPU 10
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#define CLK_DEV 11
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#define CLK_AHB 12
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#define CLK_APB 13
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#define CLK_DMAC 14
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#define CLK_NOC0_CLK_MUX 15
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#define CLK_NOC1_CLK_MUX 16
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#define CLK_HP_CLK_MUX 17
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#define CLK_HP_CLK_DIV 18
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#define CLK_NOC1_CLK_DIV 19
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#define CLK_NOC0 20
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#define CLK_NOC1 21
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#define CLK_SENOR_SRC 22
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/* peripheral device clock */
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#define CLK_GPIO 23
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#define CLK_TIMER 24
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#define CLK_DSI 25
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#define CLK_CSI 26
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#define CLK_SI 27
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#define CLK_DE 28
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#define CLK_HDE 29
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#define CLK_VDE 30
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#define CLK_VCE 31
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#define CLK_NAND 32
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#define CLK_SD0 33
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#define CLK_SD1 34
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#define CLK_SD2 35
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#define CLK_UART0 36
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#define CLK_UART1 37
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#define CLK_UART2 38
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#define CLK_UART3 39
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#define CLK_UART4 40
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#define CLK_UART5 41
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#define CLK_UART6 42
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#define CLK_PWM0 43
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#define CLK_PWM1 44
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#define CLK_PWM2 45
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#define CLK_PWM3 46
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#define CLK_PWM4 47
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#define CLK_PWM5 48
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#define CLK_GPU3D 49
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#define CLK_I2C0 50
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#define CLK_I2C1 51
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#define CLK_I2C2 52
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#define CLK_I2C3 53
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#define CLK_SPI0 54
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#define CLK_SPI1 55
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#define CLK_SPI2 56
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#define CLK_SPI3 57
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#define CLK_USB3_480MPLL0 58
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#define CLK_USB3_480MPHY0 59
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#define CLK_USB3_5GPHY 60
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#define CLK_USB3_CCE 61
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#define CLK_USB3_MAC 62
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#define CLK_LCD 63
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#define CLK_HDMI_AUDIO 64
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#define CLK_I2SRX 65
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#define CLK_I2STX 66
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#define CLK_SENSOR0 67
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#define CLK_SENSOR1 68
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#define CLK_HDMI_DEV 69
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#define CLK_ETHERNET 70
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#define CLK_RMII_REF 71
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#define CLK_USB2H0_PLLEN 72
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#define CLK_USB2H0_PHY 73
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#define CLK_USB2H0_CCE 74
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#define CLK_USB2H1_PLLEN 75
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#define CLK_USB2H1_PHY 76
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#define CLK_USB2H1_CCE 77
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#define CLK_TVOUT 78
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#define CLK_THERMAL_SENSOR 79
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#define CLK_IRC_SWITCH 80
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#define CLK_PCM1 81
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#define CLK_NR_CLKS (CLK_PCM1 + 1)
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#endif /* __DT_BINDINGS_CLOCK_S700_H */
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@ -0,0 +1,34 @@
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// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
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//
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// Device Tree binding constants for Actions Semi S700 Reset Management Unit
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//
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// Copyright (c) 2018 Linaro Ltd.
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#ifndef __DT_BINDINGS_ACTIONS_S700_RESET_H
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#define __DT_BINDINGS_ACTIONS_S700_RESET_H
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#define RESET_AUDIO 0
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#define RESET_CSI 1
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#define RESET_DE 2
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#define RESET_DSI 3
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#define RESET_GPIO 4
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#define RESET_I2C0 5
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#define RESET_I2C1 6
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#define RESET_I2C2 7
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#define RESET_I2C3 8
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#define RESET_KEY 9
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#define RESET_LCD0 10
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#define RESET_SI 11
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#define RESET_SPI0 12
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#define RESET_SPI1 13
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#define RESET_SPI2 14
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#define RESET_SPI3 15
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#define RESET_UART0 16
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#define RESET_UART1 17
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#define RESET_UART2 18
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#define RESET_UART3 19
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#define RESET_UART4 20
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#define RESET_UART5 21
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#define RESET_UART6 22
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#endif /* __DT_BINDINGS_ACTIONS_S700_RESET_H */
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