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Fix the local bus divider mapping
The real clock divider is 4 times of the bits LCRR[CLKDIV], according the latest RevF RM. Signed-off-by: Dave Liu <daveliu@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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@ -170,7 +170,12 @@ void get_sys_info (sys_info_t * sysInfo)
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}
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#endif
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if (lcrr_div == 2 || lcrr_div == 4 || lcrr_div == 8) {
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#if !defined(CONFIG_MPC8540) && !defined(CONFIG_MPC8541) && \
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#if defined(CONFIG_FSL_CORENET)
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/* If this is corenet based SoC, bit-representation
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* for four times the clock divider values.
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*/
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lcrr_div *= 4;
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#elif !defined(CONFIG_MPC8540) && !defined(CONFIG_MPC8541) && \
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!defined(CONFIG_MPC8555) && !defined(CONFIG_MPC8560)
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/*
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* Yes, the entire PQ38 family use the same
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