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driver/ddr/fsl: Update DDR4 MR6 for Vref range

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MR6 bit 6 is set accrodingly for range 1 or 2, per JEDEC spec.

Signed-off-by: York Sun <yorksun@freescale.com>
This commit is contained in:
York Sun 2015-11-04 10:03:18 -08:00
parent 19601dd99c
commit 0fb7197436
1 changed files with 3 additions and 0 deletions
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3
drivers/ddr/fsl/ctrl_regs.c
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@ -1186,6 +1186,9 @@ static void set_ddr_sdram_mode_10(const unsigned int ctrl_num,
esdmode6 = ((tccdl_min - 4) & 0x7) << 10;
if (popts->ddr_cdr2 & DDR_CDR2_VREF_RANGE_2)
esdmode6 |= 1 << 6; /* Range 2 */
ddr->ddr_sdram_mode_10 = (0
| ((esdmode6 & 0xffff) << 16)
| ((esdmode7 & 0xffff) << 0)