mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-08-20 00:48:52 +09:00
Merge with /home/wd/git/u-boot/custodian/u-boot-ppc4xx
This commit is contained in:
commit
0f5642d732
5
Makefile
5
Makefile
@ -430,6 +430,7 @@ inka4x0_config: unconfig
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@$(MKCONFIG) inka4x0 ppc mpc5xxx inka4x0
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@$(MKCONFIG) inka4x0 ppc mpc5xxx inka4x0
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lite5200b_config \
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lite5200b_config \
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lite5200b_PM_config \
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lite5200b_LOWBOOT_config: unconfig
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lite5200b_LOWBOOT_config: unconfig
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@mkdir -p $(obj)include
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@mkdir -p $(obj)include
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@mkdir -p $(obj)board/icecube
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@mkdir -p $(obj)board/icecube
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@ -438,6 +439,10 @@ lite5200b_LOWBOOT_config: unconfig
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@ echo "... DDR memory revision"
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@ echo "... DDR memory revision"
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@ echo "#define CONFIG_MPC5200" >>$(obj)include/config.h
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@ echo "#define CONFIG_MPC5200" >>$(obj)include/config.h
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@ echo "#define CONFIG_LITE5200B" >>$(obj)include/config.h
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@ echo "#define CONFIG_LITE5200B" >>$(obj)include/config.h
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@[ -z "$(findstring _PM_,$@)" ] || \
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{ echo "#define CONFIG_LITE5200B_PM" >>$(obj)include/config.h ; \
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echo "... with power management (low-power mode) support" ; \
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}
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@[ -z "$(findstring LOWBOOT_,$@)" ] || \
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@[ -z "$(findstring LOWBOOT_,$@)" ] || \
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{ echo "TEXT_BASE = 0xFF000000" >$(obj)board/icecube/config.tmp ; \
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{ echo "TEXT_BASE = 0xFF000000" >$(obj)board/icecube/config.tmp ; \
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echo "... with LOWBOOT configuration" ; \
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echo "... with LOWBOOT configuration" ; \
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@ -26,7 +26,7 @@
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extern void board_pll_init_f(void);
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extern void board_pll_init_f(void);
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void liveoak_gpio_init(void)
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static void acadia_gpio_init(void)
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{
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{
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/*
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/*
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* GPIO0 setup (select GPIO or alternate function)
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* GPIO0 setup (select GPIO or alternate function)
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@ -55,8 +55,12 @@ int board_early_init_f(void)
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{
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{
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unsigned int reg;
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unsigned int reg;
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/* don't reinit PLL when booting via I2C bootstrap option */
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mfsdr(SDR_PINSTP, reg);
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if (reg != 0xf0000000)
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board_pll_init_f();
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board_pll_init_f();
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liveoak_gpio_init();
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acadia_gpio_init();
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/* USB Host core needs this bit set */
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/* USB Host core needs this bit set */
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mfsdr(sdrultra1, reg);
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mfsdr(sdrultra1, reg);
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@ -103,7 +103,7 @@ tlbtabB:
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tlbentry(CFG_PERIPHERAL_BASE, SZ_4K, 0xF0000000, 4, AC_R|AC_W|SA_G|SA_I)
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tlbentry(CFG_PERIPHERAL_BASE, SZ_4K, 0xF0000000, 4, AC_R|AC_W|SA_G|SA_I)
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tlbentry(CFG_ACE_BASE, SZ_1K, 0xE0000000, 4,AC_R|AC_W|SA_G|SA_I)
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tlbentry(CFG_ACE_BASE, SZ_1K, CFG_ACE_BASE, 4,AC_R|AC_W|SA_G|SA_I)
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tlbentry(CFG_PCI_BASE, SZ_256M, 0x00000000, 0xC, AC_R|AC_W|SA_G|SA_I)
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tlbentry(CFG_PCI_BASE, SZ_256M, 0x00000000, 0xC, AC_R|AC_W|SA_G|SA_I)
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tlbentry(CFG_PCI_MEMBASE, SZ_256M, 0x10000000, 0xC, AC_R|AC_W|SA_G|SA_I)
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tlbentry(CFG_PCI_MEMBASE, SZ_256M, 0x10000000, 0xC, AC_R|AC_W|SA_G|SA_I)
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@ -42,6 +42,53 @@
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#include "mt48lc16m16a2-75.h"
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#include "mt48lc16m16a2-75.h"
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# endif
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# endif
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#endif
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#endif
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#ifdef CONFIG_LITE5200B_PM
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/* u-boot part of low-power mode implementation */
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#define SAVED_ADDR (*(void **)0x00000000)
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#define PSC2_4 0x02
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void lite5200b_wakeup(void)
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{
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unsigned char wakeup_pin;
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void (*linux_wakeup)(void);
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/* check PSC2_4, if it's down "QT" is signaling we have a wakeup
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* from low power mode */
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*(vu_char *)MPC5XXX_WU_GPIO_ENABLE = PSC2_4;
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__asm__ volatile ("sync");
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wakeup_pin = *(vu_char *)MPC5XXX_WU_GPIO_DATA_I;
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if (wakeup_pin & PSC2_4)
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return;
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/* acknowledge to "QT"
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* by holding pin at 1 for 10 uS */
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*(vu_char *)MPC5XXX_WU_GPIO_DIR = PSC2_4;
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__asm__ volatile ("sync");
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*(vu_char *)MPC5XXX_WU_GPIO_DATA_O = PSC2_4;
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__asm__ volatile ("sync");
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udelay(10);
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/* put ram out of self-refresh */
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*(vu_long *)MPC5XXX_SDRAM_CTRL |= 0x80000000; /* mode_en */
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__asm__ volatile ("sync");
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*(vu_long *)MPC5XXX_SDRAM_CTRL |= 0x50000000; /* cke ref_en */
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__asm__ volatile ("sync");
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*(vu_long *)MPC5XXX_SDRAM_CTRL &= ~0x80000000; /* !mode_en */
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__asm__ volatile ("sync");
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udelay(10); /* wait a bit */
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/* jump back to linux kernel code */
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linux_wakeup = SAVED_ADDR;
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printf("\n\nLooks like we just woke, transferring control to 0x%08lx\n",
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linux_wakeup);
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linux_wakeup();
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}
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#else
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#define lite5200b_wakeup()
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#endif
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#ifndef CFG_RAMBOOT
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#ifndef CFG_RAMBOOT
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static void sdram_start (int hi_addr)
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static void sdram_start (int hi_addr)
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{
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{
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@ -208,6 +255,8 @@ long int initdram (int board_type)
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__asm__ volatile ("sync");
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__asm__ volatile ("sync");
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}
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}
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lite5200b_wakeup();
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return dramsize + dramsize2;
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return dramsize + dramsize2;
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}
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}
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@ -423,7 +423,7 @@ int do_diskboot (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
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}
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}
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part = simple_strtoul(++ep, NULL, 16);
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part = simple_strtoul(++ep, NULL, 16);
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}
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}
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if (get_partition_info (ide_dev_desc, part, &info)) {
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if (get_partition_info (&ide_dev_desc[dev], part, &info)) {
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SHOW_BOOT_PROGRESS (-1);
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SHOW_BOOT_PROGRESS (-1);
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return 1;
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return 1;
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}
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}
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@ -1344,7 +1344,7 @@ ulong ide_read (int device, lbaint_t blknr, ulong blkcnt, void *buffer)
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++n;
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++n;
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++blknr;
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++blknr;
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buffer += ATA_SECTORWORDS;
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buffer += ATA_BLOCKSIZE;
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}
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}
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IDE_READ_E:
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IDE_READ_E:
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ide_led (DEVICE_LED(device), 0); /* LED off */
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ide_led (DEVICE_LED(device), 0); /* LED off */
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@ -1428,7 +1428,7 @@ ulong ide_write (int device, lbaint_t blknr, ulong blkcnt, void *buffer)
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c = ide_inb (device, ATA_STATUS); /* clear IRQ */
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c = ide_inb (device, ATA_STATUS); /* clear IRQ */
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++n;
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++n;
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++blknr;
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++blknr;
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buffer += ATA_SECTORWORDS;
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buffer += ATA_BLOCKSIZE;
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}
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}
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WR_OUT:
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WR_OUT:
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ide_led (DEVICE_LED(device), 0); /* LED off */
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ide_led (DEVICE_LED(device), 0); /* LED off */
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@ -2052,7 +2052,7 @@ ulong atapi_read (int device, lbaint_t blknr, ulong blkcnt, void *buffer)
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n+=cnt;
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n+=cnt;
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blkcnt-=cnt;
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blkcnt-=cnt;
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blknr+=cnt;
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blknr+=cnt;
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buffer+=cnt*(ATAPI_READ_BLOCK_SIZE/4); /* ulong blocksize in ulong */
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buffer+=(cnt*ATAPI_READ_BLOCK_SIZE);
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} while (blkcnt > 0);
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} while (blkcnt > 0);
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return (n);
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return (n);
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}
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}
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@ -248,7 +248,7 @@ int do_scsiboot (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
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}
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}
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part = simple_strtoul(++ep, NULL, 16);
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part = simple_strtoul(++ep, NULL, 16);
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}
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}
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if (get_partition_info (scsi_dev_desc, part, &info)) {
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if (get_partition_info (&scsi_dev_desc[dev], part, &info)) {
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printf("error reading partinfo\n");
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printf("error reading partinfo\n");
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return 1;
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return 1;
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}
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}
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@ -125,6 +125,7 @@ int i2c_bootrom_enabled(void)
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return (val & SDR0_SDCS_SDD);
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return (val & SDR0_SDCS_SDD);
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#endif
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#endif
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}
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}
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#endif
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#if defined(CONFIG_440GX)
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#if defined(CONFIG_440GX)
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#define SDR0_PINSTP_SHIFT 29
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#define SDR0_PINSTP_SHIFT 29
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@ -178,16 +179,37 @@ static char *bootstrap_str[] = {
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};
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};
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#endif
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#endif
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#if defined(CONFIG_405EZ)
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#define SDR0_PINSTP_SHIFT 28
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static char *bootstrap_str[] = {
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"EBC (8 bits)",
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"SPI (fast)",
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"NAND (512 page, 4 addr cycle)",
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"I2C (Addr 0x50)",
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"EBC (32 bits)",
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"I2C (Addr 0x50)",
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"NAND (2K page, 5 addr cycle)",
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"I2C (Addr 0x50)",
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"EBC (16 bits)",
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"Reserved",
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"NAND (2K page, 4 addr cycle)",
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"I2C (Addr 0x50)",
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"NAND (512 page, 3 addr cycle)",
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"I2C (Addr 0x50)",
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"SPI (slow)",
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"I2C (Addr 0x50)",
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};
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#endif
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#if defined(SDR0_PINSTP_SHIFT)
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#if defined(SDR0_PINSTP_SHIFT)
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static int bootstrap_option(void)
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static int bootstrap_option(void)
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{
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{
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unsigned long val;
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unsigned long val;
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mfsdr(sdr_pinstp, val);
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mfsdr(SDR_PINSTP, val);
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return ((val & 0xe0000000) >> SDR0_PINSTP_SHIFT);
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return ((val & 0xf0000000) >> SDR0_PINSTP_SHIFT);
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}
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}
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#endif /* SDR0_PINSTP_SHIFT */
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#endif /* SDR0_PINSTP_SHIFT */
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#endif
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#if defined(CONFIG_440)
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#if defined(CONFIG_440)
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@ -403,11 +425,11 @@ int checkcpu (void)
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#if defined(I2C_BOOTROM)
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#if defined(I2C_BOOTROM)
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printf (" I2C boot EEPROM %sabled\n", i2c_bootrom_enabled() ? "en" : "dis");
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printf (" I2C boot EEPROM %sabled\n", i2c_bootrom_enabled() ? "en" : "dis");
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#endif /* I2C_BOOTROM */
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#if defined(SDR0_PINSTP_SHIFT)
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#if defined(SDR0_PINSTP_SHIFT)
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printf (" Bootstrap Option %c - ", (char)bootstrap_option() + 'A');
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printf (" Bootstrap Option %c - ", (char)bootstrap_option() + 'A');
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printf ("Boot ROM Location %s\n", bootstrap_str[bootstrap_option()]);
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printf ("Boot ROM Location %s\n", bootstrap_str[bootstrap_option()]);
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#endif /* SDR0_PINSTP_SHIFT */
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#endif /* SDR0_PINSTP_SHIFT */
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#endif /* I2C_BOOTROM */
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#if defined(CONFIG_PCI)
|
#if defined(CONFIG_PCI)
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printf (" Internal PCI arbiter %sabled", pci_arbiter_enabled() ? "en" : "dis");
|
printf (" Internal PCI arbiter %sabled", pci_arbiter_enabled() ? "en" : "dis");
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@ -91,7 +91,6 @@ static void _i2c_bus_reset(void)
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void i2c_init(int speed, int slaveadd)
|
void i2c_init(int speed, int slaveadd)
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{
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{
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sys_info_t sysInfo;
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unsigned long freqOPB;
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unsigned long freqOPB;
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int val, divisor;
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int val, divisor;
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int bus;
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int bus;
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@ -124,8 +123,7 @@ void i2c_init(int speed, int slaveadd)
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/* Clock divide Register */
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/* Clock divide Register */
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/* get OPB frequency */
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/* get OPB frequency */
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get_sys_info(&sysInfo);
|
freqOPB = get_OPB_freq();
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freqOPB = sysInfo.freqPLB / sysInfo.pllOpbDiv;
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/* set divisor according to freqOPB */
|
/* set divisor according to freqOPB */
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divisor = (freqOPB - 1) / 10000000;
|
divisor = (freqOPB - 1) / 10000000;
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if (divisor == 0)
|
if (divisor == 0)
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||||||
|
22
doc/README.Lite5200B_low_power
Normal file
22
doc/README.Lite5200B_low_power
Normal file
@ -0,0 +1,22 @@
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|
Lite5200B wakeup from low-power mode (CONFIG_LITE5200B_PM)
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||||||
|
----------------------------------------------------------
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|
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||||||
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Low-power mode as described in Lite5200B User's Manual, means that
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|
with support of MC68HLC908QT1 microcontroller (refered to as QT),
|
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|
everything but the SDRAM can be powered down. This brings
|
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|
maximum power saving, while one can still restore previous state
|
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|
quickly.
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|
|
||||||
|
Quick overview where U-Boot comes into the picture:
|
||||||
|
- OS saves device states
|
||||||
|
- OS saves wakeup handler address to physical 0x0, puts SDRAM into
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|
self-refresh and signals to QT, it should power down the board
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|
- / board is sleeping here /
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|
- someone presses SW4 (connected to QT)
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|
- U-Boot checks PSC2_4 pin, if QT drives it down, then we woke up,
|
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|
so get SDRAM out of self-refresh and transfer control to OS
|
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|
wakeup handler
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|
- OS restores device states
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||||||
|
|
||||||
|
This was tested on Linux with USB and Ethernet in use. Adding
|
||||||
|
support for other devices is an OS issue.
|
@ -78,7 +78,7 @@
|
|||||||
#define CONFIG_PCI_SYS_MEM_PHYS CFG_SDRAM_BASE
|
#define CONFIG_PCI_SYS_MEM_PHYS CFG_SDRAM_BASE
|
||||||
#define CONFIG_PCI_SYS_MEM_SIZE (1024 * 1024 * 1024)
|
#define CONFIG_PCI_SYS_MEM_SIZE (1024 * 1024 * 1024)
|
||||||
|
|
||||||
#define CFG_ACE_BASE 0xe0000000 /* Xilinx ACE controller - Compact Flash */
|
#define CFG_ACE_BASE 0xfe000000 /* Xilinx ACE controller - Compact Flash */
|
||||||
|
|
||||||
/*-----------------------------------------------------------------------
|
/*-----------------------------------------------------------------------
|
||||||
* Initial RAM & stack pointer (placed in internal SRAM)
|
* Initial RAM & stack pointer (placed in internal SRAM)
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|
@ -570,6 +570,8 @@
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|||||||
#define SDR_ICTX0_STAT 0x40000000
|
#define SDR_ICTX0_STAT 0x40000000
|
||||||
#define SDR_ICTX1_STAT 0x20000000
|
#define SDR_ICTX1_STAT 0x20000000
|
||||||
|
|
||||||
|
#define SDR_PINSTP 0x40
|
||||||
|
|
||||||
/******************************************************************************
|
/******************************************************************************
|
||||||
* Control
|
* Control
|
||||||
******************************************************************************/
|
******************************************************************************/
|
||||||
|
@ -148,7 +148,7 @@
|
|||||||
#define sdrcfgd (SDR_DCR_BASE+0x1)
|
#define sdrcfgd (SDR_DCR_BASE+0x1)
|
||||||
#define sdr_sdstp0 0x0020 /* */
|
#define sdr_sdstp0 0x0020 /* */
|
||||||
#define sdr_sdstp1 0x0021 /* */
|
#define sdr_sdstp1 0x0021 /* */
|
||||||
#define sdr_pinstp 0x0040
|
#define SDR_PINSTP 0x0040
|
||||||
#define sdr_sdcs 0x0060
|
#define sdr_sdcs 0x0060
|
||||||
#define sdr_ecid0 0x0080
|
#define sdr_ecid0 0x0080
|
||||||
#define sdr_ecid1 0x0081
|
#define sdr_ecid1 0x0081
|
||||||
|
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