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sunxi: Make CPUCFG_BASE macro names the same across families
Use SUNXI_CPUCFG_BASE across all families. This makes writing common PSCI code easier. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
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@ -73,8 +73,8 @@ psci_fiq_enter:
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lsr r9, r9, #10
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and r9, r9, #0xf
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movw r8, #(SUN6I_CPUCFG_BASE & 0xffff)
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movt r8, #(SUN6I_CPUCFG_BASE >> 16)
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movw r8, #(SUNXI_CPUCFG_BASE & 0xffff)
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movt r8, #(SUNXI_CPUCFG_BASE >> 16)
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@ Wait for the core to enter WFI
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lsl r11, r9, #6 @ x64
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@ -114,8 +114,8 @@ psci_fiq_enter:
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str r10, [r12, #0x140]
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#endif
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movw r8, #(SUN6I_CPUCFG_BASE & 0xffff)
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movt r8, #(SUN6I_CPUCFG_BASE >> 16)
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movw r8, #(SUNXI_CPUCFG_BASE & 0xffff)
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movt r8, #(SUNXI_CPUCFG_BASE >> 16)
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@ Unlock CPU
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ldr r10, [r8, #0x1e4]
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@ -139,8 +139,8 @@ psci_cpu_on:
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str r2, [r0] @ store target PC at stack top
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dsb
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movw r0, #(SUN6I_CPUCFG_BASE & 0xffff)
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movt r0, #(SUN6I_CPUCFG_BASE >> 16)
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movw r0, #(SUNXI_CPUCFG_BASE & 0xffff)
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movt r0, #(SUNXI_CPUCFG_BASE >> 16)
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@ CPU mask
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and r1, r1, #3 @ only care about first cluster
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@ -189,8 +189,8 @@ psci_cpu_on:
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str r6, [r0, #0x100]
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@ re-calculate CPU control register address
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movw r0, #(SUN6I_CPUCFG_BASE & 0xffff)
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movt r0, #(SUN6I_CPUCFG_BASE >> 16)
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movw r0, #(SUNXI_CPUCFG_BASE & 0xffff)
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movt r0, #(SUNXI_CPUCFG_BASE >> 16)
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@ Deassert reset on target CPU
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mov r6, #3
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@ -73,8 +73,8 @@ psci_fiq_enter:
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lsr r9, r9, #10
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and r9, r9, #0xf
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movw r8, #(SUN7I_CPUCFG_BASE & 0xffff)
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movt r8, #(SUN7I_CPUCFG_BASE >> 16)
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movw r8, #(SUNXI_CPUCFG_BASE & 0xffff)
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movt r8, #(SUNXI_CPUCFG_BASE >> 16)
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@ Wait for the core to enter WFI
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lsl r11, r9, #6 @ x64
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@ -128,8 +128,8 @@ psci_cpu_on:
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str r2, [r0] @ store target PC at stack top
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dsb
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movw r0, #(SUN7I_CPUCFG_BASE & 0xffff)
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movt r0, #(SUN7I_CPUCFG_BASE >> 16)
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movw r0, #(SUNXI_CPUCFG_BASE & 0xffff)
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movt r0, #(SUNXI_CPUCFG_BASE >> 16)
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@ CPU mask
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and r1, r1, #3 @ only care about first cluster
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@ -18,6 +18,10 @@
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#define SUNXI_SRAM_D_BASE 0x00010000 /* 4 kiB */
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#define SUNXI_SRAM_B_BASE 0x00020000 /* 64 kiB (secure) */
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#ifdef CONFIG_MACH_SUN8I_A83T
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#define SUNXI_CPUCFG_BASE 0x01700000
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#endif
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#define SUNXI_SRAMC_BASE 0x01c00000
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#define SUNXI_DRAMC_BASE 0x01c01000
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#define SUNXI_DMA_BASE 0x01c02000
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@ -94,7 +98,10 @@
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#define SUNXI_TP_BASE 0x01c25000
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#define SUNXI_PMU_BASE 0x01c25400
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#define SUN7I_CPUCFG_BASE 0x01c25c00
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#ifdef CONFIG_MACH_SUN7I
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#define SUNXI_CPUCFG_BASE 0x01c25c00
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#endif
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#define SUNXI_UART0_BASE 0x01c28000
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#define SUNXI_UART1_BASE 0x01c28400
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@ -148,7 +155,11 @@
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#define SUNXI_RTC_BASE 0x01f00000
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#define SUNXI_PRCM_BASE 0x01f01400
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#define SUN6I_CPUCFG_BASE 0x01f01c00
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#if defined CONFIG_SUNXI_GEN_SUN6I && !defined CONFIG_MACH_SUN8I_A83T
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#define SUNXI_CPUCFG_BASE 0x01f01c00
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#endif
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#define SUNXI_R_TWI_BASE 0x01f02400
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#define SUNXI_R_UART_BASE 0x01f02800
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#define SUNXI_R_PIO_BASE 0x01f02c00
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