mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-09-28 23:50:26 +09:00
Merge branch 'master' of git://git.denx.de/u-boot-tegra
This commit is contained in:
Tom Rini
commit
0ed06c7ee4
@ -16,7 +16,7 @@
|
||||
i2c2 = "/i2c@7000c400";
|
||||
mmc0 = "/sdhci@c8000600";
|
||||
usb0 = "/usb@c5000000";
|
||||
usb1 = "/usb@c5004000"; /* on-module only, for ASIX */
|
||||
usb1 = "/usb@c5004000"; /* On-module only, for ASIX */
|
||||
usb2 = "/usb@c5008000";
|
||||
};
|
||||
|
||||
@ -92,8 +92,10 @@
|
||||
/* EHCI instance 1: ULPI -> USB3340 -> AX88772B */
|
||||
usb@c5004000 {
|
||||
status = "okay";
|
||||
/* ULPI_RESET */
|
||||
nvidia,phy-reset-gpio =
|
||||
<&gpio TEGRA_GPIO(V, 1) GPIO_ACTIVE_LOW>;
|
||||
/* VBUS_LAN */
|
||||
nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 1) GPIO_ACTIVE_HIGH>;
|
||||
nvidia,vbus-gpio = <&gpio TEGRA_GPIO(BB, 1) GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
|
||||
@ -1,5 +1,6 @@
|
||||
/dts-v1/;
|
||||
|
||||
#include <dt-bindings/input/input.h>
|
||||
#include "tegra20.dtsi"
|
||||
|
||||
/ {
|
||||
@ -11,7 +12,13 @@
|
||||
};
|
||||
|
||||
aliases {
|
||||
usb0 = "/usb@c5008000";
|
||||
rtc0 = "/i2c@7000d000/tps6586x@34";
|
||||
rtc1 = "/rtc@7000e000";
|
||||
serial0 = &uarta;
|
||||
serial1 = &uartc;
|
||||
usb0 = "/usb@c5000000";
|
||||
usb1 = "/usb@c5004000";
|
||||
usb2 = "/usb@c5008000";
|
||||
mmc0 = "/sdhci@c8000600";
|
||||
mmc1 = "/sdhci@c8000000";
|
||||
};
|
||||
@ -26,19 +33,475 @@
|
||||
status = "okay";
|
||||
rgb {
|
||||
status = "okay";
|
||||
nvidia,panel = <&lcd_panel>;
|
||||
|
||||
nvidia,panel = <&panel>;
|
||||
|
||||
display-timings {
|
||||
timing@0 {
|
||||
/* PAZ00 has 1024x600 */
|
||||
clock-frequency = <54030000>;
|
||||
hactive = <1024>;
|
||||
vactive = <600>;
|
||||
hback-porch = <160>;
|
||||
hfront-porch = <24>;
|
||||
hsync-len = <136>;
|
||||
vback-porch = <3>;
|
||||
vfront-porch = <61>;
|
||||
vsync-len = <6>;
|
||||
hsync-active = <1>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
hdmi@54280000 {
|
||||
status = "okay";
|
||||
|
||||
vdd-supply = <&hdmi_vdd_reg>;
|
||||
pll-supply = <&hdmi_pll_reg>;
|
||||
|
||||
nvidia,ddc-i2c-bus = <&hdmi_ddc>;
|
||||
nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7)
|
||||
GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
};
|
||||
|
||||
pinmux@70000014 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&state_default>;
|
||||
|
||||
state_default: pinmux {
|
||||
ata {
|
||||
nvidia,pins = "ata", "atc", "atd", "ate",
|
||||
"dap2", "gmb", "gmc", "gmd", "spia",
|
||||
"spib", "spic", "spid", "spie";
|
||||
nvidia,function = "gmi";
|
||||
};
|
||||
atb {
|
||||
nvidia,pins = "atb", "gma", "gme";
|
||||
nvidia,function = "sdio4";
|
||||
};
|
||||
cdev1 {
|
||||
nvidia,pins = "cdev1";
|
||||
nvidia,function = "plla_out";
|
||||
};
|
||||
cdev2 {
|
||||
nvidia,pins = "cdev2";
|
||||
nvidia,function = "pllp_out4";
|
||||
};
|
||||
crtp {
|
||||
nvidia,pins = "crtp";
|
||||
nvidia,function = "crt";
|
||||
};
|
||||
csus {
|
||||
nvidia,pins = "csus";
|
||||
nvidia,function = "pllc_out1";
|
||||
};
|
||||
dap1 {
|
||||
nvidia,pins = "dap1";
|
||||
nvidia,function = "dap1";
|
||||
};
|
||||
dap3 {
|
||||
nvidia,pins = "dap3";
|
||||
nvidia,function = "dap3";
|
||||
};
|
||||
dap4 {
|
||||
nvidia,pins = "dap4";
|
||||
nvidia,function = "dap4";
|
||||
};
|
||||
ddc {
|
||||
nvidia,pins = "ddc";
|
||||
nvidia,function = "i2c2";
|
||||
};
|
||||
dta {
|
||||
nvidia,pins = "dta", "dtb", "dtc", "dtd", "dte";
|
||||
nvidia,function = "rsvd1";
|
||||
};
|
||||
dtf {
|
||||
nvidia,pins = "dtf";
|
||||
nvidia,function = "i2c3";
|
||||
};
|
||||
gpu {
|
||||
nvidia,pins = "gpu", "sdb", "sdd";
|
||||
nvidia,function = "pwm";
|
||||
};
|
||||
gpu7 {
|
||||
nvidia,pins = "gpu7";
|
||||
nvidia,function = "rtck";
|
||||
};
|
||||
gpv {
|
||||
nvidia,pins = "gpv", "slxa", "slxk";
|
||||
nvidia,function = "pcie";
|
||||
};
|
||||
hdint {
|
||||
nvidia,pins = "hdint", "pta";
|
||||
nvidia,function = "hdmi";
|
||||
};
|
||||
i2cp {
|
||||
nvidia,pins = "i2cp";
|
||||
nvidia,function = "i2cp";
|
||||
};
|
||||
irrx {
|
||||
nvidia,pins = "irrx", "irtx";
|
||||
nvidia,function = "uarta";
|
||||
};
|
||||
kbca {
|
||||
nvidia,pins = "kbca", "kbcc", "kbce", "kbcf";
|
||||
nvidia,function = "kbc";
|
||||
};
|
||||
kbcb {
|
||||
nvidia,pins = "kbcb", "kbcd";
|
||||
nvidia,function = "sdio2";
|
||||
};
|
||||
lcsn {
|
||||
nvidia,pins = "lcsn", "ld0", "ld1", "ld2",
|
||||
"ld3", "ld4", "ld5", "ld6", "ld7",
|
||||
"ld8", "ld9", "ld10", "ld11", "ld12",
|
||||
"ld13", "ld14", "ld15", "ld16", "ld17",
|
||||
"ldc", "ldi", "lhp0", "lhp1", "lhp2",
|
||||
"lhs", "lm0", "lm1", "lpp", "lpw0",
|
||||
"lpw1", "lpw2", "lsc0", "lsc1", "lsck",
|
||||
"lsda", "lsdi", "lspi", "lvp0", "lvp1",
|
||||
"lvs";
|
||||
nvidia,function = "displaya";
|
||||
};
|
||||
owc {
|
||||
nvidia,pins = "owc";
|
||||
nvidia,function = "owr";
|
||||
};
|
||||
pmc {
|
||||
nvidia,pins = "pmc";
|
||||
nvidia,function = "pwr_on";
|
||||
};
|
||||
rm {
|
||||
nvidia,pins = "rm";
|
||||
nvidia,function = "i2c1";
|
||||
};
|
||||
sdc {
|
||||
nvidia,pins = "sdc";
|
||||
nvidia,function = "twc";
|
||||
};
|
||||
sdio1 {
|
||||
nvidia,pins = "sdio1";
|
||||
nvidia,function = "sdio1";
|
||||
};
|
||||
slxc {
|
||||
nvidia,pins = "slxc", "slxd";
|
||||
nvidia,function = "spi4";
|
||||
};
|
||||
spdi {
|
||||
nvidia,pins = "spdi", "spdo";
|
||||
nvidia,function = "rsvd2";
|
||||
};
|
||||
spif {
|
||||
nvidia,pins = "spif", "uac";
|
||||
nvidia,function = "rsvd4";
|
||||
};
|
||||
spig {
|
||||
nvidia,pins = "spig", "spih";
|
||||
nvidia,function = "spi2_alt";
|
||||
};
|
||||
uaa {
|
||||
nvidia,pins = "uaa", "uab", "uda";
|
||||
nvidia,function = "ulpi";
|
||||
};
|
||||
uad {
|
||||
nvidia,pins = "uad";
|
||||
nvidia,function = "spdif";
|
||||
};
|
||||
uca {
|
||||
nvidia,pins = "uca", "ucb";
|
||||
nvidia,function = "uartc";
|
||||
};
|
||||
conf_ata {
|
||||
nvidia,pins = "ata", "atb", "atc", "atd", "ate",
|
||||
"cdev1", "cdev2", "dap1", "dap2", "dtf",
|
||||
"gma", "gmb", "gmc", "gmd", "gme",
|
||||
"gpu", "gpu7", "gpv", "i2cp", "pta",
|
||||
"rm", "sdio1", "slxk", "spdo", "uac",
|
||||
"uda";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
};
|
||||
conf_ck32 {
|
||||
nvidia,pins = "ck32", "ddrc", "pmca", "pmcb",
|
||||
"pmcc", "pmcd", "pmce", "xm2c", "xm2d";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
};
|
||||
conf_crtp {
|
||||
nvidia,pins = "crtp", "dap3", "dap4", "dtb",
|
||||
"dtc", "dte", "slxa", "slxc", "slxd",
|
||||
"spdi";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
conf_csus {
|
||||
nvidia,pins = "csus", "spia", "spib", "spid",
|
||||
"spif";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
||||
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
conf_ddc {
|
||||
nvidia,pins = "ddc", "irrx", "irtx", "kbca",
|
||||
"kbcb", "kbcc", "kbcd", "kbce", "kbcf",
|
||||
"spic", "spig", "uaa", "uab";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
};
|
||||
conf_dta {
|
||||
nvidia,pins = "dta", "dtd", "owc", "sdc", "sdd",
|
||||
"spie", "spih", "uad", "uca", "ucb";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
||||
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
conf_hdint {
|
||||
nvidia,pins = "hdint", "ld0", "ld1", "ld2",
|
||||
"ld3", "ld4", "ld5", "ld6", "ld7",
|
||||
"ld8", "ld9", "ld10", "ld11", "ld12",
|
||||
"ld13", "ld14", "ld15", "ld16", "ld17",
|
||||
"ldc", "ldi", "lhs", "lsc0", "lspi",
|
||||
"lvs", "pmc";
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
};
|
||||
conf_lc {
|
||||
nvidia,pins = "lc", "ls";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
||||
};
|
||||
conf_lcsn {
|
||||
nvidia,pins = "lcsn", "lhp0", "lhp1", "lhp2",
|
||||
"lm0", "lm1", "lpp", "lpw0", "lpw1",
|
||||
"lpw2", "lsc1", "lsck", "lsda", "lsdi",
|
||||
"lvp0", "lvp1", "sdb";
|
||||
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
conf_ld17_0 {
|
||||
nvidia,pins = "ld17_0", "ld19_18", "ld21_20",
|
||||
"ld23_22";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
i2s@70002800 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
serial@70006000 {
|
||||
clock-frequency = < 216000000 >;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
serial@70006200 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
pwm: pwm@7000a000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
lvds_ddc: i2c@7000c000 {
|
||||
status = "okay";
|
||||
clock-frequency = <400000>;
|
||||
|
||||
alc5632: alc5632@1e {
|
||||
compatible = "realtek,alc5632";
|
||||
reg = <0x1e>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
};
|
||||
};
|
||||
|
||||
hdmi_ddc: i2c@7000c400 {
|
||||
status = "okay";
|
||||
clock-frequency = <100000>;
|
||||
};
|
||||
|
||||
nvec@7000c500 {
|
||||
compatible = "nvidia,nvec";
|
||||
reg = <0x7000c500 0x100>;
|
||||
interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
clock-frequency = <80000>;
|
||||
request-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_HIGH>;
|
||||
slave-addr = <138>;
|
||||
clocks = <&tegra_car TEGRA20_CLK_I2C3>,
|
||||
<&tegra_car TEGRA20_CLK_PLL_P_OUT3>;
|
||||
clock-names = "div-clk", "fast-clk";
|
||||
resets = <&tegra_car 67>;
|
||||
reset-names = "i2c";
|
||||
};
|
||||
|
||||
i2c@7000d000 {
|
||||
status = "okay";
|
||||
clock-frequency = <400000>;
|
||||
|
||||
pmic: tps6586x@34 {
|
||||
compatible = "ti,tps6586x";
|
||||
reg = <0x34>;
|
||||
interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
|
||||
|
||||
#gpio-cells = <2>;
|
||||
gpio-controller;
|
||||
|
||||
sys-supply = <&p5valw_reg>;
|
||||
vin-sm0-supply = <&sys_reg>;
|
||||
vin-sm1-supply = <&sys_reg>;
|
||||
vin-sm2-supply = <&sys_reg>;
|
||||
vinldo01-supply = <&sm2_reg>;
|
||||
vinldo23-supply = <&sm2_reg>;
|
||||
vinldo4-supply = <&sm2_reg>;
|
||||
vinldo678-supply = <&sm2_reg>;
|
||||
vinldo9-supply = <&sm2_reg>;
|
||||
|
||||
regulators {
|
||||
sys_reg: sys {
|
||||
regulator-name = "vdd_sys";
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
sm0 {
|
||||
regulator-name = "+1.2vs_sm0,vdd_core";
|
||||
regulator-min-microvolt = <1200000>;
|
||||
regulator-max-microvolt = <1200000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
sm1 {
|
||||
regulator-name = "+1.0vs_sm1,vdd_cpu";
|
||||
regulator-min-microvolt = <1000000>;
|
||||
regulator-max-microvolt = <1000000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
sm2_reg: sm2 {
|
||||
regulator-name = "+3.7vs_sm2,vin_ldo*";
|
||||
regulator-min-microvolt = <3700000>;
|
||||
regulator-max-microvolt = <3700000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
/* LDO0 is not connected to anything */
|
||||
|
||||
ldo1 {
|
||||
regulator-name = "+1.1vs_ldo1,avdd_pll*";
|
||||
regulator-min-microvolt = <1100000>;
|
||||
regulator-max-microvolt = <1100000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
ldo2 {
|
||||
regulator-name = "+1.2vs_ldo2,vdd_rtc";
|
||||
regulator-min-microvolt = <1200000>;
|
||||
regulator-max-microvolt = <1200000>;
|
||||
};
|
||||
|
||||
ldo3 {
|
||||
regulator-name = "+3.3vs_ldo3,avdd_usb*";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
ldo4 {
|
||||
regulator-name = "+1.8vs_ldo4,avdd_osc,vddio_sys";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
ldo5 {
|
||||
regulator-name = "+2.85vs_ldo5,vcore_mmc";
|
||||
regulator-min-microvolt = <2850000>;
|
||||
regulator-max-microvolt = <2850000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
ldo6 {
|
||||
/*
|
||||
* Research indicates this should be
|
||||
* 1.8v; other boards that use this
|
||||
* rail for the same purpose need it
|
||||
* set to 1.8v. The schematic signal
|
||||
* name is incorrect; perhaps copied
|
||||
* from an incorrect NVIDIA reference.
|
||||
*/
|
||||
regulator-name = "+2.85vs_ldo6,avdd_vdac";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
};
|
||||
|
||||
hdmi_vdd_reg: ldo7 {
|
||||
regulator-name = "+3.3vs_ldo7,avdd_hdmi";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
};
|
||||
|
||||
hdmi_pll_reg: ldo8 {
|
||||
regulator-name = "+1.8vs_ldo8,avdd_hdmi_pll";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
};
|
||||
|
||||
ldo9 {
|
||||
regulator-name = "+2.85vs_ldo9,vdd_ddr_rx";
|
||||
regulator-min-microvolt = <2850000>;
|
||||
regulator-max-microvolt = <2850000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
ldo_rtc {
|
||||
regulator-name = "+3.3vs_rtc";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
adt7461@4c {
|
||||
compatible = "adi,adt7461";
|
||||
reg = <0x4c>;
|
||||
};
|
||||
};
|
||||
|
||||
pmc@7000e400 {
|
||||
nvidia,invert-interrupt;
|
||||
nvidia,suspend-mode = <1>;
|
||||
nvidia,cpu-pwr-good-time = <2000>;
|
||||
nvidia,cpu-pwr-off-time = <0>;
|
||||
nvidia,core-pwr-good-time = <3845 3845>;
|
||||
nvidia,core-pwr-off-time = <0>;
|
||||
nvidia,sys-clock-req-active-high;
|
||||
};
|
||||
|
||||
usb@c5000000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
usb-phy@c5000000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
usb@c5004000 {
|
||||
status = "okay";
|
||||
nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 0)
|
||||
GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
|
||||
usb-phy@c5004000 {
|
||||
status = "okay";
|
||||
nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 0)
|
||||
GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
|
||||
usb@c5008000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
usb-phy@c5008000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
sdhci@c8000000 {
|
||||
status = "okay";
|
||||
cd-gpios = <&gpio TEGRA_GPIO(V, 5) GPIO_ACTIVE_LOW>;
|
||||
@ -53,6 +516,19 @@
|
||||
non-removable;
|
||||
};
|
||||
|
||||
backlight: backlight {
|
||||
compatible = "pwm-backlight";
|
||||
|
||||
enable-gpios = <&gpio TEGRA_GPIO(U, 4) GPIO_ACTIVE_HIGH>;
|
||||
power-supply = <&vdd_bl_reg>;
|
||||
pwms = <&pwm 0 5000000>;
|
||||
|
||||
brightness-levels = <0 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240 255>;
|
||||
default-brightness-level = <10>;
|
||||
|
||||
backlight-boot-off;
|
||||
};
|
||||
|
||||
clocks {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
@ -60,38 +536,101 @@
|
||||
|
||||
clk32k_in: clock@0 {
|
||||
compatible = "fixed-clock";
|
||||
reg=<0>;
|
||||
reg = <0>;
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <32768>;
|
||||
};
|
||||
};
|
||||
|
||||
pwm: pwm@7000a000 {
|
||||
status = "okay";
|
||||
gpio-keys {
|
||||
compatible = "gpio-keys";
|
||||
|
||||
power {
|
||||
label = "Power";
|
||||
gpios = <&gpio TEGRA_GPIO(J, 7) GPIO_ACTIVE_LOW>;
|
||||
linux,code = <KEY_POWER>;
|
||||
wakeup-source;
|
||||
};
|
||||
};
|
||||
|
||||
lcd_panel: panel {
|
||||
/* PAZ00 has 1024x600 */
|
||||
clock = <54030000>;
|
||||
xres = <1024>;
|
||||
yres = <600>;
|
||||
right-margin = <160>;
|
||||
left-margin = <24>;
|
||||
hsync-len = <136>;
|
||||
upper-margin = <3>;
|
||||
lower-margin = <61>;
|
||||
vsync-len = <6>;
|
||||
hsync-active-high;
|
||||
nvidia,bits-per-pixel = <16>;
|
||||
nvidia,pwm = <&pwm 0 0>;
|
||||
nvidia,backlight-enable-gpios = <&gpio TEGRA_GPIO(U, 4)
|
||||
GPIO_ACTIVE_HIGH>;
|
||||
nvidia,lvds-shutdown-gpios = <&gpio TEGRA_GPIO(M, 6)
|
||||
GPIO_ACTIVE_HIGH>;
|
||||
nvidia,backlight-vdd-gpios = <&gpio TEGRA_GPIO(W, 0)
|
||||
GPIO_ACTIVE_HIGH>;
|
||||
nvidia,panel-vdd-gpios = <&gpio TEGRA_GPIO(A, 4)
|
||||
GPIO_ACTIVE_HIGH>;
|
||||
nvidia,panel-timings = <400 4 203 17 15>;
|
||||
gpio-leds {
|
||||
compatible = "gpio-leds";
|
||||
|
||||
wifi {
|
||||
label = "wifi-led";
|
||||
gpios = <&gpio TEGRA_GPIO(D, 0) GPIO_ACTIVE_HIGH>;
|
||||
linux,default-trigger = "rfkill0";
|
||||
};
|
||||
};
|
||||
|
||||
panel: panel {
|
||||
compatible = "samsung,ltn101nt05", "simple-panel";
|
||||
|
||||
ddc-i2c-bus = <&lvds_ddc>;
|
||||
power-supply = <&vdd_pnl_reg>;
|
||||
enable-gpios = <&gpio TEGRA_GPIO(M, 6) GPIO_ACTIVE_HIGH>;
|
||||
|
||||
backlight = <&backlight>;
|
||||
};
|
||||
|
||||
regulators {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
p5valw_reg: regulator@0 {
|
||||
compatible = "regulator-fixed";
|
||||
reg = <0>;
|
||||
regulator-name = "+5valw";
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
vdd_pnl_reg: regulator@1 {
|
||||
compatible = "regulator-fixed";
|
||||
reg = <1>;
|
||||
regulator-name = "+3VS,vdd_pnl";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
gpio = <&gpio TEGRA_GPIO(A, 4) GPIO_ACTIVE_HIGH>;
|
||||
enable-active-high;
|
||||
};
|
||||
|
||||
vdd_bl_reg: regulator@2 {
|
||||
compatible = "regulator-fixed";
|
||||
reg = <2>;
|
||||
regulator-name = "vdd_bl";
|
||||
regulator-min-microvolt = <2800000>;
|
||||
regulator-max-microvolt = <2800000>;
|
||||
gpio = <&gpio TEGRA_GPIO(W, 0) GPIO_ACTIVE_HIGH>;
|
||||
enable-active-high;
|
||||
};
|
||||
};
|
||||
|
||||
sound {
|
||||
compatible = "nvidia,tegra-audio-alc5632-paz00",
|
||||
"nvidia,tegra-audio-alc5632";
|
||||
|
||||
nvidia,model = "Compal PAZ00";
|
||||
|
||||
nvidia,audio-routing =
|
||||
"Int Spk", "SPKOUT",
|
||||
"Int Spk", "SPKOUTN",
|
||||
"Headset Mic", "MICBIAS1",
|
||||
"MIC1", "Headset Mic",
|
||||
"Headset Stereophone", "HPR",
|
||||
"Headset Stereophone", "HPL",
|
||||
"DMICDAT", "Digital Mic";
|
||||
|
||||
nvidia,audio-codec = <&alc5632>;
|
||||
nvidia,i2s-controller = <&tegra_i2s1>;
|
||||
nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2)
|
||||
GPIO_ACTIVE_HIGH>;
|
||||
|
||||
clocks = <&tegra_car TEGRA20_CLK_PLL_A>,
|
||||
<&tegra_car TEGRA20_CLK_PLL_A_OUT0>,
|
||||
<&tegra_car TEGRA20_CLK_CDEV1>;
|
||||
clock-names = "pll_a", "pll_a_out0", "mclk";
|
||||
};
|
||||
};
|
||||
|
||||
@ -44,10 +44,12 @@
|
||||
hvdd-pex-supply = <&sys_3v3_reg>;
|
||||
|
||||
pci@1,0 {
|
||||
/* TS_DIFF1/2/3/4 left disabled */
|
||||
nvidia,num-lanes = <4>;
|
||||
};
|
||||
|
||||
pci@2,0 {
|
||||
/* PCIE1_RX/TX left disabled */
|
||||
nvidia,num-lanes = <1>;
|
||||
};
|
||||
|
||||
|
||||
@ -11,6 +11,19 @@
|
||||
|
||||
extern unsigned long nvtboot_boot_x0;
|
||||
|
||||
static int set_fdt_addr(void)
|
||||
{
|
||||
int ret;
|
||||
|
||||
ret = setenv_hex("fdt_addr", nvtboot_boot_x0);
|
||||
if (ret) {
|
||||
printf("Failed to set fdt_addr to point at DTB: %d\n", ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*
|
||||
* Attempt to use /chosen/nvidia,ether-mac in the nvtboot DTB to U-Boot's
|
||||
* ethaddr environment variable if possible.
|
||||
@ -47,6 +60,11 @@ static int set_ethaddr_from_nvtboot(void)
|
||||
|
||||
int tegra_soc_board_init_late(void)
|
||||
{
|
||||
/*
|
||||
* Ignore errors here; the value may not be used depending on
|
||||
* extlinux.conf or boot script content.
|
||||
*/
|
||||
set_fdt_addr();
|
||||
/* Ignore errors here; not all cases care about Ethernet addresses */
|
||||
set_ethaddr_from_nvtboot();
|
||||
|
||||
|
||||
@ -9,7 +9,7 @@ menuconfig PCI
|
||||
if PCI
|
||||
|
||||
config DM_PCI
|
||||
bool "Enable driver mode for PCI"
|
||||
bool "Enable driver model for PCI"
|
||||
depends on DM
|
||||
help
|
||||
Use driver model for PCI. Driver model is the new method for
|
||||
|
||||
@ -343,7 +343,7 @@ static int display_init(struct udevice *dev, void *lcdbase,
|
||||
|
||||
/*
|
||||
* Before we probe the display device (eDP), tell it that this device
|
||||
* is are the source of the display data.
|
||||
* is the source of the display data.
|
||||
*/
|
||||
ret = uclass_find_first_device(UCLASS_DISPLAY, &dp_dev);
|
||||
if (ret) {
|
||||
|
||||
Loading…
Reference in New Issue
Block a user