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imx: mx6: fix mmdc ch0 clk for 6SL

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>From RM, per_periph2_clk_sel option3 is:
"derive clock from 198MHz clock (divided 392MHz PLL2 PFD)."

So fix it.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
This commit is contained in:
Peng Fan 2016-12-11 19:24:25 +08:00 committed by Stefano Babic
parent 40913fb595
commit 0e81982de0
1 changed files with 5 additions and 0 deletions
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5
arch/arm/cpu/armv7/mx6/clock.c
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@ -514,6 +514,11 @@ static u32 get_mmdc_ch0_clk(void)
freq = mxc_get_pll_pfd(PLL_BUS, 0);
break;
case 3:
if (is_mx6sl()) {
freq = mxc_get_pll_pfd(PLL_BUS, 2) >> 1;
break;
}
pmu_misc2_audio_div = PMU_MISC2_AUDIO_DIV(__raw_readl(&imx_ccm->pmu_misc2));
switch (pmu_misc2_audio_div) {
case 0: