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https://github.com/brain-hackers/u-boot-brain
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Merge branch 'master' of git://git.denx.de/u-boot-ppc4xx
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commit
0e0c0892a1
@ -221,6 +221,66 @@ void reconfigure_pll(u32 new_cpu_freq)
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#endif
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#endif
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}
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}
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#ifdef CONFIG_SYS_4xx_CHIP_21_ERRATA
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void
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chip_21_errata(void)
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{
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/*
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* See rev 1.09 of the 405EX/405EXr errata. CHIP_21 says that
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* sometimes reading the PVR and/or SDR0_ECID results in incorrect
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* values. Since the rev-D chip uses the SDR0_ECID bits to control
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* internal features, that means the second PCIe or ethernet of an EX
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* variant could fail to work. Also, security features of both EX and
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* EXr might be incorrectly disabled.
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*
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* The suggested workaround is as follows (covering rev-C and rev-D):
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*
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* 1.Read the PVR and SDR0_ECID3.
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*
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* 2.If the PVR matches an expected Revision C PVR value AND if
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* SDR0_ECID3[12:15] is different from PVR[28:31], then processor is
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* Revision C: continue executing the initialization code (no reset
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* required). else go to step 3.
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*
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* 3.If the PVR matches an expected Revision D PVR value AND if
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* SDR0_ECID3[10:11] matches its expected value, then continue
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* executing initialization code, no reset required. else write
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* DBCR0[RST] = 0b11 to generate a SysReset.
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*/
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u32 pvr;
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u32 pvr_28_31;
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u32 ecid3;
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u32 ecid3_10_11;
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u32 ecid3_12_15;
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/* Step 1: */
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pvr = get_pvr();
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mfsdr(SDR0_ECID3, ecid3);
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/* Step 2: */
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pvr_28_31 = pvr & 0xf;
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ecid3_10_11 = (ecid3 >> 20) & 0x3;
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ecid3_12_15 = (ecid3 >> 16) & 0xf;
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if ((pvr == CONFIG_405EX_CHIP21_PVR_REV_C) &&
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(pvr_28_31 != ecid3_12_15)) {
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/* No reset required. */
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return;
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}
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/* Step 3: */
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if ((pvr == CONFIG_405EX_CHIP21_PVR_REV_D) &&
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(ecid3_10_11 == CONFIG_405EX_CHIP21_ECID3_REV_D)) {
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/* No reset required. */
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return;
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}
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/* Reset required. */
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__asm__ __volatile__ ("sync; isync");
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mtspr(SPRN_DBCR0, 0x30000000);
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}
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#endif
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/*
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/*
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* Breath some life into the CPU...
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* Breath some life into the CPU...
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*
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*
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@ -235,6 +295,10 @@ cpu_init_f (void)
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u32 val;
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u32 val;
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#endif
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#endif
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#ifdef CONFIG_SYS_4xx_CHIP_21_ERRATA
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chip_21_errata();
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#endif
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reconfigure_pll(CONFIG_SYS_PLL_RECONFIG);
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reconfigure_pll(CONFIG_SYS_PLL_RECONFIG);
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#if (defined(CONFIG_405EP) || defined (CONFIG_405EX)) && \
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#if (defined(CONFIG_405EP) || defined (CONFIG_405EX)) && \
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@ -43,6 +43,11 @@
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#define SDR0_PFC1 0x4101
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#define SDR0_PFC1 0x4101
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#define SDR0_MFR 0x4300 /* SDR0_MFR reg */
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#define SDR0_MFR 0x4300 /* SDR0_MFR reg */
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#define SDR0_ECID0 0x0080
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#define SDR0_ECID1 0x0081
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#define SDR0_ECID2 0x0082
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#define SDR0_ECID3 0x0083
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#define SDR0_SDCS_SDD (0x80000000 >> 31)
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#define SDR0_SDCS_SDD (0x80000000 >> 31)
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#define SDR0_SRST_DMC (0x80000000 >> 10)
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#define SDR0_SRST_DMC (0x80000000 >> 10)
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@ -973,6 +973,37 @@
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#define PVR_5200 0x80822011
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#define PVR_5200 0x80822011
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#define PVR_5200B 0x80822014
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#define PVR_5200B 0x80822014
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/*
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* 405EX/EXr CHIP_21 Errata
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*/
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#ifdef CONFIG_SYS_4xx_CHIP_21_405EX_SECURITY
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#define CONFIG_SYS_4xx_CHIP_21_ERRATA
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#define CONFIG_405EX_CHIP21_PVR_REV_C PVR_405EX1_RC
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#define CONFIG_405EX_CHIP21_PVR_REV_D PVR_405EX1_RD
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#define CONFIG_405EX_CHIP21_ECID3_REV_D 0x0
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#endif
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#ifdef CONFIG_SYS_4xx_CHIP_21_405EX_NO_SECURITY
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#define CONFIG_SYS_4xx_CHIP_21_ERRATA
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#define CONFIG_405EX_CHIP21_PVR_REV_C PVR_405EX2_RC
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#define CONFIG_405EX_CHIP21_PVR_REV_D PVR_405EX2_RD
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#define CONFIG_405EX_CHIP21_ECID3_REV_D 0x1
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#endif
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#ifdef CONFIG_SYS_4xx_CHIP_21_405EXr_SECURITY
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#define CONFIG_SYS_4xx_CHIP_21_ERRATA
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#define CONFIG_405EX_CHIP21_PVR_REV_C PVR_405EXR1_RC
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#define CONFIG_405EX_CHIP21_PVR_REV_D PVR_405EXR1_RD
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#define CONFIG_405EX_CHIP21_ECID3_REV_D 0x2
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#endif
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#ifdef CONFIG_SYS_4xx_CHIP_21_405EXr_NO_SECURITY
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#define CONFIG_SYS_4xx_CHIP_21_ERRATA
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#define CONFIG_405EX_CHIP21_PVR_REV_C PVR_405EXR2_RC
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#define CONFIG_405EX_CHIP21_PVR_REV_D PVR_405EXR2_RD
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#define CONFIG_405EX_CHIP21_ECID3_REV_D 0x3
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#endif
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/*
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/*
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* System Version Register
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* System Version Register
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*/
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*/
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@ -43,6 +43,20 @@
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#define CONFIG_SYS_TEXT_BASE 0xFFFA0000
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#define CONFIG_SYS_TEXT_BASE 0xFFFA0000
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#endif
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#endif
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/*
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* CHIP_21 errata - you must set this to match your exact CPU, else your
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* board will not boot. DO NOT enable this unless you have JTAG available
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* for recovery, in the event you get it wrong.
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*
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* Kilauea uses the 405EX, while Haleakala uses the 405EXr. Either board
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* may be equipped for security or not. You must look at the CPU part
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* number to be sure what you have.
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*/
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/* #define CONFIG_SYS_4xx_CHIP_21_405EX_NO_SECURITY */
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/* #define CONFIG_SYS_4xx_CHIP_21_405EX_SECURITY */
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/* #define CONFIG_SYS_4xx_CHIP_21_405EXr_NO_SECURITY */
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/* #define CONFIG_SYS_4xx_CHIP_21_405EXr_SECURITY */
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/*
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/*
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* Include common defines/options for all AMCC eval boards
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* Include common defines/options for all AMCC eval boards
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*/
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*/
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