diff --git a/arch/arm/cpu/armv7/exynos/dmc_init_ddr3.c b/arch/arm/cpu/armv7/exynos/dmc_init_ddr3.c
index 4d73b45435..7c0b12ae51 100644
--- a/arch/arm/cpu/armv7/exynos/dmc_init_ddr3.c
+++ b/arch/arm/cpu/armv7/exynos/dmc_init_ddr3.c
@@ -464,6 +464,16 @@ int ddr3_mem_ctrl_init(struct mem_timings *mem, int reset)
 							+ DMC_OFFSET);
 	pmu = (struct exynos5_power *)EXYNOS5420_POWER_BASE;
 
+	if (CONFIG_NR_DRAM_BANKS > 4) {
+		/* Need both controllers. */
+		mem->memcontrol |= DMC_MEMCONTROL_NUM_CHIP_2;
+		mem->chips_per_channel = 2;
+		mem->chips_to_configure = 2;
+	} else {
+		/* 2GB requires a single controller */
+		mem->memcontrol |= DMC_MEMCONTROL_NUM_CHIP_1;
+	}
+
 	/* Enable PAUSE for DREX */
 	setbits_le32(&clk->pause, ENABLE_BIT);