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arch: armv8: fsl-layerscape: export serdes config to environment
Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
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@ -242,6 +242,7 @@ config FSL_LSCH2
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select SYS_FSL_SEC_BE
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config FSL_LSCH3
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select ARCH_MISC_INIT
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bool
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config NXP_LSCH3_2
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@ -1632,3 +1632,17 @@ __weak int dram_init(void)
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return 0;
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}
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#ifdef CONFIG_ARCH_MISC_INIT
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__weak int serdes_misc_init(void)
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{
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return 0;
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}
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int arch_misc_init(void)
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{
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serdes_misc_init();
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return 0;
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}
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#endif
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@ -600,3 +600,62 @@ void fsl_serdes_init(void)
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serdes3_prtcl_map);
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#endif
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}
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int serdes_set_env(int sd, int rcwsr, int sd_prctl_mask, int sd_prctl_shift)
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{
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struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
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char scfg[16], snum[16];
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int cfgr = 0;
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u32 cfg;
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cfg = gur_in32(&gur->rcwsr[rcwsr - 1]) & sd_prctl_mask;
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cfg >>= sd_prctl_shift;
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cfg = serdes_get_number(sd, cfg);
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#if defined(SRDS_BITS_PER_LANE)
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/*
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* reverse lanes, lane 0 should be printed first so it must be moved to
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* high order bits.
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* For example bb58 should read 85bb, lane 0 being protocol 8.
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* This only applies to SoCs that define SRDS_BITS_PER_LANE and have
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* independent per-lane protocol configuration, at this time LS1028A and
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* LS1088A. LS2 and LX2 SoCs encode the full protocol mix across all
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* lanes as a single value.
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*/
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for (int i = 0; i < SRDS_MAX_LANES; i++) {
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int tmp;
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tmp = cfg >> (i * SRDS_BITS_PER_LANE);
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tmp &= GENMASK(SRDS_BITS_PER_LANE - 1, 0);
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tmp <<= (SRDS_MAX_LANES - i - 1) * SRDS_BITS_PER_LANE;
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cfgr |= tmp;
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}
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#endif /* SRDS_BITS_PER_LANE */
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snprintf(snum, 16, "serdes%d", sd);
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snprintf(scfg, 16, "%x", cfgr);
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env_set(snum, scfg);
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return 0;
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}
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int serdes_misc_init(void)
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{
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#ifdef CONFIG_SYS_FSL_SRDS_1
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serdes_set_env(FSL_SRDS_1, FSL_CHASSIS3_SRDS1_REGSR,
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FSL_CHASSIS3_SRDS1_PRTCL_MASK,
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FSL_CHASSIS3_SRDS1_PRTCL_SHIFT);
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#endif
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#ifdef CONFIG_SYS_FSL_SRDS_2
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serdes_set_env(FSL_SRDS_2, FSL_CHASSIS3_SRDS2_REGSR,
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FSL_CHASSIS3_SRDS2_PRTCL_MASK,
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FSL_CHASSIS3_SRDS2_PRTCL_SHIFT);
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#endif
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#ifdef CONFIG_SYS_NXP_SRDS_3
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serdes_set_env(NXP_SRDS_3, FSL_CHASSIS3_SRDS3_REGSR,
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FSL_CHASSIS3_SRDS3_PRTCL_MASK,
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FSL_CHASSIS3_SRDS3_PRTCL_SHIFT);
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#endif
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return 0;
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}
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@ -123,6 +123,7 @@
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#define CONFIG_SYS_PAGE_SIZE 0x10000
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#define SRDS_MAX_LANES 4
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#define SRDS_BITS_PER_LANE 4
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/* TZ Protection Controller Definitions */
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#define TZPC_BASE 0x02200000
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@ -252,6 +253,7 @@
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#define TZPCDECPROT_2_CLR_BASE (TZPC_BASE + 0x820)
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#define SRDS_MAX_LANES 4
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#define SRDS_BITS_PER_LANE 4
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#define CONFIG_SYS_FSL_OCRAM_BASE 0x18000000 /* initial RAM */
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#define SYS_FSL_OCRAM_SPACE_SIZE 0x00200000 /* 2M */
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