mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-06-09 23:36:03 +09:00
imx: support i.MX8QM MEK board
Add i.MX8QM MEK board support. Included a basic dts, enabled SPL FIT Boot log as below: U-Boot SPL 2019.01-rc1-00029-gf002213219 (Dec 24 2018 - 10:28:30 +0800) Normal Boot Trying to boot from MMC2_2 U-Boot 2019.01-rc1-00029-gf002213219 (Dec 24 2018 - 10:28:30 +0800) CPU: NXP i.MX8QM RevB A53 at 142933 MHz Model: Freescale i.MX8QM MEK Board: iMX8QM MEK Build: SCFW 9330215b Boot: SD1 DRAM: 6 GiB MMC: FSL_SDHC: 0, FSL_SDHC: 1 Loading Environment from MMC... *** Warning - bad CRC, using default environment In: serial@5a060000 Out: serial@5a060000 Err: serial@5a060000 Net: Error: ethernet@5b040000 address not set. eth-1: ethernet@5b040000 Hit any key to stop autoboot: 0 Signed-off-by: Peng Fan <peng.fan@nxp.com>
This commit is contained in:
Peng Fan
Stefano Babic
parent
894e02b7b0
commit
0d331c035a
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@ -561,7 +561,9 @@ dtb-$(CONFIG_MX7) += imx7d-sdb.dtb \
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dtb-$(CONFIG_ARCH_MX7ULP) += imx7ulp-evk.dtb
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dtb-$(CONFIG_ARCH_IMX8) += fsl-imx8qxp-mek.dtb
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dtb-$(CONFIG_ARCH_IMX8) += \
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fsl-imx8qxp-mek.dtb \
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fsl-imx8qm-mek.dtb \
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dtb-$(CONFIG_ARCH_IMX8M) += fsl-imx8mq-evk.dtb
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112
arch/arm/dts/fsl-imx8qm-mek-u-boot.dtsi
Normal file
112
arch/arm/dts/fsl-imx8qm-mek-u-boot.dtsi
Normal file
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@ -0,0 +1,112 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright 2018 NXP
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*/
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&mu {
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u-boot,dm-spl;
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};
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&clk {
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u-boot,dm-spl;
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};
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&iomuxc {
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u-boot,dm-spl;
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};
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&pd_lsio {
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u-boot,dm-spl;
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};
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&pd_lsio_gpio0 {
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u-boot,dm-spl;
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};
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&pd_lsio_gpio1 {
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u-boot,dm-spl;
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};
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&pd_lsio_gpio2 {
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u-boot,dm-spl;
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};
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&pd_lsio_gpio3 {
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u-boot,dm-spl;
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};
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&pd_lsio_gpio4 {
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u-boot,dm-spl;
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};
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&pd_lsio_gpio5 {
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u-boot,dm-spl;
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};
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&pd_lsio_gpio6 {
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u-boot,dm-spl;
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};
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&pd_lsio_gpio7 {
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u-boot,dm-spl;
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};
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&pd_conn {
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u-boot,dm-spl;
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};
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&pd_conn_sdch0 {
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u-boot,dm-spl;
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};
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&pd_conn_sdch1 {
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u-boot,dm-spl;
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};
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&pd_conn_sdch2 {
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u-boot,dm-spl;
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};
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&gpio0 {
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u-boot,dm-spl;
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};
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&gpio1 {
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u-boot,dm-spl;
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};
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&gpio2 {
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u-boot,dm-spl;
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};
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&gpio3 {
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u-boot,dm-spl;
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};
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&gpio4 {
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u-boot,dm-spl;
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};
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&gpio5 {
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u-boot,dm-spl;
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};
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&gpio6 {
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u-boot,dm-spl;
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};
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&gpio7 {
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u-boot,dm-spl;
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};
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&lpuart0 {
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u-boot,dm-spl;
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};
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&usdhc1 {
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u-boot,dm-spl;
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};
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&usdhc2 {
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u-boot,dm-spl;
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};
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184
arch/arm/dts/fsl-imx8qm-mek.dts
Normal file
184
arch/arm/dts/fsl-imx8qm-mek.dts
Normal file
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@ -0,0 +1,184 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright 2017-2018 NXP
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*/
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/dts-v1/;
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#include "fsl-imx8qm.dtsi"
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#include "fsl-imx8qm-mek-u-boot.dtsi"
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/ {
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model = "Freescale i.MX8QM MEK";
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compatible = "fsl,imx8qm-mek", "fsl,imx8qm";
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chosen {
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bootargs = "console=ttyLP0,115200 earlycon=lpuart32,0x5a060000,115200";
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stdout-path = &lpuart0;
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};
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reg_usdhc2_vmmc: usdhc2_vmmc {
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compatible = "regulator-fixed";
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regulator-name = "sw-3p3-sd1";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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gpio = <&gpio4 7 GPIO_ACTIVE_HIGH>;
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off-on-delay = <4800>;
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enable-active-high;
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};
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};
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&iomuxc {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_hog>;
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imx8qm-mek {
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pinctrl_hog: hoggrp {
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fsl,pins = <
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SC_P_MCLK_OUT0_AUD_ACM_MCLK_OUT0 0x0600004c
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SC_P_QSPI1A_DATA1_LSIO_GPIO4_IO25 0x0600004c
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SC_P_SCU_GPIO0_03_LSIO_GPIO0_IO31 0x0600004c
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>;
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};
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pinctrl_fec1: fec1grp {
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fsl,pins = <
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SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB_PAD 0x000014a0
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SC_P_ENET0_MDC_CONN_ENET0_MDC 0x06000020
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SC_P_ENET0_MDIO_CONN_ENET0_MDIO 0x06000020
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SC_P_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL 0x00000061
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SC_P_ENET0_RGMII_TXC_CONN_ENET0_RGMII_TXC 0x00000061
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SC_P_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0 0x00000061
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SC_P_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1 0x00000061
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SC_P_ENET0_RGMII_TXD2_CONN_ENET0_RGMII_TXD2 0x00000061
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SC_P_ENET0_RGMII_TXD3_CONN_ENET0_RGMII_TXD3 0x00000061
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SC_P_ENET0_RGMII_RXC_CONN_ENET0_RGMII_RXC 0x00000061
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SC_P_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL 0x00000061
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SC_P_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0 0x00000061
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SC_P_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1 0x00000061
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SC_P_ENET0_RGMII_RXD2_CONN_ENET0_RGMII_RXD2 0x00000061
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SC_P_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3 0x00000061
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>;
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};
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pinctrl_fec2: fec2grp {
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fsl,pins = <
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SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETA_PAD 0x000014a0
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SC_P_ENET1_RGMII_TX_CTL_CONN_ENET1_RGMII_TX_CTL 0x00000060
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SC_P_ENET1_RGMII_TXC_CONN_ENET1_RGMII_TXC 0x00000060
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SC_P_ENET1_RGMII_TXD0_CONN_ENET1_RGMII_TXD0 0x00000060
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SC_P_ENET1_RGMII_TXD1_CONN_ENET1_RGMII_TXD1 0x00000060
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SC_P_ENET1_RGMII_TXD2_CONN_ENET1_RGMII_TXD2 0x00000060
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SC_P_ENET1_RGMII_TXD3_CONN_ENET1_RGMII_TXD3 0x00000060
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SC_P_ENET1_RGMII_RXC_CONN_ENET1_RGMII_RXC 0x00000060
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SC_P_ENET1_RGMII_RX_CTL_CONN_ENET1_RGMII_RX_CTL 0x00000060
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SC_P_ENET1_RGMII_RXD0_CONN_ENET1_RGMII_RXD0 0x00000060
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SC_P_ENET1_RGMII_RXD1_CONN_ENET1_RGMII_RXD1 0x00000060
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SC_P_ENET1_RGMII_RXD2_CONN_ENET1_RGMII_RXD2 0x00000060
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SC_P_ENET1_RGMII_RXD3_CONN_ENET1_RGMII_RXD3 0x00000060
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>;
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};
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pinctrl_lpuart0: lpuart0grp {
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fsl,pins = <
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SC_P_UART0_RX_DMA_UART0_RX 0x06000020
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SC_P_UART0_TX_DMA_UART0_TX 0x06000020
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>;
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};
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pinctrl_usdhc1: usdhc1grp {
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fsl,pins = <
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SC_P_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041
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SC_P_EMMC0_CMD_CONN_EMMC0_CMD 0x00000021
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SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000021
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SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000021
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SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000021
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SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000021
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SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000021
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SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000021
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SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000021
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SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000021
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SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE 0x00000041
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SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x00000021
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>;
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};
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pinctrl_usdhc2_gpio: usdhc2grpgpio {
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fsl,pins = <
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SC_P_USDHC1_DATA6_LSIO_GPIO5_IO21 0x00000021
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SC_P_USDHC1_DATA7_LSIO_GPIO5_IO22 0x00000021
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SC_P_USDHC1_RESET_B_LSIO_GPIO4_IO07 0x00000021
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>;
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};
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pinctrl_usdhc2: usdhc2grp {
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fsl,pins = <
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SC_P_USDHC1_CLK_CONN_USDHC1_CLK 0x06000041
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SC_P_USDHC1_CMD_CONN_USDHC1_CMD 0x00000021
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SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0 0x00000021
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SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1 0x00000021
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SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2 0x00000021
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SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3 0x00000021
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SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000021
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>;
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};
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};
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};
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&usdhc1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_usdhc1>;
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bus-width = <8>;
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non-removable;
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status = "okay";
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};
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&usdhc2 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
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bus-width = <4>;
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cd-gpios = <&gpio5 22 GPIO_ACTIVE_LOW>;
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wp-gpios = <&gpio5 21 GPIO_ACTIVE_HIGH>;
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vmmc-supply = <®_usdhc2_vmmc>;
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status = "okay";
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};
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&fec1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_fec1>;
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phy-mode = "rgmii-txid";
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phy-handle = <ðphy0>;
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fsl,magic-packet;
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fsl,rgmii_rxc_dly;
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status = "okay";
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mdio {
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#address-cells = <1>;
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#size-cells = <0>;
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ethphy0: ethernet-phy@0 {
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compatible = "ethernet-phy-ieee802.3-c22";
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reg = <0>;
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at803x,eee-disabled;
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at803x,vddio-1p8v;
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};
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ethphy1: ethernet-phy@1 {
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compatible = "ethernet-phy-ieee802.3-c22";
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reg = <1>;
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at803x,eee-disabled;
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at803x,vddio-1p8v;
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status = "disabled";
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};
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};
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};
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&lpuart0 { /* console */
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_lpuart0>;
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status = "okay";
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};
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&gpio1 {
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status = "okay";
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};
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@ -32,8 +32,14 @@ config TARGET_IMX8QXP_MEK
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select BOARD_LATE_INIT
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select IMX8QXP
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config TARGET_IMX8QM_MEK
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bool "Support i.MX8QM MEK board"
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select BOARD_LATE_INIT
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select IMX8QM
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endchoice
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source "board/freescale/imx8qxp_mek/Kconfig"
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source "board/freescale/imx8qm_mek/Kconfig"
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endif
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14
board/freescale/imx8qm_mek/Kconfig
Normal file
14
board/freescale/imx8qm_mek/Kconfig
Normal file
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@ -0,0 +1,14 @@
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if TARGET_IMX8QM_MEK
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config SYS_BOARD
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default "imx8qm_mek"
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config SYS_VENDOR
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default "freescale"
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config SYS_CONFIG_NAME
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default "imx8qm_mek"
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source "board/freescale/common/Kconfig"
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endif
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6
board/freescale/imx8qm_mek/MAINTAINERS
Normal file
6
board/freescale/imx8qm_mek/MAINTAINERS
Normal file
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@ -0,0 +1,6 @@
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i.MX8QM MEK BOARD
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M: Peng Fan <peng.fan@nxp.com>
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S: Maintained
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F: board/freescale/imx8qm_mek/
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F: include/configs/imx8qm_mek.h
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F: configs/imx8qm_mek_defconfig
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8
board/freescale/imx8qm_mek/Makefile
Normal file
8
board/freescale/imx8qm_mek/Makefile
Normal file
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@ -0,0 +1,8 @@
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#
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# Copyright 2018 NXP
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#
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# SPDX-License-Identifier: GPL-2.0+
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#
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obj-y += imx8qm_mek.o
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obj-$(CONFIG_SPL_BUILD) += spl.o
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57
board/freescale/imx8qm_mek/README
Normal file
57
board/freescale/imx8qm_mek/README
Normal file
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@ -0,0 +1,57 @@
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U-Boot for the NXP i.MX8QM EVK board
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Quick Start
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===========
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- Build the ARM Trusted firmware binary
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- Get scfw_tcm.bin and ahab-container.img
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- Build U-Boot
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- Flash the binary into the SD card
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- Boot
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Get and Build the ARM Trusted firmware
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======================================
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$ git clone https://source.codeaurora.org/external/imx/imx-atf
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$ cd imx-atf/
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$ git checkout origin/imx_4.14.78_1.0.0_ga -b imx_4.14.78_1.0.0_ga
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$ make PLAT=imx8qm bl31
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Get scfw_tcm.bin and ahab-container.img
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==============================
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$ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/imx-sc-firmware-1.1.bin
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$ chmod +x imx-sc-firmware-1.1.bin
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$ ./imx-sc-firmware-1.1.bin
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$ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/firmware-imx-8.0.bin
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$ chmod +x firmware-imx-8.0.bin
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$ ./firmware-imx-8.0.bin
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Copy the following binaries to U-Boot folder:
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$ cp imx-atf/build/imx8qm/release/bl31.bin .
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$ cp u-boot/u-boot.bin .
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Copy the following firmwares U-Boot folder :
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$ cp firmware-imx-7.6/firmware/seco/ahab-container.img .
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$ cp imx-sc-firmware-0.7/mx8qm-mek-scfw-tcm.bin .
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Build U-Boot
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============
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$ export ATF_LOAD_ADDR=0x80000000
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$ export BL33_LOAD_ADDR=0x80020000
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$ make imx8qm_mek_defconfig
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$ make flash.bin
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$ dd if=u-boot.itb of=flash.bin bs=512 seek=1984
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||||
Flash the binary into the SD card
|
||||
=================================
|
||||
|
||||
Burn the flash.bin binary to SD card offset 32KB:
|
||||
|
||||
$ sudo dd if=flash.bin of=/dev/sd[x] bs=1024 seek=32
|
||||
|
||||
Boot
|
||||
====
|
||||
Set Boot switch SW2: 1100.
|
||||
157
board/freescale/imx8qm_mek/imx8qm_mek.c
Normal file
157
board/freescale/imx8qm_mek/imx8qm_mek.c
Normal file
|
|
@ -0,0 +1,157 @@
|
|||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* Copyright 2018 NXP
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <errno.h>
|
||||
#include <linux/libfdt.h>
|
||||
#include <environment.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/gpio.h>
|
||||
#include <asm/arch/clock.h>
|
||||
#include <asm/arch/sci/sci.h>
|
||||
#include <asm/arch/imx8-pins.h>
|
||||
#include <asm/arch/iomux.h>
|
||||
#include <asm/arch/sys_proto.h>
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
#define UART_PAD_CTRL ((SC_PAD_CONFIG_OUT_IN << PADRING_CONFIG_SHIFT) | \
|
||||
(SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \
|
||||
(SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | \
|
||||
(SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT))
|
||||
|
||||
static iomux_cfg_t uart0_pads[] = {
|
||||
SC_P_UART0_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
|
||||
SC_P_UART0_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
|
||||
};
|
||||
|
||||
static void setup_iomux_uart(void)
|
||||
{
|
||||
imx8_iomux_setup_multiple_pads(uart0_pads, ARRAY_SIZE(uart0_pads));
|
||||
}
|
||||
|
||||
int board_early_init_f(void)
|
||||
{
|
||||
int ret;
|
||||
/* Set UART0 clock root to 80 MHz */
|
||||
sc_pm_clock_rate_t rate = 80000000;
|
||||
|
||||
/* Power up UART0 */
|
||||
ret = sc_pm_set_resource_power_mode(-1, SC_R_UART_0, SC_PM_PW_MODE_ON);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
ret = sc_pm_set_clock_rate(-1, SC_R_UART_0, 2, &rate);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
/* Enable UART0 clock root */
|
||||
ret = sc_pm_clock_enable(-1, SC_R_UART_0, 2, true, false);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
setup_iomux_uart();
|
||||
|
||||
sc_pm_set_resource_power_mode(-1, SC_R_GPIO_5, SC_PM_PW_MODE_ON);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
#if IS_ENABLED(CONFIG_DM_GPIO)
|
||||
static void board_gpio_init(void)
|
||||
{
|
||||
/* TODO */
|
||||
}
|
||||
#else
|
||||
static inline void board_gpio_init(void) {}
|
||||
#endif
|
||||
|
||||
#if IS_ENABLED(CONFIG_FEC_MXC)
|
||||
#include <miiphy.h>
|
||||
|
||||
int board_phy_config(struct phy_device *phydev)
|
||||
{
|
||||
phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x1f);
|
||||
phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x8);
|
||||
|
||||
phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x00);
|
||||
phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x82ee);
|
||||
phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05);
|
||||
phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100);
|
||||
|
||||
if (phydev->drv->config)
|
||||
phydev->drv->config(phydev);
|
||||
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
|
||||
void build_info(void)
|
||||
{
|
||||
u32 sc_build = 0, sc_commit = 0;
|
||||
|
||||
/* Get SCFW build and commit id */
|
||||
sc_misc_build_info(-1, &sc_build, &sc_commit);
|
||||
if (!sc_build) {
|
||||
printf("SCFW does not support build info\n");
|
||||
sc_commit = 0; /* Display 0 when the build info is not supported*/
|
||||
}
|
||||
printf("Build: SCFW %x\n", sc_commit);
|
||||
}
|
||||
|
||||
int checkboard(void)
|
||||
{
|
||||
puts("Board: iMX8QM MEK\n");
|
||||
|
||||
build_info();
|
||||
print_bootinfo();
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int board_init(void)
|
||||
{
|
||||
/* Power up base board */
|
||||
sc_pm_set_resource_power_mode(-1, SC_R_BOARD_R1, SC_PM_PW_MODE_ON);
|
||||
|
||||
board_gpio_init();
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
void detail_board_ddr_info(void)
|
||||
{
|
||||
puts("\nDDR ");
|
||||
}
|
||||
|
||||
/*
|
||||
* Board specific reset that is system reset.
|
||||
*/
|
||||
void reset_cpu(ulong addr)
|
||||
{
|
||||
/* TODO */
|
||||
}
|
||||
|
||||
#ifdef CONFIG_OF_BOARD_SETUP
|
||||
int ft_board_setup(void *blob, bd_t *bd)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
|
||||
int board_mmc_get_env_dev(int devno)
|
||||
{
|
||||
return devno;
|
||||
}
|
||||
|
||||
int board_late_init(void)
|
||||
{
|
||||
#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
|
||||
env_set("board_name", "MEK");
|
||||
env_set("board_rev", "iMX8QM");
|
||||
#endif
|
||||
|
||||
return 0;
|
||||
}
|
||||
19
board/freescale/imx8qm_mek/imximage.cfg
Normal file
19
board/freescale/imx8qm_mek/imximage.cfg
Normal file
|
|
@ -0,0 +1,19 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* Copyright 2018 NXP
|
||||
*/
|
||||
|
||||
#define __ASSEMBLY__
|
||||
|
||||
/* Boot from SD, sector size 0x400 */
|
||||
BOOT_FROM SD 0x400
|
||||
/* SoC type IMX8QM */
|
||||
SOC_TYPE IMX8QM
|
||||
/* Append seco container image */
|
||||
APPEND mx8qm-ahab-container.img
|
||||
/* Create the 2nd container */
|
||||
CONTAINER
|
||||
/* Add scfw image with exec attribute */
|
||||
IMAGE SCU mx8qm-mek-scfw-tcm.bin
|
||||
/* Add ATF image with exec attribute */
|
||||
IMAGE A35 spl/u-boot-spl.bin 0x00100000
|
||||
75
board/freescale/imx8qm_mek/spl.c
Normal file
75
board/freescale/imx8qm_mek/spl.c
Normal file
|
|
@ -0,0 +1,75 @@
|
|||
/*
|
||||
* Copyright 2018 NXP
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <dm.h>
|
||||
#include <spl.h>
|
||||
#include <dm/uclass.h>
|
||||
#include <dm/device.h>
|
||||
#include <dm/uclass-internal.h>
|
||||
#include <dm/device-internal.h>
|
||||
#include <dm/lists.h>
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
void spl_board_init(void)
|
||||
{
|
||||
struct udevice *dev;
|
||||
int offset;
|
||||
|
||||
uclass_find_first_device(UCLASS_MISC, &dev);
|
||||
|
||||
for (; dev; uclass_find_next_device(&dev)) {
|
||||
if (device_probe(dev))
|
||||
continue;
|
||||
}
|
||||
|
||||
offset = fdt_node_offset_by_compatible(gd->fdt_blob, -1, "nxp,imx8-pd");
|
||||
while (offset != -FDT_ERR_NOTFOUND) {
|
||||
lists_bind_fdt(gd->dm_root, offset_to_ofnode(offset),
|
||||
NULL, true);
|
||||
offset = fdt_node_offset_by_compatible(gd->fdt_blob, offset,
|
||||
"nxp,imx8-pd");
|
||||
}
|
||||
|
||||
uclass_find_first_device(UCLASS_POWER_DOMAIN, &dev);
|
||||
|
||||
for (; dev; uclass_find_next_device(&dev)) {
|
||||
if (device_probe(dev))
|
||||
continue;
|
||||
}
|
||||
|
||||
arch_cpu_init();
|
||||
|
||||
board_early_init_f();
|
||||
|
||||
timer_init();
|
||||
|
||||
preloader_console_init();
|
||||
|
||||
puts("Normal Boot\n");
|
||||
}
|
||||
|
||||
#ifdef CONFIG_SPL_LOAD_FIT
|
||||
int board_fit_config_name_match(const char *name)
|
||||
{
|
||||
/* Just empty function now - can't decide what to choose */
|
||||
debug("%s: %s\n", __func__, name);
|
||||
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
|
||||
void board_init_f(ulong dummy)
|
||||
{
|
||||
/* Clear global data */
|
||||
memset((void *)gd, 0, sizeof(gd_t));
|
||||
|
||||
/* Clear the BSS. */
|
||||
memset(__bss_start, 0, __bss_end - __bss_start);
|
||||
|
||||
board_init_r(NULL, 0);
|
||||
}
|
||||
75
configs/imx8qm_mek_defconfig
Normal file
75
configs/imx8qm_mek_defconfig
Normal file
|
|
@ -0,0 +1,75 @@
|
|||
CONFIG_ARM=y
|
||||
CONFIG_ARCH_IMX8=y
|
||||
CONFIG_SYS_TEXT_BASE=0x80020000
|
||||
CONFIG_SPL_GPIO_SUPPORT=y
|
||||
CONFIG_SPL_LIBCOMMON_SUPPORT=y
|
||||
CONFIG_SPL_LIBGENERIC_SUPPORT=y
|
||||
CONFIG_SYS_MALLOC_F_LEN=0x2000
|
||||
CONFIG_TARGET_IMX8QM_MEK=y
|
||||
CONFIG_SPL_MMC_SUPPORT=y
|
||||
CONFIG_SPL_SERIAL_SUPPORT=y
|
||||
CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
|
||||
CONFIG_SPL=y
|
||||
CONFIG_NR_DRAM_BANKS=3
|
||||
CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-imx/mkimage_fit_atf.sh"
|
||||
CONFIG_FIT=y
|
||||
CONFIG_SPL_LOAD_FIT=y
|
||||
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/imx8qm_mek/imximage.cfg"
|
||||
CONFIG_BOOTDELAY=3
|
||||
CONFIG_LOG=y
|
||||
CONFIG_SPL_BOARD_INIT=y
|
||||
CONFIG_SPL_SEPARATE_BSS=y
|
||||
CONFIG_SPL_POWER_SUPPORT=y
|
||||
CONFIG_SPL_POWER_DOMAIN=y
|
||||
CONFIG_SPL_WATCHDOG_SUPPORT=y
|
||||
CONFIG_CMD_CPU=y
|
||||
# CONFIG_CMD_IMPORTENV is not set
|
||||
CONFIG_CMD_CLK=y
|
||||
CONFIG_CMD_DM=y
|
||||
CONFIG_CMD_GPIO=y
|
||||
CONFIG_CMD_I2C=y
|
||||
CONFIG_CMD_MMC=y
|
||||
CONFIG_CMD_DHCP=y
|
||||
CONFIG_CMD_MII=y
|
||||
CONFIG_CMD_PING=y
|
||||
CONFIG_CMD_CACHE=y
|
||||
CONFIG_CMD_FAT=y
|
||||
CONFIG_SPL_OF_CONTROL=y
|
||||
CONFIG_DEFAULT_DEVICE_TREE="fsl-imx8qm-mek"
|
||||
CONFIG_ENV_IS_IN_MMC=y
|
||||
CONFIG_SPL_DM=y
|
||||
CONFIG_SPL_CLK=y
|
||||
CONFIG_CLK_IMX8=y
|
||||
CONFIG_CPU=y
|
||||
CONFIG_DM_GPIO=y
|
||||
CONFIG_MXC_GPIO=y
|
||||
CONFIG_DM_PCA953X=y
|
||||
CONFIG_DM_I2C=y
|
||||
CONFIG_SYS_I2C_IMX_LPI2C=y
|
||||
CONFIG_I2C_MUX=y
|
||||
CONFIG_I2C_MUX_PCA954x=y
|
||||
CONFIG_MISC=y
|
||||
CONFIG_DM_MMC=y
|
||||
CONFIG_PHYLIB=y
|
||||
CONFIG_PHY_ADDR_ENABLE=y
|
||||
CONFIG_PHY_ATHEROS=y
|
||||
CONFIG_DM_ETH=y
|
||||
CONFIG_PHY_GIGE=y
|
||||
CONFIG_FEC_MXC_SHARE_MDIO=y
|
||||
CONFIG_FEC_MXC_MDIO_BASE=0x5B040000
|
||||
CONFIG_FEC_MXC=y
|
||||
CONFIG_MII=y
|
||||
CONFIG_PINCTRL=y
|
||||
CONFIG_SPL_PINCTRL=y
|
||||
CONFIG_PINCTRL_IMX8=y
|
||||
CONFIG_POWER_DOMAIN=y
|
||||
CONFIG_IMX8_POWER_DOMAIN=y
|
||||
CONFIG_DM_REGULATOR=y
|
||||
CONFIG_SPL_DM_REGULATOR=y
|
||||
CONFIG_DM_REGULATOR_FIXED=y
|
||||
CONFIG_DM_REGULATOR_GPIO=y
|
||||
CONFIG_SPL_DM_REGULATOR_GPIO=y
|
||||
CONFIG_DM_SERIAL=y
|
||||
CONFIG_FSL_LPUART=y
|
||||
CONFIG_SPL_TINY_MEMSET=y
|
||||
# CONFIG_EFI_LOADER is not set
|
||||
176
include/configs/imx8qm_mek.h
Normal file
176
include/configs/imx8qm_mek.h
Normal file
|
|
@ -0,0 +1,176 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* Copyright 2018 NXP
|
||||
*/
|
||||
|
||||
#ifndef __IMX8QM_MEK_H
|
||||
#define __IMX8QM_MEK_H
|
||||
|
||||
#include <linux/sizes.h>
|
||||
#include <asm/arch/imx-regs.h>
|
||||
|
||||
#ifdef CONFIG_SPL_BUILD
|
||||
#define CONFIG_SPL_TEXT_BASE 0x0
|
||||
#define CONFIG_SPL_MAX_SIZE (124 * 1024)
|
||||
#define CONFIG_SYS_MONITOR_LEN (1024 * 1024)
|
||||
#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR
|
||||
#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x800
|
||||
#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 0
|
||||
|
||||
#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv8/u-boot-spl.lds"
|
||||
#define CONFIG_SPL_STACK 0x013E000
|
||||
#define CONFIG_SPL_BSS_START_ADDR 0x00128000
|
||||
#define CONFIG_SPL_BSS_MAX_SIZE 0x1000 /* 4 KB */
|
||||
#define CONFIG_SYS_SPL_MALLOC_START 0x00120000
|
||||
#define CONFIG_SYS_SPL_MALLOC_SIZE 0x3000 /* 12 KB */
|
||||
#define CONFIG_SERIAL_LPUART_BASE 0x5a060000
|
||||
#define CONFIG_SYS_ICACHE_OFF
|
||||
#define CONFIG_SYS_DCACHE_OFF
|
||||
#define CONFIG_MALLOC_F_ADDR 0x00120000
|
||||
|
||||
#define CONFIG_SPL_RAW_IMAGE_ARM_TRUSTED_FIRMWARE
|
||||
|
||||
#define CONFIG_SPL_ABORT_ON_RAW_IMAGE
|
||||
|
||||
#define CONFIG_OF_EMBED
|
||||
#endif
|
||||
|
||||
#define CONFIG_REMAKE_ELF
|
||||
|
||||
#define CONFIG_BOARD_EARLY_INIT_F
|
||||
|
||||
/* Flat Device Tree Definitions */
|
||||
#define CONFIG_OF_BOARD_SETUP
|
||||
|
||||
#undef CONFIG_CMD_EXPORTENV
|
||||
#undef CONFIG_CMD_IMPORTENV
|
||||
#undef CONFIG_CMD_IMLS
|
||||
|
||||
#undef CONFIG_CMD_CRC32
|
||||
#undef CONFIG_BOOTM_NETBSD
|
||||
|
||||
#define CONFIG_FSL_ESDHC
|
||||
#define CONFIG_FSL_USDHC
|
||||
#define CONFIG_SYS_FSL_ESDHC_ADDR 0
|
||||
#define USDHC1_BASE_ADDR 0x5B010000
|
||||
#define USDHC2_BASE_ADDR 0x5B020000
|
||||
#define CONFIG_SUPPORT_EMMC_BOOT /* eMMC specific */
|
||||
|
||||
#define CONFIG_ENV_OVERWRITE
|
||||
|
||||
#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
|
||||
|
||||
/* Initial environment variables */
|
||||
#define CONFIG_EXTRA_ENV_SETTINGS \
|
||||
"script=boot.scr\0" \
|
||||
"image=Image\0" \
|
||||
"panel=NULL\0" \
|
||||
"console=ttyLP0,${baudrate} earlycon=lpuart32,0x5a060000,${baudrate}\0" \
|
||||
"fdt_addr=0x83000000\0" \
|
||||
"fdt_high=0xffffffffffffffff\0" \
|
||||
"boot_fdt=try\0" \
|
||||
"fdt_file=fsl-imx8qxp-mek.dtb\0" \
|
||||
"initrd_addr=0x83800000\0" \
|
||||
"initrd_high=0xffffffffffffffff\0" \
|
||||
"mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \
|
||||
"mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \
|
||||
"mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \
|
||||
"mmcautodetect=yes\0" \
|
||||
"mmcargs=setenv bootargs console=${console} root=${mmcroot}\0 " \
|
||||
"loadbootscript=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
|
||||
"bootscript=echo Running bootscript from mmc ...; " \
|
||||
"source\0" \
|
||||
"loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
|
||||
"loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
|
||||
"mmcboot=echo Booting from mmc ...; " \
|
||||
"run mmcargs; " \
|
||||
"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
|
||||
"if run loadfdt; then " \
|
||||
"booti ${loadaddr} - ${fdt_addr}; " \
|
||||
"else " \
|
||||
"echo WARN: Cannot load the DT; " \
|
||||
"fi; " \
|
||||
"else " \
|
||||
"echo wait for boot; " \
|
||||
"fi;\0" \
|
||||
"netargs=setenv bootargs console=${console} " \
|
||||
"root=/dev/nfs " \
|
||||
"ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
|
||||
"netboot=echo Booting from net ...; " \
|
||||
"run netargs; " \
|
||||
"if test ${ip_dyn} = yes; then " \
|
||||
"setenv get_cmd dhcp; " \
|
||||
"else " \
|
||||
"setenv get_cmd tftp; " \
|
||||
"fi; " \
|
||||
"${get_cmd} ${loadaddr} ${image}; " \
|
||||
"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
|
||||
"if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \
|
||||
"booti ${loadaddr} - ${fdt_addr}; " \
|
||||
"else " \
|
||||
"echo WARN: Cannot load the DT; " \
|
||||
"fi; " \
|
||||
"else " \
|
||||
"booti; " \
|
||||
"fi;\0"
|
||||
|
||||
#define CONFIG_BOOTCOMMAND \
|
||||
"mmc dev ${mmcdev}; if mmc rescan; then " \
|
||||
"if run loadbootscript; then " \
|
||||
"run bootscript; " \
|
||||
"else " \
|
||||
"if run loadimage; then " \
|
||||
"run mmcboot; " \
|
||||
"else run netboot; " \
|
||||
"fi; " \
|
||||
"fi; " \
|
||||
"else booti ${loadaddr} - ${fdt_addr}; fi"
|
||||
|
||||
/* Link Definitions */
|
||||
#define CONFIG_LOADADDR 0x80280000
|
||||
|
||||
#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
|
||||
|
||||
#define CONFIG_SYS_INIT_SP_ADDR 0x80200000
|
||||
|
||||
/* Default environment is in SD */
|
||||
#define CONFIG_ENV_SIZE 0x1000
|
||||
#define CONFIG_ENV_OFFSET (64 * SZ_64K)
|
||||
#define CONFIG_SYS_MMC_ENV_PART 0 /* user area */
|
||||
|
||||
#define CONFIG_SYS_MMC_IMG_LOAD_PART 1
|
||||
|
||||
/* On LPDDR4 board, USDHC1 is for eMMC, USDHC2 is for SD on CPU board */
|
||||
#define CONFIG_SYS_MMC_ENV_DEV 1 /* USDHC2 */
|
||||
#define CONFIG_MMCROOT "/dev/mmcblk1p2" /* USDHC2 */
|
||||
#define CONFIG_SYS_FSL_USDHC_NUM 2
|
||||
|
||||
/* Size of malloc() pool */
|
||||
#define CONFIG_SYS_MALLOC_LEN ((CONFIG_ENV_SIZE + (32 * 1024)) * 1024)
|
||||
|
||||
#define CONFIG_SYS_SDRAM_BASE 0x80000000
|
||||
#define PHYS_SDRAM_1 0x80000000
|
||||
#define PHYS_SDRAM_2 0x880000000
|
||||
#define PHYS_SDRAM_1_SIZE 0x80000000 /* 2 GB */
|
||||
#define PHYS_SDRAM_2_SIZE 0x100000000 /* 4 GB */
|
||||
|
||||
/* Serial */
|
||||
#define CONFIG_BAUDRATE 115200
|
||||
|
||||
/* Monitor Command Prompt */
|
||||
#define CONFIG_HUSH_PARSER
|
||||
#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
|
||||
#define CONFIG_SYS_CBSIZE 2048
|
||||
#define CONFIG_SYS_MAXARGS 64
|
||||
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
|
||||
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
|
||||
sizeof(CONFIG_SYS_PROMPT) + 16)
|
||||
|
||||
/* Generic Timer Definitions */
|
||||
#define COUNTER_FREQUENCY 8000000 /* 8MHz */
|
||||
|
||||
/* Networking */
|
||||
#define CONFIG_FEC_XCV_TYPE RGMII
|
||||
#define FEC_QUIRK_ENET_MAC
|
||||
|
||||
#endif /* __IMX8QM_MEK_H */
|
||||
Loading…
Reference in New Issue
Block a user