brain-hackers_pepepper-mirror/u-boot-brain
1
0
Fork 0
mirror of https://github.com/brain-hackers/u-boot-brain synced 2024-09-29 08:00:26 +09:00
Code Issues Projects Releases Wiki Activity

arm: davinci: remove dead code for PHYs used by DaVinci DM* boards

Browse Source 
The support for DaVinci DM* boards has been dropped a while ago. The
code for all those PHYs is no longer used and they have their own
proper PHY drivers in drivers/net/phy anyway. Remove all dead code.

Signed-off-by: Bartosz Golaszewski <bgolaszewski@baylibre.com>
This commit is contained in:
Bartosz Golaszewski 2019-04-29 18:37:09 +02:00 committed by Tom Rini
parent 50e3b4c7aa
commit 0c56542592
6 changed files with 0 additions and 354 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
arch/arm/mach-davinci/Makefile
View File

@ -12,7 +12,6 @@ obj-$(CONFIG_SOC_DM365) += dm365.o
obj-$(CONFIG_SOC_DM644X) += dm644x.o
obj-$(CONFIG_SOC_DM646X) += dm646x.o
obj-$(CONFIG_SOC_DA850) += da850_pinmux.o
obj-$(CONFIG_DRIVER_TI_EMAC) += lxt972.o dp83848.o et1011c.o ksz8873.o
ifdef CONFIG_SPL_BUILD
obj-$(CONFIG_SPL_FRAMEWORK) += spl.o

127
arch/arm/mach-davinci/dp83848.c
View File

@ -1,127 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* National Semiconductor DP83848 PHY Driver for TI DaVinci
* (TMS320DM644x) based boards.
*
* Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
*
* --------------------------------------------------------
*/
#include <common.h>
#include <net.h>
#include <dp83848.h>
#include <asm/arch/emac_defs.h>
#include "../../../drivers/net/ti/davinci_emac.h"
#ifdef CONFIG_DRIVER_TI_EMAC
#ifdef CONFIG_CMD_NET
int dp83848_is_phy_connected(int phy_addr)
{
u_int16_t id1, id2;
if (!davinci_eth_phy_read(phy_addr, DP83848_PHYID1_REG, &id1))
return(0);
if (!davinci_eth_phy_read(phy_addr, DP83848_PHYID2_REG, &id2))
return(0);
if ((id1 == DP83848_PHYID1_OUI) && (id2 == DP83848_PHYID2_OUI))
return(1);
return(0);
}
int dp83848_get_link_speed(int phy_addr)
{
u_int16_t tmp;
volatile emac_regs* emac = (emac_regs *)EMAC_BASE_ADDR;
if (!davinci_eth_phy_read(phy_addr, DP83848_STAT_REG, &tmp))
return(0);
if (!(tmp & DP83848_LINK_STATUS)) /* link up? */
return(0);
if (!davinci_eth_phy_read(phy_addr, DP83848_PHY_STAT_REG, &tmp))
return(0);
/* Speed doesn't matter, there is no setting for it in EMAC... */
if (tmp & DP83848_DUPLEX) {
/* set DM644x EMAC for Full Duplex */
emac->MACCONTROL = EMAC_MACCONTROL_MIIEN_ENABLE |
EMAC_MACCONTROL_FULLDUPLEX_ENABLE;
} else {
/*set DM644x EMAC for Half Duplex */
emac->MACCONTROL = EMAC_MACCONTROL_MIIEN_ENABLE;
}
return(1);
}
int dp83848_init_phy(int phy_addr)
{
int ret = 1;
if (!dp83848_get_link_speed(phy_addr)) {
/* Try another time */
udelay(100000);
ret = dp83848_get_link_speed(phy_addr);
}
/* Disable PHY Interrupts */
davinci_eth_phy_write(phy_addr, DP83848_PHY_INTR_CTRL_REG, 0);
return(ret);
}
int dp83848_auto_negotiate(int phy_addr)
{
u_int16_t tmp;
if (!davinci_eth_phy_read(phy_addr, DP83848_CTL_REG, &tmp))
return(0);
/* Restart Auto_negotiation */
tmp &= ~DP83848_AUTONEG; /* remove autonegotiation enable */
tmp |= DP83848_ISOLATE; /* Electrically isolate PHY */
davinci_eth_phy_write(phy_addr, DP83848_CTL_REG, tmp);
/* Set the Auto_negotiation Advertisement Register
* MII advertising for Next page, 100BaseTxFD and HD,
* 10BaseTFD and HD, IEEE 802.3
*/
tmp = DP83848_NP | DP83848_TX_FDX | DP83848_TX_HDX |
DP83848_10_FDX | DP83848_10_HDX | DP83848_AN_IEEE_802_3;
davinci_eth_phy_write(phy_addr, DP83848_ANA_REG, tmp);
/* Read Control Register */
if (!davinci_eth_phy_read(phy_addr, DP83848_CTL_REG, &tmp))
return(0);
tmp |= DP83848_SPEED_SELECT | DP83848_AUTONEG | DP83848_DUPLEX_MODE;
davinci_eth_phy_write(phy_addr, DP83848_CTL_REG, tmp);
/* Restart Auto_negotiation */
tmp |= DP83848_RESTART_AUTONEG;
davinci_eth_phy_write(phy_addr, DP83848_CTL_REG, tmp);
/*check AutoNegotiate complete */
udelay(10000);
if (!davinci_eth_phy_read(phy_addr, DP83848_STAT_REG, &tmp))
return(0);
if (!(tmp & DP83848_AUTONEG_COMP))
return(0);
return (dp83848_get_link_speed(phy_addr));
}
#endif /* CONFIG_CMD_NET */
#endif /* CONFIG_DRIVER_ETHER */

41
arch/arm/mach-davinci/et1011c.c
View File

@ -1,41 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* LSI ET1011C PHY Driver for TI DaVinci(TMS320DM6467) board.
*
* Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
*/
#include <common.h>
#include <net.h>
#include <miiphy.h>
#include <asm/arch/emac_defs.h>
#include "../../../drivers/net/ti/davinci_emac.h"
#ifdef CONFIG_DRIVER_TI_EMAC
#ifdef CONFIG_CMD_NET
/* LSI PHYSICAL LAYER TRANSCEIVER ET1011C */
#define MII_PHY_CONFIG_REG 22
/* PHY Config bits */
#define PHY_SYS_CLK_EN (1 << 4)
int et1011c_get_link_speed(int phy_addr)
{
u_int16_t data;
if (davinci_eth_phy_read(phy_addr, MII_STATUS_REG, &data) && (data & 0x04)) {
davinci_eth_phy_read(phy_addr, MII_PHY_CONFIG_REG, &data);
/* Enable 125MHz clock sourced from PHY */
davinci_eth_phy_write(phy_addr, MII_PHY_CONFIG_REG,
data | PHY_SYS_CLK_EN);
return (1);
}
return (0);
}
#endif /* CONFIG_CMD_NET */
#endif /* CONFIG_DRIVER_ETHER */

21
arch/arm/mach-davinci/include/mach/emac_defs.h
View File

@ -69,25 +69,4 @@
#define EMAC_MDIO_CLOCK_FREQ 2000000 /* 2.0 MHz */
#endif
#define PHY_KSZ8873 (0x00221450)
int ksz8873_is_phy_connected(int phy_addr);
int ksz8873_get_link_speed(int phy_addr);
int ksz8873_init_phy(int phy_addr);
int ksz8873_auto_negotiate(int phy_addr);
#define PHY_LXT972 (0x001378e2)
int lxt972_is_phy_connected(int phy_addr);
int lxt972_get_link_speed(int phy_addr);
int lxt972_init_phy(int phy_addr);
int lxt972_auto_negotiate(int phy_addr);
#define PHY_DP83848 (0x20005c90)
int dp83848_is_phy_connected(int phy_addr);
int dp83848_get_link_speed(int phy_addr);
int dp83848_init_phy(int phy_addr);
int dp83848_auto_negotiate(int phy_addr);
#define PHY_ET1011C (0x282f013)
int et1011c_get_link_speed(int phy_addr);
#endif /* _DM644X_EMAC_H_ */

52
arch/arm/mach-davinci/ksz8873.c
View File

@ -1,52 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Micrel KSZ8873 PHY Driver for TI DaVinci
* (TMS320DM644x) based boards.
*
* Copyright (C) 2011 Heiko Schocher <hsdenx.de>
*
* based on:
* National Semiconductor DP83848 PHY Driver for TI DaVinci
* (TMS320DM644x) based boards.
*
* Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
*
* --------------------------------------------------------
*/
#include <common.h>
#include <miiphy.h>
#include <net.h>
#include <asm/arch/emac_defs.h>
#include <asm/io.h>
#include "../../../drivers/net/ti/davinci_emac.h"
int ksz8873_is_phy_connected(int phy_addr)
{
u_int16_t dummy;
return davinci_eth_phy_read(phy_addr, MII_PHYSID1, &dummy);
}
int ksz8873_get_link_speed(int phy_addr)
{
emac_regs *emac = (emac_regs *)EMAC_BASE_ADDR;
/* we always have a link to the switch, 100 FD */
writel((EMAC_MACCONTROL_MIIEN_ENABLE |
EMAC_MACCONTROL_FULLDUPLEX_ENABLE),
&emac->MACCONTROL);
return 1;
}
int ksz8873_init_phy(int phy_addr)
{
return 1;
}
int ksz8873_auto_negotiate(int phy_addr)
{
return dp83848_get_link_speed(phy_addr);
}

112
arch/arm/mach-davinci/lxt972.c
View File

@ -1,112 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Intel LXT971/LXT972 PHY Driver for TI DaVinci
* (TMS320DM644x) based boards.
*
* Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
*
* --------------------------------------------------------
*/
#include <common.h>
#include <net.h>
#include <miiphy.h>
#include <lxt971a.h>
#include <asm/arch/emac_defs.h>
#include "../../../drivers/net/ti/davinci_emac.h"
#ifdef CONFIG_DRIVER_TI_EMAC
#ifdef CONFIG_CMD_NET
int lxt972_is_phy_connected(int phy_addr)
{
u_int16_t id1, id2;
if (!davinci_eth_phy_read(phy_addr, MII_PHYSID1, &id1))
return(0);
if (!davinci_eth_phy_read(phy_addr, MII_PHYSID2, &id2))
return(0);
if ((id1 == (0x0013)) && ((id2 & 0xfff0) == 0x78e0))
return(1);
return(0);
}
int lxt972_get_link_speed(int phy_addr)
{
u_int16_t stat1, tmp;
volatile emac_regs *emac = (emac_regs *)EMAC_BASE_ADDR;
if (!davinci_eth_phy_read(phy_addr, PHY_LXT971_STAT2, &stat1))
return(0);
if (!(stat1 & PHY_LXT971_STAT2_LINK)) /* link up? */
return(0);
if (!davinci_eth_phy_read(phy_addr, PHY_LXT971_DIG_CFG, &tmp))
return(0);
tmp |= PHY_LXT971_DIG_CFG_MII_DRIVE;
davinci_eth_phy_write(phy_addr, PHY_LXT971_DIG_CFG, tmp);
/* Read back */
if (!davinci_eth_phy_read(phy_addr, PHY_LXT971_DIG_CFG, &tmp))
return(0);
/* Speed doesn't matter, there is no setting for it in EMAC... */
if (stat1 & PHY_LXT971_STAT2_DUPLEX_MODE) {
/* set DM644x EMAC for Full Duplex */
emac->MACCONTROL = EMAC_MACCONTROL_MIIEN_ENABLE |
EMAC_MACCONTROL_FULLDUPLEX_ENABLE;
} else {
/*set DM644x EMAC for Half Duplex */
emac->MACCONTROL = EMAC_MACCONTROL_MIIEN_ENABLE;
}
return(1);
}
int lxt972_init_phy(int phy_addr)
{
int ret = 1;
if (!lxt972_get_link_speed(phy_addr)) {
/* Try another time */
ret = lxt972_get_link_speed(phy_addr);
}
/* Disable PHY Interrupts */
davinci_eth_phy_write(phy_addr, PHY_LXT971_INT_ENABLE, 0);
return(ret);
}
int lxt972_auto_negotiate(int phy_addr)
{
u_int16_t tmp;
if (!davinci_eth_phy_read(phy_addr, MII_BMCR, &tmp))
return(0);
/* Restart Auto_negotiation */
tmp |= BMCR_ANRESTART;
davinci_eth_phy_write(phy_addr, MII_BMCR, tmp);
/*check AutoNegotiate complete */
udelay (10000);
if (!davinci_eth_phy_read(phy_addr, MII_BMSR, &tmp))
return(0);
if (!(tmp & BMSR_ANEGCOMPLETE))
return(0);
return (lxt972_get_link_speed(phy_addr));
}
#endif /* CONFIG_CMD_NET */
#endif /* CONFIG_DRIVER_ETHER */