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ARMV7: OMAP3: Apply Cortex-A8 errata workarounds only on affected revisions
The workarounds for errata 621766 and 725233 should only be applied on affected Cortex-A8 revisions. Recent chips use r3px cores where these have been fixed. Signed-off-by: Mans Rullgard <mans@mansr.com> Signed-off-by: Steve Sakoman <steve@sakoman.com> Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
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@ -163,15 +163,22 @@ l2_cache_disable:
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* general use.
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* general use.
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*****************************************************************************/
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*****************************************************************************/
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setup_auxcr:
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setup_auxcr:
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mrc p15, 0, r0, c0, c0, 0 @ read main ID register
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and r2, r0, #0x00f00000 @ variant
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and r3, r0, #0x0000000f @ revision
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orr r1, r3, r2, lsr #20-4 @ combine variant and revision
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mov r12, #0x3
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mov r12, #0x3
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mrc p15, 0, r0, c1, c0, 1
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mrc p15, 0, r0, c1, c0, 1
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orr r0, r0, #0x10 @ Enable ASA
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orr r0, r0, #0x10 @ Enable ASA
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orr r0, r0, #1 << 5 @ Enable L1NEON
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@ Enable L1NEON on pre-r2p1 (erratum 621766 workaround)
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cmp r1, #0x21
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orrlt r0, r0, #1 << 5
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.word 0xE1600070 @ SMC
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.word 0xE1600070 @ SMC
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mov r12, #0x2
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mov r12, #0x2
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mrc p15, 1, r0, c9, c0, 2
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mrc p15, 1, r0, c9, c0, 2
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@ Set PLD_FWD bit in L2AUXCR (Cortex-A8 erratum 725233 workaround)
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@ Set PLD_FWD bit in L2AUXCR on pre-r2p1 (erratum 725233 workaround)
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orr r0, r0, #1 << 27
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cmp r1, #0x21
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orrlt r0, r0, #1 << 27
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.word 0xE1600070 @ SMC
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.word 0xE1600070 @ SMC
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bx lr
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bx lr
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