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ARMV7: OMAP3: Apply Cortex-A8 errata workarounds only on affected revisions

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The workarounds for errata 621766 and 725233 should only be applied
on affected Cortex-A8 revisions.  Recent chips use r3px cores where
these have been fixed.

Signed-off-by: Mans Rullgard <mans@mansr.com>
Signed-off-by: Steve Sakoman <steve@sakoman.com>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
This commit is contained in:
Mans Rullgard 2010-04-14 16:10:28 +01:00 committed by Sandeep Paulraj
parent 096ca838b5
commit 0c0a0e0781
1 changed files with 10 additions and 3 deletions
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13
arch/arm/cpu/armv7/omap3/cache.S
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@ -163,15 +163,22 @@ l2_cache_disable:
* general use.
*****************************************************************************/
setup_auxcr:
mrc p15, 0, r0, c0, c0, 0 @ read main ID register
and r2, r0, #0x00f00000 @ variant
and r3, r0, #0x0000000f @ revision
orr r1, r3, r2, lsr #20-4 @ combine variant and revision
mov r12, #0x3
mrc p15, 0, r0, c1, c0, 1
orr r0, r0, #0x10 @ Enable ASA
orr r0, r0, #1 << 5 @ Enable L1NEON
@ Enable L1NEON on pre-r2p1 (erratum 621766 workaround)
cmp r1, #0x21
orrlt r0, r0, #1 << 5
.word 0xE1600070 @ SMC
mov r12, #0x2
mrc p15, 1, r0, c9, c0, 2
@ Set PLD_FWD bit in L2AUXCR (Cortex-A8 erratum 725233 workaround)
orr r0, r0, #1 << 27
@ Set PLD_FWD bit in L2AUXCR on pre-r2p1 (erratum 725233 workaround)
cmp r1, #0x21
orrlt r0, r0, #1 << 27
.word 0xE1600070 @ SMC
bx lr