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arm: at91: mpddr: allow multiple DDR controllers
The mpddr.c depends on ATMEL_BASE_MPDDRC for the base address to configure the controller. This cannot be used when there is more than one controller (i.e. AT91SAM9G45, AT91SAM9M10). Signed-off-by: Erik van Luijk <evanluijk@interact.nl> [remove 'new blank line at EOF'] Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
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@ -23,7 +23,9 @@ struct atmel_mpddr {
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u32 md;
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u32 md;
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};
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};
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int ddr2_init(const unsigned int ram_address,
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int ddr2_init(const unsigned int base,
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const unsigned int ram_address,
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const struct atmel_mpddr *mpddr);
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const struct atmel_mpddr *mpddr);
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/* Bit field in mode register */
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/* Bit field in mode register */
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@ -9,10 +9,10 @@
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#include <asm/io.h>
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#include <asm/io.h>
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#include <asm/arch/atmel_mpddrc.h>
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#include <asm/arch/atmel_mpddrc.h>
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static inline void atmel_mpddr_op(int mode, u32 ram_address)
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static inline void atmel_mpddr_op(const struct atmel_mpddr *mpddr,
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int mode,
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u32 ram_address)
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{
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{
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struct atmel_mpddr *mpddr = (struct atmel_mpddr *)ATMEL_BASE_MPDDRC;
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writel(mode, &mpddr->mr);
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writel(mode, &mpddr->mr);
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writel(0, ram_address);
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writel(0, ram_address);
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}
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}
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@ -27,10 +27,13 @@ static int ddr2_decodtype_is_seq(u32 cr)
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return 1;
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return 1;
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}
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}
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int ddr2_init(const unsigned int ram_address,
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int ddr2_init(const unsigned int base,
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const unsigned int ram_address,
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const struct atmel_mpddr *mpddr_value)
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const struct atmel_mpddr *mpddr_value)
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{
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{
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struct atmel_mpddr *mpddr = (struct atmel_mpddr *)ATMEL_BASE_MPDDRC;
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const struct atmel_mpddr *mpddr = (struct atmel_mpddr *)base;
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u32 ba_off, cr;
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u32 ba_off, cr;
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/* Compute bank offset according to NC in configuration register */
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/* Compute bank offset according to NC in configuration register */
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@ -52,30 +55,30 @@ int ddr2_init(const unsigned int ram_address,
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writel(mpddr_value->tpr2, &mpddr->tpr2);
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writel(mpddr_value->tpr2, &mpddr->tpr2);
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/* Issue a NOP command */
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/* Issue a NOP command */
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atmel_mpddr_op(ATMEL_MPDDRC_MR_MODE_NOP_CMD, ram_address);
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atmel_mpddr_op(mpddr, ATMEL_MPDDRC_MR_MODE_NOP_CMD, ram_address);
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/* A 200 us is provided to precede any signal toggle */
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/* A 200 us is provided to precede any signal toggle */
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udelay(200);
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udelay(200);
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/* Issue a NOP command */
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/* Issue a NOP command */
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atmel_mpddr_op(ATMEL_MPDDRC_MR_MODE_NOP_CMD, ram_address);
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atmel_mpddr_op(mpddr, ATMEL_MPDDRC_MR_MODE_NOP_CMD, ram_address);
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/* Issue an all banks precharge command */
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/* Issue an all banks precharge command */
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atmel_mpddr_op(ATMEL_MPDDRC_MR_MODE_PRCGALL_CMD, ram_address);
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atmel_mpddr_op(mpddr, ATMEL_MPDDRC_MR_MODE_PRCGALL_CMD, ram_address);
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/* Issue an extended mode register set(EMRS2) to choose operation */
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/* Issue an extended mode register set(EMRS2) to choose operation */
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atmel_mpddr_op(ATMEL_MPDDRC_MR_MODE_EXT_LMR_CMD,
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atmel_mpddr_op(mpddr, ATMEL_MPDDRC_MR_MODE_EXT_LMR_CMD,
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ram_address + (0x2 << ba_off));
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ram_address + (0x2 << ba_off));
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/* Issue an extended mode register set(EMRS3) to set EMSR to 0 */
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/* Issue an extended mode register set(EMRS3) to set EMSR to 0 */
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atmel_mpddr_op(ATMEL_MPDDRC_MR_MODE_EXT_LMR_CMD,
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atmel_mpddr_op(mpddr, ATMEL_MPDDRC_MR_MODE_EXT_LMR_CMD,
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ram_address + (0x3 << ba_off));
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ram_address + (0x3 << ba_off));
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/*
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/*
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* Issue an extended mode register set(EMRS1) to enable DLL and
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* Issue an extended mode register set(EMRS1) to enable DLL and
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* program D.I.C (output driver impedance control)
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* program D.I.C (output driver impedance control)
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*/
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*/
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atmel_mpddr_op(ATMEL_MPDDRC_MR_MODE_EXT_LMR_CMD,
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atmel_mpddr_op(mpddr, ATMEL_MPDDRC_MR_MODE_EXT_LMR_CMD,
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ram_address + (0x1 << ba_off));
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ram_address + (0x1 << ba_off));
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/* Enable DLL reset */
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/* Enable DLL reset */
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@ -83,21 +86,21 @@ int ddr2_init(const unsigned int ram_address,
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writel(cr | ATMEL_MPDDRC_CR_DLL_RESET_ENABLED, &mpddr->cr);
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writel(cr | ATMEL_MPDDRC_CR_DLL_RESET_ENABLED, &mpddr->cr);
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/* A mode register set(MRS) cycle is issued to reset DLL */
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/* A mode register set(MRS) cycle is issued to reset DLL */
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atmel_mpddr_op(ATMEL_MPDDRC_MR_MODE_LMR_CMD, ram_address);
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atmel_mpddr_op(mpddr, ATMEL_MPDDRC_MR_MODE_LMR_CMD, ram_address);
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/* Issue an all banks precharge command */
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/* Issue an all banks precharge command */
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atmel_mpddr_op(ATMEL_MPDDRC_MR_MODE_PRCGALL_CMD, ram_address);
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atmel_mpddr_op(mpddr, ATMEL_MPDDRC_MR_MODE_PRCGALL_CMD, ram_address);
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/* Two auto-refresh (CBR) cycles are provided */
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/* Two auto-refresh (CBR) cycles are provided */
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atmel_mpddr_op(ATMEL_MPDDRC_MR_MODE_RFSH_CMD, ram_address);
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atmel_mpddr_op(mpddr, ATMEL_MPDDRC_MR_MODE_RFSH_CMD, ram_address);
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atmel_mpddr_op(ATMEL_MPDDRC_MR_MODE_RFSH_CMD, ram_address);
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atmel_mpddr_op(mpddr, ATMEL_MPDDRC_MR_MODE_RFSH_CMD, ram_address);
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/* Disable DLL reset */
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/* Disable DLL reset */
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cr = readl(&mpddr->cr);
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cr = readl(&mpddr->cr);
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writel(cr & (~ATMEL_MPDDRC_CR_DLL_RESET_ENABLED), &mpddr->cr);
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writel(cr & (~ATMEL_MPDDRC_CR_DLL_RESET_ENABLED), &mpddr->cr);
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/* A mode register set (MRS) cycle is issued to disable DLL reset */
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/* A mode register set (MRS) cycle is issued to disable DLL reset */
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atmel_mpddr_op(ATMEL_MPDDRC_MR_MODE_LMR_CMD, ram_address);
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atmel_mpddr_op(mpddr, ATMEL_MPDDRC_MR_MODE_LMR_CMD, ram_address);
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/* Set OCD calibration in default state */
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/* Set OCD calibration in default state */
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cr = readl(&mpddr->cr);
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cr = readl(&mpddr->cr);
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@ -107,7 +110,7 @@ int ddr2_init(const unsigned int ram_address,
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* An extended mode register set (EMRS1) cycle is issued
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* An extended mode register set (EMRS1) cycle is issued
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* to OCD default value
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* to OCD default value
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*/
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*/
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atmel_mpddr_op(ATMEL_MPDDRC_MR_MODE_EXT_LMR_CMD,
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atmel_mpddr_op(mpddr, ATMEL_MPDDRC_MR_MODE_EXT_LMR_CMD,
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ram_address + (0x1 << ba_off));
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ram_address + (0x1 << ba_off));
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/* OCD calibration mode exit */
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/* OCD calibration mode exit */
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@ -118,11 +121,11 @@ int ddr2_init(const unsigned int ram_address,
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* An extended mode register set (EMRS1) cycle is issued
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* An extended mode register set (EMRS1) cycle is issued
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* to enable OCD exit
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* to enable OCD exit
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*/
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*/
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atmel_mpddr_op(ATMEL_MPDDRC_MR_MODE_EXT_LMR_CMD,
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atmel_mpddr_op(mpddr, ATMEL_MPDDRC_MR_MODE_EXT_LMR_CMD,
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ram_address + (0x1 << ba_off));
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ram_address + (0x1 << ba_off));
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/* A nornal mode command is provided */
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/* A nornal mode command is provided */
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atmel_mpddr_op(ATMEL_MPDDRC_MR_MODE_NORMAL_CMD, ram_address);
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atmel_mpddr_op(mpddr, ATMEL_MPDDRC_MR_MODE_NORMAL_CMD, ram_address);
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/* Perform a write access to any DDR2-SDRAM address */
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/* Perform a write access to any DDR2-SDRAM address */
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writel(0, ram_address);
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writel(0, ram_address);
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@ -147,7 +147,7 @@ void mem_init(void)
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writel(csa, &mat->ebicsa);
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writel(csa, &mat->ebicsa);
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/* DDRAM2 Controller initialize */
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/* DDRAM2 Controller initialize */
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ddr2_init(ATMEL_BASE_CS6, &ddr2);
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ddr2_init(ATMEL_BASE_DDRSDRC0, ATMEL_BASE_CS6, &ddr2);
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}
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}
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#endif
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#endif
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@ -327,6 +327,6 @@ void mem_init(void)
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writel(csa, &matrix->ebicsa);
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writel(csa, &matrix->ebicsa);
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/* DDRAM2 Controller initialize */
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/* DDRAM2 Controller initialize */
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ddr2_init(ATMEL_BASE_CS1, &ddr2);
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ddr2_init(ATMEL_BASE_DDRSDRC, ATMEL_BASE_CS1, &ddr2);
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}
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}
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#endif
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#endif
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@ -364,6 +364,6 @@ void mem_init(void)
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writel(csa, &matrix->ebicsa);
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writel(csa, &matrix->ebicsa);
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/* DDRAM2 Controller initialize */
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/* DDRAM2 Controller initialize */
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ddr2_init(ATMEL_BASE_CS1, &ddr2);
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ddr2_init(ATMEL_BASE_DDRSDRC, ATMEL_BASE_CS1, &ddr2);
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}
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}
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#endif
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#endif
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@ -194,7 +194,7 @@ void mem_init(void)
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writel(0x4, &pmc->scer);
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writel(0x4, &pmc->scer);
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/* DDRAM2 Controller initialize */
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/* DDRAM2 Controller initialize */
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ddr2_init(ATMEL_BASE_DDRCS, &ddr2);
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ddr2_init(ATMEL_BASE_MPDDRC, ATMEL_BASE_DDRCS, &ddr2);
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}
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}
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void at91_pmc_init(void)
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void at91_pmc_init(void)
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@ -433,7 +433,7 @@ void mem_init(void)
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writel(0x4, &pmc->scer);
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writel(0x4, &pmc->scer);
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/* DDRAM2 Controller initialize */
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/* DDRAM2 Controller initialize */
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ddr2_init(ATMEL_BASE_DDRCS, &ddr2);
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ddr2_init(ATMEL_BASE_MPDDRC, ATMEL_BASE_DDRCS, &ddr2);
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}
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}
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void at91_pmc_init(void)
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void at91_pmc_init(void)
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@ -393,7 +393,7 @@ void mem_init(void)
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writel(0x4, &pmc->scer);
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writel(0x4, &pmc->scer);
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/* DDRAM2 Controller initialize */
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/* DDRAM2 Controller initialize */
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ddr2_init(ATMEL_BASE_DDRCS, &ddr2);
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ddr2_init(ATMEL_BASE_MPDDRC, ATMEL_BASE_DDRCS, &ddr2);
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}
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}
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void at91_pmc_init(void)
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void at91_pmc_init(void)
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@ -389,7 +389,7 @@ void mem_init(void)
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writel(0x4, &pmc->scer);
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writel(0x4, &pmc->scer);
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/* DDRAM2 Controller initialize */
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/* DDRAM2 Controller initialize */
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ddr2_init(ATMEL_BASE_DDRCS, &ddr2);
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ddr2_init(ATMEL_BASE_MPDDRC, ATMEL_BASE_DDRCS, &ddr2);
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}
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}
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void at91_pmc_init(void)
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void at91_pmc_init(void)
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@ -160,7 +160,7 @@ void mem_init(void)
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writel(csa, &mat->ebicsa);
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writel(csa, &mat->ebicsa);
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/* DDRAM2 Controller initialize */
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/* DDRAM2 Controller initialize */
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ddr2_init(ATMEL_BASE_CS6, &ddr2);
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ddr2_init(ATMEL_BASE_DDRSDRC0, ATMEL_BASE_CS6, &ddr2);
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}
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}
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#endif
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#endif
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@ -251,5 +251,4 @@
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#define CONFIG_SYS_MCKR 0x1301
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#define CONFIG_SYS_MCKR 0x1301
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#define CONFIG_SYS_MCKR_CSS 0x1302
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#define CONFIG_SYS_MCKR_CSS 0x1302
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#define ATMEL_BASE_MPDDRC ATMEL_BASE_DDRSDRC0
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#endif
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#endif
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@ -259,8 +259,6 @@
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#define CONFIG_SYS_MCKR 0x1301
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#define CONFIG_SYS_MCKR 0x1301
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#define CONFIG_SYS_MCKR_CSS 0x1302
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#define CONFIG_SYS_MCKR_CSS 0x1302
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#define ATMEL_BASE_MPDDRC ATMEL_BASE_DDRSDRC
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#ifdef CONFIG_SYS_USE_MMC
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#ifdef CONFIG_SYS_USE_MMC
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#define CONFIG_SPL_LDSCRIPT arch/arm/mach-at91/arm926ejs/u-boot-spl.lds
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#define CONFIG_SPL_LDSCRIPT arch/arm/mach-at91/arm926ejs/u-boot-spl.lds
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#define CONFIG_SPL_MMC_SUPPORT
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#define CONFIG_SPL_MMC_SUPPORT
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#define CONFIG_SYS_MCKR 0x1301
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#define CONFIG_SYS_MCKR 0x1301
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#define CONFIG_SYS_MCKR_CSS 0x1302
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#define CONFIG_SYS_MCKR_CSS 0x1302
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#define ATMEL_BASE_MPDDRC ATMEL_BASE_DDRSDRC
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#ifdef CONFIG_SYS_USE_MMC
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#ifdef CONFIG_SYS_USE_MMC
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#define CONFIG_SPL_LDSCRIPT arch/arm/mach-at91/arm926ejs/u-boot-spl.lds
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#define CONFIG_SPL_LDSCRIPT arch/arm/mach-at91/arm926ejs/u-boot-spl.lds
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#define CONFIG_SPL_MMC_SUPPORT
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#define CONFIG_SPL_MMC_SUPPORT
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#define CONFIG_SYS_MCKR 0x1301
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#define CONFIG_SYS_MCKR 0x1301
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#define CONFIG_SYS_MCKR_CSS 0x1302
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#define CONFIG_SYS_MCKR_CSS 0x1302
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#define ATMEL_BASE_MPDDRC ATMEL_BASE_DDRSDRC0
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#endif
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#endif
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