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ppc4xx: Update APC405 board support

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- enable esd's auto_update mechanism
- fix LCD support on latest hardware revision (uses other LCD controller)
- support alternative flash layout on rev. 1.8 boards
- coding style cleanup

Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
This commit is contained in:
Matthias Fuchs 2008-04-21 14:42:11 +02:00 committed by Stefan Roese
parent 83975d02e2
commit 0b9872515a
2 changed files with 242 additions and 124 deletions
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4
board/esd/apc405/Makefile
View File

@ -28,7 +28,9 @@ endif
LIB = $(obj)lib$(BOARD).a LIB = $(obj)lib$(BOARD).a
COBJS = $(BOARD).o strataflash.o ../common/misc.o COBJS = $(BOARD).o \
../common/misc.o \
../common/auto_update.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS)) OBJS := $(addprefix $(obj),$(COBJS))

362
board/esd/apc405/apc405.c
View File

@ -1,4 +1,7 @@
/* /*
* (C) Copyright 2005-2008
* Matthias Fuchs, esd gmbh germany, matthias.fuchs@esd-electronics.com
*
* (C) Copyright 2001-2003 * (C) Copyright 2001-2003
* Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
* *
@ -23,17 +26,22 @@
#include <common.h> #include <common.h>
#include <asm/processor.h> #include <asm/processor.h>
#include <asm/io.h>
#include <command.h> #include <command.h>
#include <malloc.h> #include <malloc.h>
#include <flash.h>
#include <asm/4xx_pci.h>
#include <pci.h>
DECLARE_GLOBAL_DATA_PTR; DECLARE_GLOBAL_DATA_PTR;
#if 0 #undef FPGA_DEBUG
#define FPGA_DEBUG
#endif
extern int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); extern int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]);
extern void lxt971_no_sleep(void); extern void lxt971_no_sleep(void);
extern ulong flash_get_size (ulong base, int banknum);
int flash_banks = CFG_MAX_FLASH_BANKS_DETECT;
/* fpga configuration data - gzip compressed and generated by bin2c */ /* fpga configuration data - gzip compressed and generated by bin2c */
const unsigned char fpgadata[] = const unsigned char fpgadata[] =
@ -46,82 +54,94 @@ const unsigned char fpgadata[] =
*/ */
#include "../common/fpga.c" #include "../common/fpga.c"
/* Prototypes */ /* Prototypes */
int gunzip(void *, int, unsigned char *, unsigned long *); int gunzip(void *, int, unsigned char *, unsigned long *);
#ifdef CONFIG_LCD_USED #ifdef CONFIG_LCD_USED
/* logo bitmap data - gzip compressed and generated by bin2c */ /* logo bitmap data - gzip compressed and generated by bin2c */
unsigned char logo_bmp[] = unsigned char logo_bmp[] =
{ {
#include CFG_LCD_LOGO_NAME #include "logo_640_480_24bpp.c"
}; };
/* /*
* include common lcd code (for esd boards) * include common lcd code (for esd boards)
*/ */
#include "../common/lcd.c" #include "../common/lcd.c"
#include "../common/s1d13505_640_480_16bpp.h"
#include CFG_LCD_HEADER_NAME #include "../common/s1d13806_640_480_16bpp.h"
#endif /* CONFIG_LCD_USED */ #endif /* CONFIG_LCD_USED */
/*
* include common auto-update code (for esd boards)
*/
#include "../common/auto_update.h"
au_image_t au_image[] = {
{"preinst.img", 0, -1, AU_SCRIPT},
{"u-boot.img", 0xfff80000, 0x00080000, AU_FIRMWARE | AU_PROTECT},
{"pImage", 0xfe000000, 0x00100000, AU_NOR | AU_PROTECT},
{"pImage.initrd", 0xfe100000, 0x00400000, AU_NOR | AU_PROTECT},
{"work.img", 0xfe500000, 0x01400000, AU_NOR},
{"data.img", 0xff900000, 0x00580000, AU_NOR},
{"logo.img", 0xffe80000, 0x00100000, AU_NOR | AU_PROTECT},
{"postinst.img", 0, 0, AU_SCRIPT},
};
int N_AU_IMAGES = (sizeof(au_image) / sizeof(au_image[0]));
int board_revision(void) int board_revision(void)
{ {
unsigned long cntrl0Reg; unsigned long cntrl0Reg;
unsigned long value; volatile unsigned long value;
/* /*
* Get version of APC405 board from GPIO's * Get version of APC405 board from GPIO's
*/ */
/* /* Setup GPIO pins (CS2/GPIO11, CS3/GPIO12 and CS4/GPIO13 as GPIO) */
* Setup GPIO pins (CS2/GPIO11 and CS3/GPIO12 as GPIO)
*/
cntrl0Reg = mfdcr(cntrl0); cntrl0Reg = mfdcr(cntrl0);
mtdcr(cntrl0, cntrl0Reg | 0x03000000); mtdcr(cntrl0, cntrl0Reg | 0x03800000);
out32(GPIO0_ODR, in32(GPIO0_ODR) & ~0x00180000); out_be32((void*)GPIO0_ODR, in_be32((void*)GPIO0_ODR) & ~0x001c0000);
out32(GPIO0_TCR, in32(GPIO0_TCR) & ~0x00180000); out_be32((void*)GPIO0_TCR, in_be32((void*)GPIO0_TCR) & ~0x001c0000);
udelay(1000); /* wait some time before reading input */
value = in32(GPIO0_IR) & 0x00180000; /* get config bits */
/* wait some time before reading input */
udelay(1000);
/* get config bits */
value = in_be32((void*)GPIO0_IR) & 0x001c0000;
/* /*
* Restore GPIO settings * Restore GPIO settings
*/ */
mtdcr(cntrl0, cntrl0Reg); mtdcr(cntrl0, cntrl0Reg);
switch (value) { switch (value) {
case 0x00180000: case 0x001c0000:
/* CS2==1 && CS3==1 -> version <= 1.2 */ /* CS2==1 && CS3==1 && CS4==1 -> version <= 1.2 */
return 2; return 2;
case 0x00080000: case 0x000c0000:
/* CS2==0 && CS3==1 -> version 1.3 */ /* CS2==0 && CS3==1 && CS4==1 -> version 1.3 */
return 3; return 3;
#if 0 /* not yet manufactured ! */ case 0x00180000:
case 0x00100000: /* CS2==1 && CS3==1 && CS4==0 -> version 1.6 */
/* CS2==1 && CS3==0 -> version 1.4 */ return 6;
return 4; case 0x00140000:
case 0x00000000: /* CS2==1 && CS3==0 && CS4==1 -> version 1.8 */
/* CS2==0 && CS3==0 -> version 1.5 */ return 8;
return 5;
#endif
default: default:
/* should not be reached! */ /* should not be reached! */
return 0; return 0;
} }
} }
int board_early_init_f (void) int board_early_init_f (void)
{ {
/* /*
* First pull fpga-prg pin low, to disable fpga logic (on version 2 board) * First pull fpga-prg pin low, to disable fpga logic
*/ */
out32(GPIO0_ODR, 0x00000000); /* no open drain pins */ out_be32((void*)GPIO0_ODR, 0x00000000); /* no open drain pins */
out32(GPIO0_TCR, CFG_FPGA_PRG); /* setup for output */ out_be32((void*)GPIO0_TCR, CFG_FPGA_PRG); /* setup for output */
out32(GPIO0_OR, CFG_FPGA_PRG); /* set output pins to high */ out_be32((void*)GPIO0_OR, 0); /* pull prg low */
out32(GPIO0_OR, 0); /* pull prg low */
/* /*
* IRQ 0-15 405GP internally generated; active high; level sensitive * IRQ 0-15 405GP internally generated; active high; level sensitive
@ -140,48 +160,61 @@ int board_early_init_f (void)
mtdcr(uiccr, 0x00000000); /* set all to be non-critical*/ mtdcr(uiccr, 0x00000000); /* set all to be non-critical*/
mtdcr(uicpr, 0xFFFFFF81); /* set int polarities */ mtdcr(uicpr, 0xFFFFFF81); /* set int polarities */
mtdcr(uictr, 0x10000000); /* set int trigger levels */ mtdcr(uictr, 0x10000000); /* set int trigger levels */
mtdcr(uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority*/ mtdcr(uicvcr, 0x00000001); /* set vect base=0 */
mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */ mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
/* /*
* EBC Configuration Register: set ready timeout to 512 ebc-clks -> ca. 15 us * EBC Configuration Register: set ready timeout to 512 ebc-clks
*/ */
#if 1 /* test-only */ mtebc(epcr, 0xa8400000); /* ebc always driven */
mtebc (epcr, 0xa8400000); /* ebc always driven */
#else /*
mtebc (epcr, 0x28400000); /* ebc in high-z */ * New boards have a single 32MB flash connected to CS0
#endif * instead of two 16MB flashes on CS0+1.
*/
if (board_revision() >= 8) {
/* disable CS1 */
mtebc(pb1ap, 0);
mtebc(pb1cr, 0);
/* resize CS0 to 32MB */
mtebc(pb0ap, CFG_EBC_PB0AP_HWREV8);
mtebc(pb0cr, CFG_EBC_PB0CR_HWREV8);
}
return 0; return 0;
} }
int board_early_init_r(void)
/* ------------------------------------------------------------------------- */
int misc_init_f (void)
{ {
return 0; /* dummy implementation */ if (gd->board_type >= 8)
flash_banks = 1;
return 0;
} }
#define FUJI_BASE 0xf0100200
#define LCDBL_PWM 0xa0
#define LCDBL_PWMMIN 0xa4
#define LCDBL_PWMMAX 0xa8
int misc_init_r (void) int misc_init_r(void)
{ {
volatile unsigned short *fpga_mode = u16 *fpga_mode = (u16 *)(CFG_FPGA_BASE_ADDR + CFG_FPGA_CTRL);
(unsigned short *)((ulong)CFG_FPGA_BASE_ADDR + CFG_FPGA_CTRL); u16 *fpga_ctrl2 =(u16 *)(CFG_FPGA_BASE_ADDR + CFG_FPGA_CTRL2);
volatile unsigned short *fpga_ctrl2 = u8 *duart0_mcr = (u8 *)(DUART0_BA + 4);
(unsigned short *)((ulong)CFG_FPGA_BASE_ADDR + CFG_FPGA_CTRL2); u8 *duart1_mcr = (u8 *)(DUART1_BA + 4);
volatile unsigned char *duart0_mcr =
(unsigned char *)((ulong)DUART0_BA + 4);
volatile unsigned char *duart1_mcr =
(unsigned char *)((ulong)DUART1_BA + 4);
volatile unsigned short *fuji_lcdbl_pwm =
(unsigned short *)((ulong)0xf0100200 + 0xa0);
unsigned char *dst; unsigned char *dst;
ulong len = sizeof(fpgadata); ulong len = sizeof(fpgadata);
int status; int status;
int index; int index;
int i; int i;
unsigned long cntrl0Reg; unsigned long cntrl0Reg;
char *str;
uchar *logo_addr;
ulong logo_size;
ushort minb, maxb;
int result;
/* /*
* Setup GPIO pins (CS6+CS7 as GPIO) * Setup GPIO pins (CS6+CS7 as GPIO)
@ -190,9 +223,9 @@ int misc_init_r (void)
mtdcr(cntrl0, cntrl0Reg | 0x00300000); mtdcr(cntrl0, cntrl0Reg | 0x00300000);
dst = malloc(CFG_FPGA_MAX_SIZE); dst = malloc(CFG_FPGA_MAX_SIZE);
if (gunzip (dst, CFG_FPGA_MAX_SIZE, (uchar *)fpgadata, &len) != 0) { if (gunzip(dst, CFG_FPGA_MAX_SIZE, (uchar *)fpgadata, &len) != 0) {
printf ("GUNZIP ERROR - must RESET board to recover\n"); printf("GUNZIP ERROR - must RESET board to recover\n");
do_reset (NULL, 0, 0, NULL); do_reset(NULL, 0, 0, NULL);
} }
status = fpga_boot(dst, len); status = fpga_boot(dst, len);
@ -200,31 +233,34 @@ int misc_init_r (void)
printf("\nFPGA: Booting failed "); printf("\nFPGA: Booting failed ");
switch (status) { switch (status) {
case ERROR_FPGA_PRG_INIT_LOW: case ERROR_FPGA_PRG_INIT_LOW:
printf("(Timeout: INIT not low after asserting PROGRAM*)\n "); printf("(Timeout: "
"INIT not low after asserting PROGRAM*)\n ");
break; break;
case ERROR_FPGA_PRG_INIT_HIGH: case ERROR_FPGA_PRG_INIT_HIGH:
printf("(Timeout: INIT not high after deasserting PROGRAM*)\n "); printf("(Timeout: "
"INIT not high after deasserting PROGRAM*)\n ");
break; break;
case ERROR_FPGA_PRG_DONE: case ERROR_FPGA_PRG_DONE:
printf("(Timeout: DONE not high after programming FPGA)\n "); printf("(Timeout: "
"DONE not high after programming FPGA)\n ");
break; break;
} }
/* display infos on fpgaimage */ /* display infos on fpgaimage */
index = 15; index = 15;
for (i=0; i<4; i++) { for (i = 0; i < 4; i++) {
len = dst[index]; len = dst[index];
printf("FPGA: %s\n", &(dst[index+1])); printf("FPGA: %s\n", &(dst[index+1]));
index += len+3; index += len + 3;
} }
putc ('\n'); putc('\n');
/* delayed reboot */ /* delayed reboot */
for (i=20; i>0; i--) { for (i = 20; i > 0; i--) {
printf("Rebooting in %2d seconds \r",i); printf("Rebooting in %2d seconds \r",i);
for (index=0;index<1000;index++) for (index = 0; index < 1000; index++)
udelay(1000); udelay(1000);
} }
putc ('\n'); putc('\n');
do_reset(NULL, 0, 0, NULL); do_reset(NULL, 0, 0, NULL);
} }
@ -235,12 +271,12 @@ int misc_init_r (void)
/* display infos on fpgaimage */ /* display infos on fpgaimage */
index = 15; index = 15;
for (i=0; i<4; i++) { for (i = 0; i < 4; i++) {
len = dst[index]; len = dst[index];
printf("%s ", &(dst[index+1])); printf("%s ", &(dst[index + 1]));
index += len+3; index += len + 3;
} }
putc ('\n'); putc('\n');
free(dst); free(dst);
@ -255,51 +291,117 @@ int misc_init_r (void)
/* /*
* Write board revision in FPGA * Write board revision in FPGA
*/ */
*fpga_ctrl2 = (*fpga_ctrl2 & 0xfff0) | (gd->board_type & 0x000f); out_be16(fpga_ctrl2,
(in_be16(fpga_ctrl2) & 0xfff0) | (gd->board_type & 0x000f));
/* /*
* Enable power on PS/2 interface (with reset) * Enable power on PS/2 interface (with reset)
*/ */
*fpga_mode |= CFG_FPGA_CTRL_PS2_RESET; out_be16(fpga_mode, in_be16(fpga_mode) | CFG_FPGA_CTRL_PS2_RESET);
for (i=0;i<100;i++) for (i=0;i<100;i++)
udelay(1000); udelay(1000);
udelay(1000); udelay(1000);
*fpga_mode &= ~CFG_FPGA_CTRL_PS2_RESET; out_be16(fpga_mode, in_be16(fpga_mode) & ~CFG_FPGA_CTRL_PS2_RESET);
/* /*
* Enable interrupts in exar duart mcr[3] * Enable interrupts in exar duart mcr[3]
*/ */
*duart0_mcr = 0x08; out_8(duart0_mcr, 0x08);
*duart1_mcr = 0x08; out_8(duart1_mcr, 0x08);
/* /*
* Init lcd interface and display logo * Init lcd interface and display logo
*/ */
lcd_init((uchar *)CFG_LCD_BIG_REG, (uchar *)CFG_LCD_BIG_MEM, str = getenv("splashimage");
regs_13806_640_480_16bpp, if (str) {
sizeof(regs_13806_640_480_16bpp)/sizeof(regs_13806_640_480_16bpp[0]), logo_addr = (uchar *)simple_strtoul(str, NULL, 16);
logo_bmp, sizeof(logo_bmp)); logo_size = CFG_VIDEO_LOGO_MAX_SIZE;
} else {
logo_addr = logo_bmp;
logo_size = sizeof(logo_bmp);
}
if (gd->board_type >= 6) {
result = lcd_init((uchar *)CFG_LCD_BIG_REG,
(uchar *)CFG_LCD_BIG_MEM,
regs_13505_640_480_16bpp,
sizeof(regs_13505_640_480_16bpp) /
sizeof(regs_13505_640_480_16bpp[0]),
logo_addr, logo_size);
if (result && str) {
/* retry with internal image */
logo_addr = logo_bmp;
logo_size = sizeof(logo_bmp);
lcd_init((uchar *)CFG_LCD_BIG_REG,
(uchar *)CFG_LCD_BIG_MEM,
regs_13505_640_480_16bpp,
sizeof(regs_13505_640_480_16bpp) /
sizeof(regs_13505_640_480_16bpp[0]),
logo_addr, logo_size);
}
} else {
result = lcd_init((uchar *)CFG_LCD_BIG_REG,
(uchar *)CFG_LCD_BIG_MEM,
regs_13806_640_480_16bpp,
sizeof(regs_13806_640_480_16bpp) /
sizeof(regs_13806_640_480_16bpp[0]),
logo_addr, logo_size);
if (result && str) {
/* retry with internal image */
logo_addr = logo_bmp;
logo_size = sizeof(logo_bmp);
lcd_init((uchar *)CFG_LCD_BIG_REG,
(uchar *)CFG_LCD_BIG_MEM,
regs_13806_640_480_16bpp,
sizeof(regs_13806_640_480_16bpp) /
sizeof(regs_13806_640_480_16bpp[0]),
logo_addr, logo_size);
}
}
/* /*
* Reset microcontroller and setup backlight PWM controller * Reset microcontroller and setup backlight PWM controller
*/ */
*fpga_mode |= 0x0014; out_be16(fpga_mode, in_be16(fpga_mode) | 0x0014);
for (i=0;i<10;i++) for (i=0;i<10;i++)
udelay(1000); udelay(1000);
*fpga_mode |= 0x001c; out_be16(fpga_mode, in_be16(fpga_mode) | 0x001c);
*fuji_lcdbl_pwm = 0x00ff;
minb = 0;
maxb = 0xff;
str = getenv("lcdbl");
if (str) {
minb = (ushort)simple_strtoul(str, &str, 16) & 0x00ff;
if (str && (*str=',')) {
str++;
maxb = (ushort)simple_strtoul(str, NULL, 16) & 0x00ff;
} else
minb = 0;
out_be16((u16 *)(FUJI_BASE + LCDBL_PWMMIN), minb);
out_be16((u16 *)(FUJI_BASE + LCDBL_PWMMAX), maxb);
printf("LCDBL: min=0x%02x, max=0x%02x\n", minb, maxb);
}
out_be16((u16 *)(FUJI_BASE + LCDBL_PWM), 0xff);
if (getenv("usb_self") == NULL) {
setenv("usb_load", CFG_USB_LOAD_COMMAND);
setenv("usbargs", CFG_USB_ARGS);
setenv("bootcmd", CONFIG_BOOTCOMMAND);
setenv("usb_self", CFG_USB_SELF_COMMAND);
saveenv();
}
return (0); return (0);
} }
/* /*
* Check Board Identity: * Check Board Identity:
*/ */
int checkboard (void) int checkboard (void)
{ {
unsigned char str[64]; char str[64];
int i = getenv_r ("serial#", str, sizeof(str)); int i = getenv_r ("serial#", str, sizeof(str));
puts ("Board: "); puts ("Board: ");
@ -311,18 +413,11 @@ int checkboard (void)
} }
gd->board_type = board_revision(); gd->board_type = board_revision();
printf(", Rev 1.%ld\n", gd->board_type); printf(", Rev. 1.%ld\n", gd->board_type);
/*
* Disable sleep mode in LXT971
*/
lxt971_no_sleep();
return 0; return 0;
} }
/* ------------------------------------------------------------------------- */
long int initdram (int board_type) long int initdram (int board_type)
{ {
unsigned long val; unsigned long val;
@ -330,43 +425,64 @@ long int initdram (int board_type)
mtdcr(memcfga, mem_mb0cf); mtdcr(memcfga, mem_mb0cf);
val = mfdcr(memcfgd); val = mfdcr(memcfgd);
#if 0
printf("\nmb0cf=%x\n", val); /* test-only */
printf("strap=%x\n", mfdcr(strap)); /* test-only */
#endif
return (4*1024*1024 << ((val & 0x000e0000) >> 17)); return (4*1024*1024 << ((val & 0x000e0000) >> 17));
} }
/* ------------------------------------------------------------------------- */
int testdram (void)
{
/* TODO: XXX XXX XXX */
printf ("test: 16 MB - ok\n");
return (0);
}
/* ------------------------------------------------------------------------- */
#ifdef CONFIG_IDE_RESET #ifdef CONFIG_IDE_RESET
void ide_set_reset(int on) void ide_set_reset(int on)
{ {
volatile unsigned short *fpga_mode = u16 *fpga_mode = (u16 *)(CFG_FPGA_BASE_ADDR + CFG_FPGA_CTRL);
(unsigned short *)((ulong)CFG_FPGA_BASE_ADDR + CFG_FPGA_CTRL);
/* /*
* Assert or deassert CompactFlash Reset Pin * Assert or deassert CompactFlash Reset Pin
*/ */
if (on) { /* assert RESET */ if (on) {
*fpga_mode &= ~(CFG_FPGA_CTRL_CF_RESET); out_be16(fpga_mode,
} else { /* release RESET */ in_be16(fpga_mode) & ~CFG_FPGA_CTRL_CF_RESET);
*fpga_mode |= CFG_FPGA_CTRL_CF_RESET; } else {
out_be16(fpga_mode,
in_be16(fpga_mode) | CFG_FPGA_CTRL_CF_RESET);
} }
} }
#endif /* CONFIG_IDE_RESET */ #endif /* CONFIG_IDE_RESET */
/* ------------------------------------------------------------------------- */ void reset_phy(void)
{
/*
* Disable sleep mode in LXT971
*/
lxt971_no_sleep();
}
#if defined(CONFIG_USB_OHCI_NEW) && defined(CFG_USB_OHCI_BOARD_INIT)
int usb_board_init(void)
{
return 0;
}
int usb_board_stop(void)
{
unsigned short tmp;
int i;
/*
* reset PCI bus
* This is required to make some very old Linux OHCI driver
* work after U-Boot has used the OHCI controller.
*/
pci_read_config_word(PCIDEVID_405GP, PCIBRDGOPT2, &tmp);
pci_write_config_word(PCIDEVID_405GP, PCIBRDGOPT2, (tmp | 0x1000));
for (i = 0; i < 100; i++)
udelay(1000);
pci_write_config_word(PCIDEVID_405GP, PCIBRDGOPT2, tmp);
return 0;
}
int usb_board_init_fail(void)
{
usb_board_stop();
return 0;
}
#endif /* defined(CONFIG_USB_OHCI) && defined(CFG_USB_OHCI_BOARD_INIT) */