mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-08-17 15:38:51 +09:00
Merge branch 'master' of git://git.denx.de/u-boot-net
This commit is contained in:
commit
0b692dcb19
@ -293,7 +293,7 @@ int miiphy_info (char *devname, unsigned char addr, unsigned int *oui,
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int miiphy_reset (char *devname, unsigned char addr)
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{
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unsigned short reg;
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int loop_cnt;
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int timeout = 500;
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if (miiphy_read (devname, addr, PHY_BMCR, ®) != 0) {
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debug ("PHY status read failed\n");
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@ -311,13 +311,13 @@ int miiphy_reset (char *devname, unsigned char addr)
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* auto-clearing). This should happen within 0.5 seconds per the
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* IEEE spec.
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*/
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loop_cnt = 0;
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reg = 0x8000;
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while (((reg & 0x8000) != 0) && (loop_cnt++ < 1000000)) {
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if (miiphy_read (devname, addr, PHY_BMCR, ®) != 0) {
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debug ("PHY status read failed\n");
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return (-1);
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while (((reg & 0x8000) != 0) && timeout--) {
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if (miiphy_read(devname, addr, PHY_BMCR, ®) != 0) {
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debug("PHY status read failed\n");
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return -1;
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}
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udelay(1000);
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}
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if ((reg & 0x8000) == 0) {
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return (0);
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@ -108,6 +108,17 @@ static int fec_miiphy_read(char *dev, uint8_t phyAddr, uint8_t regAddr,
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return 0;
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}
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static void fec_mii_setspeed(struct fec_priv *fec)
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{
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/*
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* Set MII_SPEED = (1/(mii_speed * 2)) * System Clock
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* and do not drop the Preamble.
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*/
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writel((((imx_get_fecclk() / 1000000) + 2) / 5) << 1,
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&fec->eth->mii_speed);
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debug("fec_init: mii_speed %#lx\n",
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fec->eth->mii_speed);
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}
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static int fec_miiphy_write(char *dev, uint8_t phyAddr, uint8_t regAddr,
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uint16_t data)
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{
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@ -236,7 +247,7 @@ static int fec_rbd_init(struct fec_priv *fec, int count, int size)
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fec->rdb_ptr = malloc(size * count + DB_DATA_ALIGNMENT);
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p = (uint32_t)fec->rdb_ptr;
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if (!p) {
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puts("fec_imx27: not enough malloc memory!\n");
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puts("fec_mxc: not enough malloc memory\n");
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return -ENOMEM;
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}
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memset((void *)p, 0, size * count + DB_DATA_ALIGNMENT);
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@ -299,6 +310,13 @@ static void fec_rbd_clean(int last, struct fec_bd *pRbd)
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static int fec_get_hwaddr(struct eth_device *dev, unsigned char *mac)
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{
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/*
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* The MX27 can store the mac address in internal eeprom
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* This mechanism is not supported now by MX51
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*/
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#ifdef CONFIG_MX51
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return -1;
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#else
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struct iim_regs *iim = (struct iim_regs *)IMX_IIM_BASE;
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int i;
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@ -306,10 +324,12 @@ static int fec_get_hwaddr(struct eth_device *dev, unsigned char *mac)
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mac[6-1-i] = readl(&iim->iim_bank_area0[IIM0_MAC + i]);
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return is_valid_ether_addr(mac);
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#endif
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}
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static int fec_set_hwaddr(struct eth_device *dev, unsigned char *mac)
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static int fec_set_hwaddr(struct eth_device *dev)
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{
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uchar *mac = dev->enetaddr;
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struct fec_priv *fec = (struct fec_priv *)dev->priv;
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writel(0, &fec->eth->iaddr1);
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@ -373,7 +393,7 @@ static int fec_init(struct eth_device *dev, bd_t* bd)
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sizeof(struct fec_bd) + DB_ALIGNMENT);
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base = (uint32_t)fec->base_ptr;
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if (!base) {
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puts("fec_imx27: not enough malloc memory!\n");
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puts("fec_mxc: not enough malloc memory\n");
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return -ENOMEM;
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}
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memset((void *)base, 0, (2 + FEC_RBD_NUM) *
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@ -411,14 +431,8 @@ static int fec_init(struct eth_device *dev, bd_t* bd)
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* Frame length=1518; MII mode;
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*/
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writel(0x05ee0024, &fec->eth->r_cntrl); /* FIXME 0x05ee0004 */
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/*
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* Set MII_SPEED = (1/(mii_speed * 2)) * System Clock
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* and do not drop the Preamble.
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*/
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writel((((imx_get_ahbclk() / 1000000) + 2) / 5) << 1,
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&fec->eth->mii_speed);
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debug("fec_init: mii_speed %#lx\n",
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(((imx_get_ahbclk() / 1000000) + 2) / 5) << 1);
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fec_mii_setspeed(fec);
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}
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/*
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* Set Opcode/Pause Duration Register
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@ -460,6 +474,7 @@ static int fec_init(struct eth_device *dev, bd_t* bd)
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miiphy_restart_aneg(dev);
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fec_open(dev);
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fec_set_hwaddr(dev);
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return 0;
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}
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@ -522,7 +537,7 @@ static int fec_send(struct eth_device *dev, volatile void* packet, int length)
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* Check for valid length of data.
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*/
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if ((length > 1500) || (length <= 0)) {
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printf("Payload (%d) to large!\n", length);
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printf("Payload (%d) too large\n", length);
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return -1;
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}
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@ -651,22 +666,14 @@ static int fec_recv(struct eth_device *dev)
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static int fec_probe(bd_t *bd)
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{
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struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE;
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struct eth_device *edev;
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struct fec_priv *fec = &gfec;
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unsigned char ethaddr_str[20];
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unsigned char ethaddr[6];
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char *tmp = getenv("ethaddr");
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char *end;
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/* enable FEC clock */
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writel(readl(&pll->pccr1) | PCCR1_HCLK_FEC, &pll->pccr1);
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writel(readl(&pll->pccr0) | PCCR0_FEC_EN, &pll->pccr0);
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/* create and fill edev struct */
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edev = (struct eth_device *)malloc(sizeof(struct eth_device));
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if (!edev) {
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puts("fec_imx27: not enough malloc memory!\n");
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puts("fec_mxc: not enough malloc memory\n");
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return -ENOMEM;
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}
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edev->priv = fec;
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@ -702,14 +709,7 @@ static int fec_probe(bd_t *bd)
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* Frame length=1518; MII mode;
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*/
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writel(0x05ee0024, &fec->eth->r_cntrl); /* FIXME 0x05ee0004 */
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/*
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* Set MII_SPEED = (1/(mii_speed * 2)) * System Clock
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* and do not drop the Preamble.
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*/
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writel((((imx_get_ahbclk() / 1000000) + 2) / 5) << 1,
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&fec->eth->mii_speed);
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debug("fec_init: mii_speed %#lx\n",
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(((imx_get_ahbclk() / 1000000) + 2) / 5) << 1);
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fec_mii_setspeed(fec);
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sprintf(edev->name, "FEC_MXC");
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@ -717,20 +717,11 @@ static int fec_probe(bd_t *bd)
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eth_register(edev);
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if ((NULL != tmp) && (12 <= strlen(tmp))) {
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int i;
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/* convert MAC from string to int */
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for (i = 0; i < 6; i++) {
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ethaddr[i] = tmp ? simple_strtoul(tmp, &end, 16) : 0;
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if (tmp)
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tmp = (*end) ? end + 1 : end;
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}
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} else if (fec_get_hwaddr(edev, ethaddr) == 0) {
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if (fec_get_hwaddr(edev, ethaddr) == 0) {
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printf("got MAC address from EEPROM: %pM\n", ethaddr);
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setenv("ethaddr", (char *)ethaddr_str);
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memcpy(edev->enetaddr, ethaddr, 6);
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fec_set_hwaddr(edev);
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}
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memcpy(edev->enetaddr, ethaddr, 6);
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fec_set_hwaddr(edev, ethaddr);
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return 0;
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}
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@ -39,6 +39,7 @@
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#include "kirkwood_egiga.h"
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#define KIRKWOOD_PHY_ADR_REQUEST 0xee
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#define KWGBE_SMI_REG (((struct kwgbe_registers *)KW_EGIGA0_BASE)->smi)
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/*
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* smi_reg_read - miiphy_read callback function.
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@ -76,7 +77,7 @@ static int smi_reg_read(char *devname, u8 phy_adr, u8 reg_ofs, u16 * data)
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/* wait till the SMI is not busy */
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do {
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/* read smi register */
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smi_reg = KWGBEREG_RD(regs->smi);
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smi_reg = KWGBEREG_RD(KWGBE_SMI_REG);
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if (timeout-- == 0) {
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printf("Err..(%s) SMI busy timeout\n", __FUNCTION__);
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return -EFAULT;
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@ -89,14 +90,14 @@ static int smi_reg_read(char *devname, u8 phy_adr, u8 reg_ofs, u16 * data)
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| KWGBE_PHY_SMI_OPCODE_READ;
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/* write the smi register */
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KWGBEREG_WR(regs->smi, smi_reg);
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KWGBEREG_WR(KWGBE_SMI_REG, smi_reg);
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/*wait till read value is ready */
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timeout = KWGBE_PHY_SMI_TIMEOUT;
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do {
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/* read smi register */
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smi_reg = KWGBEREG_RD(regs->smi);
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smi_reg = KWGBEREG_RD(KWGBE_SMI_REG);
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if (timeout-- == 0) {
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printf("Err..(%s) SMI read ready timeout\n",
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__FUNCTION__);
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@ -107,7 +108,7 @@ static int smi_reg_read(char *devname, u8 phy_adr, u8 reg_ofs, u16 * data)
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/* Wait for the data to update in the SMI register */
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for (timeout = 0; timeout < KWGBE_PHY_SMI_TIMEOUT; timeout++) ;
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*data = (u16) (KWGBEREG_RD(regs->smi) & KWGBE_PHY_SMI_DATA_MASK);
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*data = (u16) (KWGBEREG_RD(KWGBE_SMI_REG) & KWGBE_PHY_SMI_DATA_MASK);
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debug("%s:(adr %d, off %d) value= %04x\n", __FUNCTION__, phy_adr,
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reg_ofs, *data);
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@ -150,7 +151,7 @@ static int smi_reg_write(char *devname, u8 phy_adr, u8 reg_ofs, u16 data)
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timeout = KWGBE_PHY_SMI_TIMEOUT;
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do {
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/* read smi register */
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smi_reg = KWGBEREG_RD(regs->smi);
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smi_reg = KWGBEREG_RD(KWGBE_SMI_REG);
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if (timeout-- == 0) {
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printf("Err..(%s) SMI busy timeout\n", __FUNCTION__);
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return -ETIME;
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@ -164,7 +165,7 @@ static int smi_reg_write(char *devname, u8 phy_adr, u8 reg_ofs, u16 data)
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smi_reg &= ~KWGBE_PHY_SMI_OPCODE_READ;
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/* write the smi register */
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KWGBEREG_WR(regs->smi, smi_reg);
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KWGBEREG_WR(KWGBE_SMI_REG, smi_reg);
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return 0;
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}
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