mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-07-13 14:46:21 +09:00
Merge branch 'master' of git://www.denx.de/git/u-boot-mips
This commit is contained in:
commit
0b20335015
1
MAKEALL
1
MAKEALL
|
@ -554,6 +554,7 @@ LIST_mips5kc_el=""
|
|||
|
||||
LIST_au1xx0_el=" \
|
||||
dbau1550_el \
|
||||
pb1000 \
|
||||
"
|
||||
|
||||
LIST_mips_el=" \
|
||||
|
|
|
@ -54,10 +54,11 @@ SECTIONS
|
|||
|
||||
.sdata : { *(.sdata) }
|
||||
|
||||
. = .;
|
||||
.u_boot_cmd : {
|
||||
__u_boot_cmd_start = .;
|
||||
.u_boot_cmd : { *(.u_boot_cmd) }
|
||||
*(.u_boot_cmd)
|
||||
__u_boot_cmd_end = .;
|
||||
}
|
||||
|
||||
uboot_end_data = .;
|
||||
num_got_entries = (__got_end - __got_start) >> 2;
|
||||
|
|
|
@ -54,9 +54,11 @@ SECTIONS
|
|||
|
||||
.sdata : { *(.sdata) }
|
||||
|
||||
.u_boot_cmd : {
|
||||
__u_boot_cmd_start = .;
|
||||
.u_boot_cmd : { *(.u_boot_cmd) }
|
||||
*(.u_boot_cmd)
|
||||
__u_boot_cmd_end = .;
|
||||
}
|
||||
|
||||
uboot_end_data = .;
|
||||
num_got_entries = (__got_end - __got_start) >> 2;
|
||||
|
|
|
@ -54,10 +54,11 @@ SECTIONS
|
|||
|
||||
.sdata : { *(.sdata) }
|
||||
|
||||
. = .;
|
||||
.u_boot_cmd : {
|
||||
__u_boot_cmd_start = .;
|
||||
.u_boot_cmd : { *(.u_boot_cmd) }
|
||||
*(.u_boot_cmd)
|
||||
__u_boot_cmd_end = .;
|
||||
}
|
||||
|
||||
uboot_end_data = .;
|
||||
num_got_entries = (__got_end - __got_start) >> 2;
|
||||
|
|
|
@ -26,7 +26,7 @@ include $(TOPDIR)/config.mk
|
|||
LIB = $(obj)lib$(BOARD).a
|
||||
|
||||
COBJS = $(BOARD).o flash.o
|
||||
SOBJS = memsetup.o
|
||||
SOBJS = lowlevel_init.o
|
||||
|
||||
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
|
||||
OBJS := $(addprefix $(obj),$(COBJS))
|
||||
|
|
|
@ -15,8 +15,8 @@
|
|||
.set noreorder
|
||||
.set mips32
|
||||
|
||||
.globl memsetup
|
||||
memsetup:
|
||||
.globl lowlevel_init
|
||||
lowlevel_init:
|
||||
/*
|
||||
* Step 1) Establish CPU endian mode.
|
||||
* NOTE: A fair amount of code is necessary on the Pb1000 to
|
|
@ -54,9 +54,11 @@ SECTIONS
|
|||
|
||||
.sdata : { *(.sdata) }
|
||||
|
||||
.u_boot_cmd : {
|
||||
__u_boot_cmd_start = .;
|
||||
.u_boot_cmd : { *(.u_boot_cmd) }
|
||||
*(.u_boot_cmd)
|
||||
__u_boot_cmd_end = .;
|
||||
}
|
||||
|
||||
uboot_end_data = .;
|
||||
num_got_entries = (__got_end - __got_start) >> 2;
|
||||
|
|
|
@ -64,10 +64,11 @@ SECTIONS
|
|||
|
||||
.sdata : { *(.sdata) }
|
||||
|
||||
. = .;
|
||||
.u_boot_cmd : {
|
||||
__u_boot_cmd_start = .;
|
||||
.u_boot_cmd : { *(.u_boot_cmd) }
|
||||
*(.u_boot_cmd)
|
||||
__u_boot_cmd_end = .;
|
||||
}
|
||||
|
||||
uboot_end_data = .;
|
||||
num_got_entries = (__got_end - __got_start) >> 2;
|
||||
|
|
|
@ -54,10 +54,11 @@ SECTIONS
|
|||
|
||||
.sdata : { *(.sdata) }
|
||||
|
||||
. = .;
|
||||
.u_boot_cmd : {
|
||||
__u_boot_cmd_start = .;
|
||||
.u_boot_cmd : { *(.u_boot_cmd) }
|
||||
*(.u_boot_cmd)
|
||||
__u_boot_cmd_end = .;
|
||||
}
|
||||
|
||||
uboot_end_data = .;
|
||||
num_got_entries = (__got_end - __got_start) >> 2;
|
||||
|
|
|
@ -90,6 +90,65 @@ mac_fifo_t mac_fifo[NO_OF_FIFOS];
|
|||
|
||||
#define MAX_WAIT 1000
|
||||
|
||||
#if defined(CONFIG_CMD_MII)
|
||||
int au1x00_miiphy_read(char *devname, unsigned char addr,
|
||||
unsigned char reg, unsigned short * value)
|
||||
{
|
||||
volatile u32 *mii_control_reg = (volatile u32*)(ETH0_BASE+MAC_MII_CNTRL);
|
||||
volatile u32 *mii_data_reg = (volatile u32*)(ETH0_BASE+MAC_MII_DATA);
|
||||
u32 mii_control;
|
||||
unsigned int timedout = 20;
|
||||
|
||||
while (*mii_control_reg & MAC_MII_BUSY) {
|
||||
udelay(1000);
|
||||
if (--timedout == 0) {
|
||||
printf("au1x00_eth: miiphy_read busy timeout!!\n");
|
||||
return -1;
|
||||
}
|
||||
}
|
||||
|
||||
mii_control = MAC_SET_MII_SELECT_REG(reg) |
|
||||
MAC_SET_MII_SELECT_PHY(addr) | MAC_MII_READ;
|
||||
|
||||
*mii_control_reg = mii_control;
|
||||
|
||||
timedout = 20;
|
||||
while (*mii_control_reg & MAC_MII_BUSY) {
|
||||
udelay(1000);
|
||||
if (--timedout == 0) {
|
||||
printf("au1x00_eth: miiphy_read busy timeout!!\n");
|
||||
return -1;
|
||||
}
|
||||
}
|
||||
*value = *mii_data_reg;
|
||||
return 0;
|
||||
}
|
||||
|
||||
int au1x00_miiphy_write(char *devname, unsigned char addr,
|
||||
unsigned char reg, unsigned short value)
|
||||
{
|
||||
volatile u32 *mii_control_reg = (volatile u32*)(ETH0_BASE+MAC_MII_CNTRL);
|
||||
volatile u32 *mii_data_reg = (volatile u32*)(ETH0_BASE+MAC_MII_DATA);
|
||||
u32 mii_control;
|
||||
unsigned int timedout = 20;
|
||||
|
||||
while (*mii_control_reg & MAC_MII_BUSY) {
|
||||
udelay(1000);
|
||||
if (--timedout == 0) {
|
||||
printf("au1x00_eth: miiphy_write busy timeout!!\n");
|
||||
return -1;
|
||||
}
|
||||
}
|
||||
|
||||
mii_control = MAC_SET_MII_SELECT_REG(reg) |
|
||||
MAC_SET_MII_SELECT_PHY(addr) | MAC_MII_WRITE;
|
||||
|
||||
*mii_data_reg = value;
|
||||
*mii_control_reg = mii_control;
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
|
||||
static int au1x00_send(struct eth_device* dev, volatile void *packet, int length){
|
||||
volatile mac_fifo_t *fifo_tx =
|
||||
(volatile mac_fifo_t*)(MAC0_TX_DMA_ADDR+MAC_TX_BUFF0_STATUS);
|
||||
|
@ -249,63 +308,4 @@ int au1x00_enet_initialize(bd_t *bis){
|
|||
return 1;
|
||||
}
|
||||
|
||||
#if defined(CONFIG_CMD_MII)
|
||||
int au1x00_miiphy_read(char *devname, unsigned char addr,
|
||||
unsigned char reg, unsigned short * value)
|
||||
{
|
||||
volatile u32 *mii_control_reg = (volatile u32*)(ETH0_BASE+MAC_MII_CNTRL);
|
||||
volatile u32 *mii_data_reg = (volatile u32*)(ETH0_BASE+MAC_MII_DATA);
|
||||
u32 mii_control;
|
||||
unsigned int timedout = 20;
|
||||
|
||||
while (*mii_control_reg & MAC_MII_BUSY) {
|
||||
udelay(1000);
|
||||
if (--timedout == 0) {
|
||||
printf("au1x00_eth: miiphy_read busy timeout!!\n");
|
||||
return -1;
|
||||
}
|
||||
}
|
||||
|
||||
mii_control = MAC_SET_MII_SELECT_REG(reg) |
|
||||
MAC_SET_MII_SELECT_PHY(addr) | MAC_MII_READ;
|
||||
|
||||
*mii_control_reg = mii_control;
|
||||
|
||||
timedout = 20;
|
||||
while (*mii_control_reg & MAC_MII_BUSY) {
|
||||
udelay(1000);
|
||||
if (--timedout == 0) {
|
||||
printf("au1x00_eth: miiphy_read busy timeout!!\n");
|
||||
return -1;
|
||||
}
|
||||
}
|
||||
*value = *mii_data_reg;
|
||||
return 0;
|
||||
}
|
||||
|
||||
int au1x00_miiphy_write(char *devname, unsigned char addr,
|
||||
unsigned char reg, unsigned short value)
|
||||
{
|
||||
volatile u32 *mii_control_reg = (volatile u32*)(ETH0_BASE+MAC_MII_CNTRL);
|
||||
volatile u32 *mii_data_reg = (volatile u32*)(ETH0_BASE+MAC_MII_DATA);
|
||||
u32 mii_control;
|
||||
unsigned int timedout = 20;
|
||||
|
||||
while (*mii_control_reg & MAC_MII_BUSY) {
|
||||
udelay(1000);
|
||||
if (--timedout == 0) {
|
||||
printf("au1x00_eth: miiphy_write busy timeout!!\n");
|
||||
return;
|
||||
}
|
||||
}
|
||||
|
||||
mii_control = MAC_SET_MII_SELECT_REG(reg) |
|
||||
MAC_SET_MII_SELECT_PHY(addr) | MAC_MII_WRITE;
|
||||
|
||||
*mii_data_reg = value;
|
||||
*mii_control_reg = mii_control;
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* CONFIG_AU1X00 */
|
||||
|
|
|
@ -22,7 +22,6 @@
|
|||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
|
||||
#include <config.h>
|
||||
#include <version.h>
|
||||
#include <asm/regdef.h>
|
||||
|
@ -30,13 +29,11 @@
|
|||
#include <asm/addrspace.h>
|
||||
#include <asm/cacheops.h>
|
||||
|
||||
|
||||
/* 16KB is the maximum size of instruction and data caches on
|
||||
* MIPS 4K.
|
||||
*/
|
||||
#define MIPS_MAX_CACHE_SIZE 0x4000
|
||||
|
||||
|
||||
/*
|
||||
* cacheop macro to automate cache operations
|
||||
* first some helpers...
|
||||
|
@ -131,7 +128,6 @@ mips_cache_reset:
|
|||
li t4, CFG_CACHELINE_SIZE
|
||||
move t5, t4
|
||||
|
||||
|
||||
li v0, MIPS_MAX_CACHE_SIZE
|
||||
|
||||
/* Now clear that much memory starting from zero.
|
||||
|
@ -139,8 +135,8 @@ mips_cache_reset:
|
|||
|
||||
li a0, KSEG1
|
||||
addu a1, a0, v0
|
||||
|
||||
2: sw zero, 0(a0)
|
||||
2:
|
||||
sw zero, 0(a0)
|
||||
sw zero, 4(a0)
|
||||
sw zero, 8(a0)
|
||||
sw zero, 12(a0)
|
||||
|
@ -202,8 +198,8 @@ mips_cache_reset:
|
|||
icacheop(a0,a1,a2,a3,Index_Store_Tag_D)
|
||||
|
||||
j ra
|
||||
.end mips_cache_reset
|
||||
|
||||
.end mips_cache_reset
|
||||
|
||||
/*******************************************************************************
|
||||
*
|
||||
|
@ -242,7 +238,6 @@ dcache_disable:
|
|||
|
||||
.end dcache_disable
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
*
|
||||
* mips_cache_lock - lock RAM area pointed to by a0 in cache.
|
||||
|
@ -266,4 +261,5 @@ mips_cache_lock:
|
|||
icacheop(a0,a1,a2,a3,0x1d)
|
||||
|
||||
j ra
|
||||
|
||||
.end mips_cache_lock
|
||||
|
|
|
@ -20,8 +20,7 @@
|
|||
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
# MA 02111-1307 USA
|
||||
#
|
||||
v=$(shell \
|
||||
$(CROSS_COMPILE)as --version|grep "GNU assembler"|awk '{print $$3}'|awk -F . '{print $$2}')
|
||||
v=$(shell $(AS) --version |grep "GNU assembler" |cut -d. -f2)
|
||||
MIPSFLAGS=$(shell \
|
||||
if [ "$v" -lt "14" ]; then \
|
||||
echo "-mcpu=4kc"; \
|
||||
|
|
|
@ -39,12 +39,12 @@ int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
|
|||
return 0;
|
||||
}
|
||||
|
||||
void flush_cache (ulong start_addr, ulong size)
|
||||
void flush_cache(ulong start_addr, ulong size)
|
||||
{
|
||||
|
||||
}
|
||||
|
||||
void write_one_tlb( int index, u32 pagemask, u32 hi, u32 low0, u32 low1 ){
|
||||
void write_one_tlb(int index, u32 pagemask, u32 hi, u32 low0, u32 low1)
|
||||
{
|
||||
write_32bit_cp0_register(CP0_ENTRYLO0, low0);
|
||||
write_32bit_cp0_register(CP0_PAGEMASK, pagemask);
|
||||
write_32bit_cp0_register(CP0_ENTRYLO1, low1);
|
||||
|
|
|
@ -22,13 +22,11 @@
|
|||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
|
||||
#include <config.h>
|
||||
#include <version.h>
|
||||
#include <asm/regdef.h>
|
||||
#include <asm/mipsregs.h>
|
||||
|
||||
|
||||
#define RVECENT(f,n) \
|
||||
b f; nop
|
||||
#define XVECENT(f,bev) \
|
||||
|
@ -239,10 +237,8 @@ reset:
|
|||
bal 1f
|
||||
nop
|
||||
.word _gp
|
||||
1:
|
||||
move gp, ra
|
||||
lw t1, 0(ra)
|
||||
move gp, t1
|
||||
1:
|
||||
lw gp, 0(ra)
|
||||
|
||||
#ifdef CONFIG_INCA_IP
|
||||
/* Disable INCA-IP Watchdog.
|
||||
|
@ -269,7 +265,6 @@ reset:
|
|||
li t0, CONF_CM_CACHABLE_NONCOHERENT
|
||||
mtc0 t0, CP0_CONFIG
|
||||
|
||||
|
||||
/* Set up temporary stack.
|
||||
*/
|
||||
li a0, CFG_INIT_SP_OFFSET
|
||||
|
@ -284,7 +279,6 @@ reset:
|
|||
j t9
|
||||
nop
|
||||
|
||||
|
||||
/*
|
||||
* void relocate_code (addr_sp, gd, addr_moni)
|
||||
*
|
||||
|
@ -376,7 +370,8 @@ in_ram:
|
|||
add t2, t6
|
||||
|
||||
sub t1, 4
|
||||
1: addi t1, 4
|
||||
1:
|
||||
addi t1, 4
|
||||
bltl t1, t2, 1b
|
||||
sw zero, 0(t1) /* delay slot */
|
||||
|
||||
|
@ -387,7 +382,6 @@ in_ram:
|
|||
|
||||
.end relocate_code
|
||||
|
||||
|
||||
/* Exception handlers.
|
||||
*/
|
||||
romReserved:
|
||||
|
|
Loading…
Reference in New Issue
Block a user