mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-07-13 06:36:16 +09:00
Merge branch 'master' of git://www.denx.de/git/u-boot-mips
This commit is contained in:
commit
0b20335015
1
MAKEALL
1
MAKEALL
|
@ -554,6 +554,7 @@ LIST_mips5kc_el=""
|
||||||
|
|
||||||
LIST_au1xx0_el=" \
|
LIST_au1xx0_el=" \
|
||||||
dbau1550_el \
|
dbau1550_el \
|
||||||
|
pb1000 \
|
||||||
"
|
"
|
||||||
|
|
||||||
LIST_mips_el=" \
|
LIST_mips_el=" \
|
||||||
|
|
|
@ -54,10 +54,11 @@ SECTIONS
|
||||||
|
|
||||||
.sdata : { *(.sdata) }
|
.sdata : { *(.sdata) }
|
||||||
|
|
||||||
. = .;
|
.u_boot_cmd : {
|
||||||
__u_boot_cmd_start = .;
|
__u_boot_cmd_start = .;
|
||||||
.u_boot_cmd : { *(.u_boot_cmd) }
|
*(.u_boot_cmd)
|
||||||
__u_boot_cmd_end = .;
|
__u_boot_cmd_end = .;
|
||||||
|
}
|
||||||
|
|
||||||
uboot_end_data = .;
|
uboot_end_data = .;
|
||||||
num_got_entries = (__got_end - __got_start) >> 2;
|
num_got_entries = (__got_end - __got_start) >> 2;
|
||||||
|
|
|
@ -54,9 +54,11 @@ SECTIONS
|
||||||
|
|
||||||
.sdata : { *(.sdata) }
|
.sdata : { *(.sdata) }
|
||||||
|
|
||||||
__u_boot_cmd_start = .;
|
.u_boot_cmd : {
|
||||||
.u_boot_cmd : { *(.u_boot_cmd) }
|
__u_boot_cmd_start = .;
|
||||||
__u_boot_cmd_end = .;
|
*(.u_boot_cmd)
|
||||||
|
__u_boot_cmd_end = .;
|
||||||
|
}
|
||||||
|
|
||||||
uboot_end_data = .;
|
uboot_end_data = .;
|
||||||
num_got_entries = (__got_end - __got_start) >> 2;
|
num_got_entries = (__got_end - __got_start) >> 2;
|
||||||
|
|
|
@ -54,10 +54,11 @@ SECTIONS
|
||||||
|
|
||||||
.sdata : { *(.sdata) }
|
.sdata : { *(.sdata) }
|
||||||
|
|
||||||
. = .;
|
.u_boot_cmd : {
|
||||||
__u_boot_cmd_start = .;
|
__u_boot_cmd_start = .;
|
||||||
.u_boot_cmd : { *(.u_boot_cmd) }
|
*(.u_boot_cmd)
|
||||||
__u_boot_cmd_end = .;
|
__u_boot_cmd_end = .;
|
||||||
|
}
|
||||||
|
|
||||||
uboot_end_data = .;
|
uboot_end_data = .;
|
||||||
num_got_entries = (__got_end - __got_start) >> 2;
|
num_got_entries = (__got_end - __got_start) >> 2;
|
||||||
|
|
|
@ -26,7 +26,7 @@ include $(TOPDIR)/config.mk
|
||||||
LIB = $(obj)lib$(BOARD).a
|
LIB = $(obj)lib$(BOARD).a
|
||||||
|
|
||||||
COBJS = $(BOARD).o flash.o
|
COBJS = $(BOARD).o flash.o
|
||||||
SOBJS = memsetup.o
|
SOBJS = lowlevel_init.o
|
||||||
|
|
||||||
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
|
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
|
||||||
OBJS := $(addprefix $(obj),$(COBJS))
|
OBJS := $(addprefix $(obj),$(COBJS))
|
||||||
|
|
|
@ -15,8 +15,8 @@
|
||||||
.set noreorder
|
.set noreorder
|
||||||
.set mips32
|
.set mips32
|
||||||
|
|
||||||
.globl memsetup
|
.globl lowlevel_init
|
||||||
memsetup:
|
lowlevel_init:
|
||||||
/*
|
/*
|
||||||
* Step 1) Establish CPU endian mode.
|
* Step 1) Establish CPU endian mode.
|
||||||
* NOTE: A fair amount of code is necessary on the Pb1000 to
|
* NOTE: A fair amount of code is necessary on the Pb1000 to
|
|
@ -54,9 +54,11 @@ SECTIONS
|
||||||
|
|
||||||
.sdata : { *(.sdata) }
|
.sdata : { *(.sdata) }
|
||||||
|
|
||||||
__u_boot_cmd_start = .;
|
.u_boot_cmd : {
|
||||||
.u_boot_cmd : { *(.u_boot_cmd) }
|
__u_boot_cmd_start = .;
|
||||||
__u_boot_cmd_end = .;
|
*(.u_boot_cmd)
|
||||||
|
__u_boot_cmd_end = .;
|
||||||
|
}
|
||||||
|
|
||||||
uboot_end_data = .;
|
uboot_end_data = .;
|
||||||
num_got_entries = (__got_end - __got_start) >> 2;
|
num_got_entries = (__got_end - __got_start) >> 2;
|
||||||
|
|
|
@ -64,10 +64,11 @@ SECTIONS
|
||||||
|
|
||||||
.sdata : { *(.sdata) }
|
.sdata : { *(.sdata) }
|
||||||
|
|
||||||
. = .;
|
.u_boot_cmd : {
|
||||||
__u_boot_cmd_start = .;
|
__u_boot_cmd_start = .;
|
||||||
.u_boot_cmd : { *(.u_boot_cmd) }
|
*(.u_boot_cmd)
|
||||||
__u_boot_cmd_end = .;
|
__u_boot_cmd_end = .;
|
||||||
|
}
|
||||||
|
|
||||||
uboot_end_data = .;
|
uboot_end_data = .;
|
||||||
num_got_entries = (__got_end - __got_start) >> 2;
|
num_got_entries = (__got_end - __got_start) >> 2;
|
||||||
|
|
|
@ -54,10 +54,11 @@ SECTIONS
|
||||||
|
|
||||||
.sdata : { *(.sdata) }
|
.sdata : { *(.sdata) }
|
||||||
|
|
||||||
. = .;
|
.u_boot_cmd : {
|
||||||
__u_boot_cmd_start = .;
|
__u_boot_cmd_start = .;
|
||||||
.u_boot_cmd : { *(.u_boot_cmd) }
|
*(.u_boot_cmd)
|
||||||
__u_boot_cmd_end = .;
|
__u_boot_cmd_end = .;
|
||||||
|
}
|
||||||
|
|
||||||
uboot_end_data = .;
|
uboot_end_data = .;
|
||||||
num_got_entries = (__got_end - __got_start) >> 2;
|
num_got_entries = (__got_end - __got_start) >> 2;
|
||||||
|
|
|
@ -90,6 +90,65 @@ mac_fifo_t mac_fifo[NO_OF_FIFOS];
|
||||||
|
|
||||||
#define MAX_WAIT 1000
|
#define MAX_WAIT 1000
|
||||||
|
|
||||||
|
#if defined(CONFIG_CMD_MII)
|
||||||
|
int au1x00_miiphy_read(char *devname, unsigned char addr,
|
||||||
|
unsigned char reg, unsigned short * value)
|
||||||
|
{
|
||||||
|
volatile u32 *mii_control_reg = (volatile u32*)(ETH0_BASE+MAC_MII_CNTRL);
|
||||||
|
volatile u32 *mii_data_reg = (volatile u32*)(ETH0_BASE+MAC_MII_DATA);
|
||||||
|
u32 mii_control;
|
||||||
|
unsigned int timedout = 20;
|
||||||
|
|
||||||
|
while (*mii_control_reg & MAC_MII_BUSY) {
|
||||||
|
udelay(1000);
|
||||||
|
if (--timedout == 0) {
|
||||||
|
printf("au1x00_eth: miiphy_read busy timeout!!\n");
|
||||||
|
return -1;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
mii_control = MAC_SET_MII_SELECT_REG(reg) |
|
||||||
|
MAC_SET_MII_SELECT_PHY(addr) | MAC_MII_READ;
|
||||||
|
|
||||||
|
*mii_control_reg = mii_control;
|
||||||
|
|
||||||
|
timedout = 20;
|
||||||
|
while (*mii_control_reg & MAC_MII_BUSY) {
|
||||||
|
udelay(1000);
|
||||||
|
if (--timedout == 0) {
|
||||||
|
printf("au1x00_eth: miiphy_read busy timeout!!\n");
|
||||||
|
return -1;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
*value = *mii_data_reg;
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
int au1x00_miiphy_write(char *devname, unsigned char addr,
|
||||||
|
unsigned char reg, unsigned short value)
|
||||||
|
{
|
||||||
|
volatile u32 *mii_control_reg = (volatile u32*)(ETH0_BASE+MAC_MII_CNTRL);
|
||||||
|
volatile u32 *mii_data_reg = (volatile u32*)(ETH0_BASE+MAC_MII_DATA);
|
||||||
|
u32 mii_control;
|
||||||
|
unsigned int timedout = 20;
|
||||||
|
|
||||||
|
while (*mii_control_reg & MAC_MII_BUSY) {
|
||||||
|
udelay(1000);
|
||||||
|
if (--timedout == 0) {
|
||||||
|
printf("au1x00_eth: miiphy_write busy timeout!!\n");
|
||||||
|
return -1;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
mii_control = MAC_SET_MII_SELECT_REG(reg) |
|
||||||
|
MAC_SET_MII_SELECT_PHY(addr) | MAC_MII_WRITE;
|
||||||
|
|
||||||
|
*mii_data_reg = value;
|
||||||
|
*mii_control_reg = mii_control;
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
static int au1x00_send(struct eth_device* dev, volatile void *packet, int length){
|
static int au1x00_send(struct eth_device* dev, volatile void *packet, int length){
|
||||||
volatile mac_fifo_t *fifo_tx =
|
volatile mac_fifo_t *fifo_tx =
|
||||||
(volatile mac_fifo_t*)(MAC0_TX_DMA_ADDR+MAC_TX_BUFF0_STATUS);
|
(volatile mac_fifo_t*)(MAC0_TX_DMA_ADDR+MAC_TX_BUFF0_STATUS);
|
||||||
|
@ -249,63 +308,4 @@ int au1x00_enet_initialize(bd_t *bis){
|
||||||
return 1;
|
return 1;
|
||||||
}
|
}
|
||||||
|
|
||||||
#if defined(CONFIG_CMD_MII)
|
|
||||||
int au1x00_miiphy_read(char *devname, unsigned char addr,
|
|
||||||
unsigned char reg, unsigned short * value)
|
|
||||||
{
|
|
||||||
volatile u32 *mii_control_reg = (volatile u32*)(ETH0_BASE+MAC_MII_CNTRL);
|
|
||||||
volatile u32 *mii_data_reg = (volatile u32*)(ETH0_BASE+MAC_MII_DATA);
|
|
||||||
u32 mii_control;
|
|
||||||
unsigned int timedout = 20;
|
|
||||||
|
|
||||||
while (*mii_control_reg & MAC_MII_BUSY) {
|
|
||||||
udelay(1000);
|
|
||||||
if (--timedout == 0) {
|
|
||||||
printf("au1x00_eth: miiphy_read busy timeout!!\n");
|
|
||||||
return -1;
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
mii_control = MAC_SET_MII_SELECT_REG(reg) |
|
|
||||||
MAC_SET_MII_SELECT_PHY(addr) | MAC_MII_READ;
|
|
||||||
|
|
||||||
*mii_control_reg = mii_control;
|
|
||||||
|
|
||||||
timedout = 20;
|
|
||||||
while (*mii_control_reg & MAC_MII_BUSY) {
|
|
||||||
udelay(1000);
|
|
||||||
if (--timedout == 0) {
|
|
||||||
printf("au1x00_eth: miiphy_read busy timeout!!\n");
|
|
||||||
return -1;
|
|
||||||
}
|
|
||||||
}
|
|
||||||
*value = *mii_data_reg;
|
|
||||||
return 0;
|
|
||||||
}
|
|
||||||
|
|
||||||
int au1x00_miiphy_write(char *devname, unsigned char addr,
|
|
||||||
unsigned char reg, unsigned short value)
|
|
||||||
{
|
|
||||||
volatile u32 *mii_control_reg = (volatile u32*)(ETH0_BASE+MAC_MII_CNTRL);
|
|
||||||
volatile u32 *mii_data_reg = (volatile u32*)(ETH0_BASE+MAC_MII_DATA);
|
|
||||||
u32 mii_control;
|
|
||||||
unsigned int timedout = 20;
|
|
||||||
|
|
||||||
while (*mii_control_reg & MAC_MII_BUSY) {
|
|
||||||
udelay(1000);
|
|
||||||
if (--timedout == 0) {
|
|
||||||
printf("au1x00_eth: miiphy_write busy timeout!!\n");
|
|
||||||
return;
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
mii_control = MAC_SET_MII_SELECT_REG(reg) |
|
|
||||||
MAC_SET_MII_SELECT_PHY(addr) | MAC_MII_WRITE;
|
|
||||||
|
|
||||||
*mii_data_reg = value;
|
|
||||||
*mii_control_reg = mii_control;
|
|
||||||
return 0;
|
|
||||||
}
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#endif /* CONFIG_AU1X00 */
|
#endif /* CONFIG_AU1X00 */
|
||||||
|
|
|
@ -22,7 +22,6 @@
|
||||||
* MA 02111-1307 USA
|
* MA 02111-1307 USA
|
||||||
*/
|
*/
|
||||||
|
|
||||||
|
|
||||||
#include <config.h>
|
#include <config.h>
|
||||||
#include <version.h>
|
#include <version.h>
|
||||||
#include <asm/regdef.h>
|
#include <asm/regdef.h>
|
||||||
|
@ -30,13 +29,11 @@
|
||||||
#include <asm/addrspace.h>
|
#include <asm/addrspace.h>
|
||||||
#include <asm/cacheops.h>
|
#include <asm/cacheops.h>
|
||||||
|
|
||||||
|
|
||||||
/* 16KB is the maximum size of instruction and data caches on
|
/* 16KB is the maximum size of instruction and data caches on
|
||||||
* MIPS 4K.
|
* MIPS 4K.
|
||||||
*/
|
*/
|
||||||
#define MIPS_MAX_CACHE_SIZE 0x4000
|
#define MIPS_MAX_CACHE_SIZE 0x4000
|
||||||
|
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* cacheop macro to automate cache operations
|
* cacheop macro to automate cache operations
|
||||||
* first some helpers...
|
* first some helpers...
|
||||||
|
@ -131,7 +128,6 @@ mips_cache_reset:
|
||||||
li t4, CFG_CACHELINE_SIZE
|
li t4, CFG_CACHELINE_SIZE
|
||||||
move t5, t4
|
move t5, t4
|
||||||
|
|
||||||
|
|
||||||
li v0, MIPS_MAX_CACHE_SIZE
|
li v0, MIPS_MAX_CACHE_SIZE
|
||||||
|
|
||||||
/* Now clear that much memory starting from zero.
|
/* Now clear that much memory starting from zero.
|
||||||
|
@ -139,8 +135,8 @@ mips_cache_reset:
|
||||||
|
|
||||||
li a0, KSEG1
|
li a0, KSEG1
|
||||||
addu a1, a0, v0
|
addu a1, a0, v0
|
||||||
|
2:
|
||||||
2: sw zero, 0(a0)
|
sw zero, 0(a0)
|
||||||
sw zero, 4(a0)
|
sw zero, 4(a0)
|
||||||
sw zero, 8(a0)
|
sw zero, 8(a0)
|
||||||
sw zero, 12(a0)
|
sw zero, 12(a0)
|
||||||
|
@ -156,11 +152,11 @@ mips_cache_reset:
|
||||||
|
|
||||||
mtc0 zero, CP0_TAGLO
|
mtc0 zero, CP0_TAGLO
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* The caches are probably in an indeterminate state,
|
* The caches are probably in an indeterminate state,
|
||||||
* so we force good parity into them by doing an
|
* so we force good parity into them by doing an
|
||||||
* invalidate, load/fill, invalidate for each line.
|
* invalidate, load/fill, invalidate for each line.
|
||||||
*/
|
*/
|
||||||
|
|
||||||
/* Assume bottom of RAM will generate good parity for the cache.
|
/* Assume bottom of RAM will generate good parity for the cache.
|
||||||
*/
|
*/
|
||||||
|
@ -201,9 +197,9 @@ mips_cache_reset:
|
||||||
move a1, a2
|
move a1, a2
|
||||||
icacheop(a0,a1,a2,a3,Index_Store_Tag_D)
|
icacheop(a0,a1,a2,a3,Index_Store_Tag_D)
|
||||||
|
|
||||||
j ra
|
j ra
|
||||||
.end mips_cache_reset
|
|
||||||
|
|
||||||
|
.end mips_cache_reset
|
||||||
|
|
||||||
/*******************************************************************************
|
/*******************************************************************************
|
||||||
*
|
*
|
||||||
|
@ -220,7 +216,7 @@ dcache_status:
|
||||||
andi v0, v0, 1
|
andi v0, v0, 1
|
||||||
j ra
|
j ra
|
||||||
|
|
||||||
.end dcache_status
|
.end dcache_status
|
||||||
|
|
||||||
/*******************************************************************************
|
/*******************************************************************************
|
||||||
*
|
*
|
||||||
|
@ -237,11 +233,10 @@ dcache_disable:
|
||||||
li t1, -8
|
li t1, -8
|
||||||
and t0, t0, t1
|
and t0, t0, t1
|
||||||
ori t0, t0, CONF_CM_UNCACHED
|
ori t0, t0, CONF_CM_UNCACHED
|
||||||
mtc0 t0, CP0_CONFIG
|
mtc0 t0, CP0_CONFIG
|
||||||
j ra
|
j ra
|
||||||
|
|
||||||
.end dcache_disable
|
.end dcache_disable
|
||||||
|
|
||||||
|
|
||||||
/*******************************************************************************
|
/*******************************************************************************
|
||||||
*
|
*
|
||||||
|
@ -266,4 +261,5 @@ mips_cache_lock:
|
||||||
icacheop(a0,a1,a2,a3,0x1d)
|
icacheop(a0,a1,a2,a3,0x1d)
|
||||||
|
|
||||||
j ra
|
j ra
|
||||||
|
|
||||||
.end mips_cache_lock
|
.end mips_cache_lock
|
||||||
|
|
|
@ -20,8 +20,7 @@
|
||||||
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||||
# MA 02111-1307 USA
|
# MA 02111-1307 USA
|
||||||
#
|
#
|
||||||
v=$(shell \
|
v=$(shell $(AS) --version |grep "GNU assembler" |cut -d. -f2)
|
||||||
$(CROSS_COMPILE)as --version|grep "GNU assembler"|awk '{print $$3}'|awk -F . '{print $$2}')
|
|
||||||
MIPSFLAGS=$(shell \
|
MIPSFLAGS=$(shell \
|
||||||
if [ "$v" -lt "14" ]; then \
|
if [ "$v" -lt "14" ]; then \
|
||||||
echo "-mcpu=4kc"; \
|
echo "-mcpu=4kc"; \
|
||||||
|
|
|
@ -39,12 +39,12 @@ int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
|
||||||
return 0;
|
return 0;
|
||||||
}
|
}
|
||||||
|
|
||||||
void flush_cache (ulong start_addr, ulong size)
|
void flush_cache(ulong start_addr, ulong size)
|
||||||
{
|
{
|
||||||
|
|
||||||
}
|
}
|
||||||
|
|
||||||
void write_one_tlb( int index, u32 pagemask, u32 hi, u32 low0, u32 low1 ){
|
void write_one_tlb(int index, u32 pagemask, u32 hi, u32 low0, u32 low1)
|
||||||
|
{
|
||||||
write_32bit_cp0_register(CP0_ENTRYLO0, low0);
|
write_32bit_cp0_register(CP0_ENTRYLO0, low0);
|
||||||
write_32bit_cp0_register(CP0_PAGEMASK, pagemask);
|
write_32bit_cp0_register(CP0_PAGEMASK, pagemask);
|
||||||
write_32bit_cp0_register(CP0_ENTRYLO1, low1);
|
write_32bit_cp0_register(CP0_ENTRYLO1, low1);
|
||||||
|
|
|
@ -22,13 +22,11 @@
|
||||||
* MA 02111-1307 USA
|
* MA 02111-1307 USA
|
||||||
*/
|
*/
|
||||||
|
|
||||||
|
|
||||||
#include <config.h>
|
#include <config.h>
|
||||||
#include <version.h>
|
#include <version.h>
|
||||||
#include <asm/regdef.h>
|
#include <asm/regdef.h>
|
||||||
#include <asm/mipsregs.h>
|
#include <asm/mipsregs.h>
|
||||||
|
|
||||||
|
|
||||||
#define RVECENT(f,n) \
|
#define RVECENT(f,n) \
|
||||||
b f; nop
|
b f; nop
|
||||||
#define XVECENT(f,bev) \
|
#define XVECENT(f,bev) \
|
||||||
|
@ -192,7 +190,7 @@ _start:
|
||||||
.word 0x00000000
|
.word 0x00000000
|
||||||
.word 0x03e00008
|
.word 0x03e00008
|
||||||
.word 0x00000000
|
.word 0x00000000
|
||||||
.word 0x00000000
|
.word 0x00000000
|
||||||
/* 0xbfc00428 */
|
/* 0xbfc00428 */
|
||||||
.word 0xdc870000
|
.word 0xdc870000
|
||||||
.word 0xfca70000
|
.word 0xfca70000
|
||||||
|
@ -203,7 +201,7 @@ _start:
|
||||||
.word 0x00000000
|
.word 0x00000000
|
||||||
.word 0x03e00008
|
.word 0x03e00008
|
||||||
.word 0x00000000
|
.word 0x00000000
|
||||||
.word 0x00000000
|
.word 0x00000000
|
||||||
#endif /* CONFIG_PURPLE */
|
#endif /* CONFIG_PURPLE */
|
||||||
.align 4
|
.align 4
|
||||||
reset:
|
reset:
|
||||||
|
@ -235,33 +233,31 @@ reset:
|
||||||
mtc0 t0, CP0_CONFIG
|
mtc0 t0, CP0_CONFIG
|
||||||
|
|
||||||
/* Initialize $gp.
|
/* Initialize $gp.
|
||||||
*/
|
*/
|
||||||
bal 1f
|
bal 1f
|
||||||
nop
|
nop
|
||||||
.word _gp
|
.word _gp
|
||||||
1:
|
1:
|
||||||
move gp, ra
|
lw gp, 0(ra)
|
||||||
lw t1, 0(ra)
|
|
||||||
move gp, t1
|
|
||||||
|
|
||||||
#ifdef CONFIG_INCA_IP
|
#ifdef CONFIG_INCA_IP
|
||||||
/* Disable INCA-IP Watchdog.
|
/* Disable INCA-IP Watchdog.
|
||||||
*/
|
*/
|
||||||
la t9, disable_incaip_wdt
|
la t9, disable_incaip_wdt
|
||||||
jalr t9
|
jalr t9
|
||||||
nop
|
nop
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
/* Initialize any external memory.
|
/* Initialize any external memory.
|
||||||
*/
|
*/
|
||||||
la t9, lowlevel_init
|
la t9, lowlevel_init
|
||||||
jalr t9
|
jalr t9
|
||||||
nop
|
nop
|
||||||
|
|
||||||
/* Initialize caches...
|
/* Initialize caches...
|
||||||
*/
|
*/
|
||||||
la t9, mips_cache_reset
|
la t9, mips_cache_reset
|
||||||
jalr t9
|
jalr t9
|
||||||
nop
|
nop
|
||||||
|
|
||||||
/* ... and enable them.
|
/* ... and enable them.
|
||||||
|
@ -269,12 +265,11 @@ reset:
|
||||||
li t0, CONF_CM_CACHABLE_NONCOHERENT
|
li t0, CONF_CM_CACHABLE_NONCOHERENT
|
||||||
mtc0 t0, CP0_CONFIG
|
mtc0 t0, CP0_CONFIG
|
||||||
|
|
||||||
|
|
||||||
/* Set up temporary stack.
|
/* Set up temporary stack.
|
||||||
*/
|
*/
|
||||||
li a0, CFG_INIT_SP_OFFSET
|
li a0, CFG_INIT_SP_OFFSET
|
||||||
la t9, mips_cache_lock
|
la t9, mips_cache_lock
|
||||||
jalr t9
|
jalr t9
|
||||||
nop
|
nop
|
||||||
|
|
||||||
li t0, CFG_SDRAM_BASE + CFG_INIT_SP_OFFSET
|
li t0, CFG_SDRAM_BASE + CFG_INIT_SP_OFFSET
|
||||||
|
@ -284,7 +279,6 @@ reset:
|
||||||
j t9
|
j t9
|
||||||
nop
|
nop
|
||||||
|
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* void relocate_code (addr_sp, gd, addr_moni)
|
* void relocate_code (addr_sp, gd, addr_moni)
|
||||||
*
|
*
|
||||||
|
@ -298,7 +292,7 @@ reset:
|
||||||
.globl relocate_code
|
.globl relocate_code
|
||||||
.ent relocate_code
|
.ent relocate_code
|
||||||
relocate_code:
|
relocate_code:
|
||||||
move sp, a0 /* Set new stack pointer */
|
move sp, a0 /* Set new stack pointer */
|
||||||
|
|
||||||
li t0, CFG_MONITOR_BASE
|
li t0, CFG_MONITOR_BASE
|
||||||
la t3, in_ram
|
la t3, in_ram
|
||||||
|
@ -312,8 +306,8 @@ relocate_code:
|
||||||
*/
|
*/
|
||||||
move t6, gp
|
move t6, gp
|
||||||
sub gp, CFG_MONITOR_BASE
|
sub gp, CFG_MONITOR_BASE
|
||||||
add gp, a2 /* gp now adjusted */
|
add gp, a2 /* gp now adjusted */
|
||||||
sub t6, gp, t6 /* t6 <-- relocation offset */
|
sub t6, gp, t6 /* t6 <-- relocation offset */
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* t0 = source address
|
* t0 = source address
|
||||||
|
@ -329,7 +323,7 @@ relocate_code:
|
||||||
sw t3, 0(t1)
|
sw t3, 0(t1)
|
||||||
addu t0, 4
|
addu t0, 4
|
||||||
ble t0, t2, 1b
|
ble t0, t2, 1b
|
||||||
addu t1, 4 /* delay slot */
|
addu t1, 4 /* delay slot */
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
/* If caches were enabled, we would have to flush them here.
|
/* If caches were enabled, we would have to flush them here.
|
||||||
|
@ -376,7 +370,8 @@ in_ram:
|
||||||
add t2, t6
|
add t2, t6
|
||||||
|
|
||||||
sub t1, 4
|
sub t1, 4
|
||||||
1: addi t1, 4
|
1:
|
||||||
|
addi t1, 4
|
||||||
bltl t1, t2, 1b
|
bltl t1, t2, 1b
|
||||||
sw zero, 0(t1) /* delay slot */
|
sw zero, 0(t1) /* delay slot */
|
||||||
|
|
||||||
|
@ -387,11 +382,10 @@ in_ram:
|
||||||
|
|
||||||
.end relocate_code
|
.end relocate_code
|
||||||
|
|
||||||
|
|
||||||
/* Exception handlers.
|
/* Exception handlers.
|
||||||
*/
|
*/
|
||||||
romReserved:
|
romReserved:
|
||||||
b romReserved
|
b romReserved
|
||||||
|
|
||||||
romExcHandle:
|
romExcHandle:
|
||||||
b romExcHandle
|
b romExcHandle
|
||||||
|
|
Loading…
Reference in New Issue
Block a user