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fsl-ddr: Fix power-down timing settings

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1. TIMING_CFG_0[ACT_PD_EXIT] was set to 6 clocks, but
   It should be set to tXP parameter, tXP=max(3CK, 7.5ns)
2. TIMING_CFG_0[PRE_PD_EXIT] was set to 6 clocks, but
   It should be set to tXP (if MR0[A12]=1) else to tXPDLL parameter
   We are setting the mode register MR0[A12]='1'

Signed-off-by: Dave Liu <daveliu@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
This commit is contained in:
Dave Liu 2009-12-16 10:24:36 -06:00 committed by Kumar Gala
parent c4ca10f1db
commit 0a71c92c7e
1 changed files with 4 additions and 3 deletions
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7
cpu/mpc8xxx/ddr/ctrl_regs.c
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@ -188,12 +188,13 @@ static void set_timing_cfg_0(fsl_ddr_cfg_regs_t *ddr)
* The DDR3 spec has not tXARD,
* we use the tXP instead of it.
* tXP=max(3nCK, 7.5ns) for DDR3.
* we use the tXP=6
* spec has not the tAXPD, we use
* tAXPD=8, need design to confirm.
*/
act_pd_exit_mclk = 6;
pre_pd_exit_mclk = 6;
int tXP = max((get_memory_clk_period_ps() * 3), 7500); /* unit=ps */
act_pd_exit_mclk = picos_to_mclk(tXP);
/* Mode register MR0[A12] is '1' - fast exit */
pre_pd_exit_mclk = act_pd_exit_mclk;
taxpd_mclk = 8;
tmrd_mclk = 4;
#else /* CONFIG_FSL_DDR2 */