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https://github.com/brain-hackers/u-boot-brain
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phy: marvell: cp110: let the firmware configure comphy for PCIe
Replace the comphy initialization for PCIe with appropriate SMC call, so the firmware will perform appropriate comphy initialization. Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com> Signed-off-by: Ken Ma <make@marvell.com> Reviewed-by: Igal Liberman <igall@marvell.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il>
This commit is contained in:
Grzegorz Jaszczyk
Stefan Roese
parent
b24bb99df1
commit
0a1a1642aa
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@ -31,6 +31,11 @@ DECLARE_GLOBAL_DATA_PTR;
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#define COMPHY_FW_MODE_FORMAT(mode) ((mode) << 12)
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#define COMPHY_FW_FORMAT(mode, idx, speeds) \
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(((mode) << 12) | ((idx) << 8) | ((speeds) << 2))
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#define COMPHY_FW_PCIE_FORMAT(pcie_width, clk_src, mode, speeds) \
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(((pcie_width) << 18) | ((clk_src) << 17) | \
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COMPHY_FW_FORMAT(mode, 0, speeds))
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#define COMPHY_SATA_MODE 0x1
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#define COMPHY_SGMII_MODE 0x2 /* SGMII 1G */
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#define COMPHY_HS_SGMII_MODE 0x3 /* SGMII 2.5G */
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@ -112,441 +117,6 @@ static u32 polling_with_timeout(void __iomem *addr, u32 val,
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return 0;
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}
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static int comphy_pcie_power_up(u32 lane, u32 pcie_width, bool clk_src,
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bool is_end_point, void __iomem *hpipe_base,
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void __iomem *comphy_base)
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{
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u32 mask, data, ret = 1;
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void __iomem *hpipe_addr = HPIPE_ADDR(hpipe_base, lane);
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void __iomem *comphy_addr = COMPHY_ADDR(comphy_base, lane);
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void __iomem *addr;
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u32 pcie_clk = 0; /* set input by default */
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debug_enter();
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/*
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* ToDo:
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* Add SAR (Sample-At-Reset) configuration for the PCIe clock
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* direction. SAR code is currently not ported from Marvell
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* U-Boot to mainline version.
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*
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* SerDes Lane 4/5 got the PCIe ref-clock #1,
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* and SerDes Lane 0 got PCIe ref-clock #0
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*/
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debug("PCIe clock = %x\n", pcie_clk);
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debug("PCIe RC = %d\n", !is_end_point);
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debug("PCIe width = %d\n", pcie_width);
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/* enable PCIe by4 and by2 */
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if (lane == 0) {
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if (pcie_width == 4) {
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reg_set(comphy_base + COMMON_PHY_SD_CTRL1,
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0x1 << COMMON_PHY_SD_CTRL1_PCIE_X4_EN_OFFSET,
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COMMON_PHY_SD_CTRL1_PCIE_X4_EN_MASK);
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} else if (pcie_width == 2) {
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reg_set(comphy_base + COMMON_PHY_SD_CTRL1,
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0x1 << COMMON_PHY_SD_CTRL1_PCIE_X2_EN_OFFSET,
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COMMON_PHY_SD_CTRL1_PCIE_X2_EN_MASK);
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}
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}
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/*
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* If PCIe clock is output and clock source from SerDes lane 5,
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* we need to configure the clock-source MUX.
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* By default, the clock source is from lane 4
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*/
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if (pcie_clk && clk_src && (lane == 5)) {
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reg_set((void __iomem *)DFX_DEV_GEN_CTRL12,
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0x3 << DFX_DEV_GEN_PCIE_CLK_SRC_OFFSET,
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DFX_DEV_GEN_PCIE_CLK_SRC_MASK);
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}
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debug("stage: RFU configurations - hard reset comphy\n");
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/* RFU configurations - hard reset comphy */
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mask = COMMON_PHY_CFG1_PWR_UP_MASK;
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data = 0x1 << COMMON_PHY_CFG1_PWR_UP_OFFSET;
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mask |= COMMON_PHY_CFG1_PIPE_SELECT_MASK;
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data |= 0x1 << COMMON_PHY_CFG1_PIPE_SELECT_OFFSET;
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mask |= COMMON_PHY_CFG1_PWR_ON_RESET_MASK;
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data |= 0x0 << COMMON_PHY_CFG1_PWR_ON_RESET_OFFSET;
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mask |= COMMON_PHY_CFG1_CORE_RSTN_MASK;
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data |= 0x0 << COMMON_PHY_CFG1_CORE_RSTN_OFFSET;
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mask |= COMMON_PHY_PHY_MODE_MASK;
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data |= 0x0 << COMMON_PHY_PHY_MODE_OFFSET;
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reg_set(comphy_addr + COMMON_PHY_CFG1_REG, data, mask);
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/* release from hard reset */
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mask = COMMON_PHY_CFG1_PWR_ON_RESET_MASK;
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data = 0x1 << COMMON_PHY_CFG1_PWR_ON_RESET_OFFSET;
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mask |= COMMON_PHY_CFG1_CORE_RSTN_MASK;
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data |= 0x1 << COMMON_PHY_CFG1_CORE_RSTN_OFFSET;
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reg_set(comphy_addr + COMMON_PHY_CFG1_REG, data, mask);
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/* Wait 1ms - until band gap and ref clock ready */
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mdelay(1);
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/* Start comphy Configuration */
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debug("stage: Comphy configuration\n");
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/* Set PIPE soft reset */
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mask = HPIPE_RST_CLK_CTRL_PIPE_RST_MASK;
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data = 0x1 << HPIPE_RST_CLK_CTRL_PIPE_RST_OFFSET;
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/* Set PHY datapath width mode for V0 */
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mask |= HPIPE_RST_CLK_CTRL_FIXED_PCLK_MASK;
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data |= 0x1 << HPIPE_RST_CLK_CTRL_FIXED_PCLK_OFFSET;
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/* Set Data bus width USB mode for V0 */
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mask |= HPIPE_RST_CLK_CTRL_PIPE_WIDTH_MASK;
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data |= 0x0 << HPIPE_RST_CLK_CTRL_PIPE_WIDTH_OFFSET;
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/* Set CORE_CLK output frequency for 250Mhz */
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mask |= HPIPE_RST_CLK_CTRL_CORE_FREQ_SEL_MASK;
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data |= 0x0 << HPIPE_RST_CLK_CTRL_CORE_FREQ_SEL_OFFSET;
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reg_set(hpipe_addr + HPIPE_RST_CLK_CTRL_REG, data, mask);
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/* Set PLL ready delay for 0x2 */
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data = 0x2 << HPIPE_CLK_SRC_LO_PLL_RDY_DL_OFFSET;
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mask = HPIPE_CLK_SRC_LO_PLL_RDY_DL_MASK;
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if (pcie_width != 1) {
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data |= 0x1 << HPIPE_CLK_SRC_LO_BUNDLE_PERIOD_SEL_OFFSET;
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mask |= HPIPE_CLK_SRC_LO_BUNDLE_PERIOD_SEL_MASK;
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data |= 0x1 << HPIPE_CLK_SRC_LO_BUNDLE_PERIOD_SCALE_OFFSET;
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mask |= HPIPE_CLK_SRC_LO_BUNDLE_PERIOD_SCALE_MASK;
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}
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reg_set(hpipe_addr + HPIPE_CLK_SRC_LO_REG, data, mask);
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/* Set PIPE mode interface to PCIe3 - 0x1 & set lane order */
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data = 0x1 << HPIPE_CLK_SRC_HI_MODE_PIPE_OFFSET;
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mask = HPIPE_CLK_SRC_HI_MODE_PIPE_MASK;
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if (pcie_width != 1) {
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mask |= HPIPE_CLK_SRC_HI_LANE_STRT_MASK;
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mask |= HPIPE_CLK_SRC_HI_LANE_MASTER_MASK;
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mask |= HPIPE_CLK_SRC_HI_LANE_BREAK_MASK;
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if (lane == 0) {
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data |= 0x1 << HPIPE_CLK_SRC_HI_LANE_STRT_OFFSET;
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data |= 0x1 << HPIPE_CLK_SRC_HI_LANE_MASTER_OFFSET;
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} else if (lane == (pcie_width - 1)) {
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data |= 0x1 << HPIPE_CLK_SRC_HI_LANE_BREAK_OFFSET;
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}
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}
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reg_set(hpipe_addr + HPIPE_CLK_SRC_HI_REG, data, mask);
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/* Config update polarity equalization */
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reg_set(hpipe_addr + HPIPE_LANE_EQ_CFG1_REG,
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0x1 << HPIPE_CFG_UPDATE_POLARITY_OFFSET,
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HPIPE_CFG_UPDATE_POLARITY_MASK);
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/* Set PIPE version 4 to mode enable */
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reg_set(hpipe_addr + HPIPE_DFE_CTRL_28_REG,
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0x1 << HPIPE_DFE_CTRL_28_PIPE4_OFFSET,
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HPIPE_DFE_CTRL_28_PIPE4_MASK);
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/* TODO: check if pcie clock is output/input - for bringup use input*/
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/* Enable PIN clock 100M_125M */
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mask = 0;
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data = 0;
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/* Only if clock is output, configure the clock-source mux */
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if (pcie_clk) {
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mask |= HPIPE_MISC_CLK100M_125M_MASK;
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data |= 0x1 << HPIPE_MISC_CLK100M_125M_OFFSET;
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}
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/*
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* Set PIN_TXDCLK_2X Clock Frequency Selection for outputs 500MHz
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* clock
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*/
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mask |= HPIPE_MISC_TXDCLK_2X_MASK;
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data |= 0x0 << HPIPE_MISC_TXDCLK_2X_OFFSET;
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/* Enable 500MHz Clock */
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mask |= HPIPE_MISC_CLK500_EN_MASK;
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data |= 0x1 << HPIPE_MISC_CLK500_EN_OFFSET;
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if (pcie_clk) { /* output */
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/* Set reference clock comes from group 1 */
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mask |= HPIPE_MISC_REFCLK_SEL_MASK;
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data |= 0x0 << HPIPE_MISC_REFCLK_SEL_OFFSET;
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} else {
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/* Set reference clock comes from group 2 */
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mask |= HPIPE_MISC_REFCLK_SEL_MASK;
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data |= 0x1 << HPIPE_MISC_REFCLK_SEL_OFFSET;
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}
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mask |= HPIPE_MISC_ICP_FORCE_MASK;
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data |= 0x1 << HPIPE_MISC_ICP_FORCE_OFFSET;
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reg_set(hpipe_addr + HPIPE_MISC_REG, data, mask);
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if (pcie_clk) { /* output */
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/* Set reference frequcency select - 0x2 for 25MHz*/
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mask = HPIPE_PWR_PLL_REF_FREQ_MASK;
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data = 0x2 << HPIPE_PWR_PLL_REF_FREQ_OFFSET;
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} else {
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/* Set reference frequcency select - 0x0 for 100MHz*/
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mask = HPIPE_PWR_PLL_REF_FREQ_MASK;
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data = 0x0 << HPIPE_PWR_PLL_REF_FREQ_OFFSET;
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}
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/* Set PHY mode to PCIe */
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mask |= HPIPE_PWR_PLL_PHY_MODE_MASK;
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data |= 0x3 << HPIPE_PWR_PLL_PHY_MODE_OFFSET;
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reg_set(hpipe_addr + HPIPE_PWR_PLL_REG, data, mask);
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/* ref clock alignment */
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if (pcie_width != 1) {
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mask = HPIPE_LANE_ALIGN_OFF_MASK;
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data = 0x0 << HPIPE_LANE_ALIGN_OFF_OFFSET;
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reg_set(hpipe_addr + HPIPE_LANE_ALIGN_REG, data, mask);
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}
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/*
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* Set the amount of time spent in the LoZ state - set for 0x7 only if
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* the PCIe clock is output
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*/
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if (pcie_clk) {
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reg_set(hpipe_addr + HPIPE_GLOBAL_PM_CTRL,
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0x7 << HPIPE_GLOBAL_PM_RXDLOZ_WAIT_OFFSET,
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HPIPE_GLOBAL_PM_RXDLOZ_WAIT_MASK);
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}
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/* Set Maximal PHY Generation Setting(8Gbps) */
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mask = HPIPE_INTERFACE_GEN_MAX_MASK;
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data = 0x2 << HPIPE_INTERFACE_GEN_MAX_OFFSET;
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/* Bypass frame detection and sync detection for RX DATA */
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mask = HPIPE_INTERFACE_DET_BYPASS_MASK;
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data = 0x1 << HPIPE_INTERFACE_DET_BYPASS_OFFSET;
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/* Set Link Train Mode (Tx training control pins are used) */
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mask |= HPIPE_INTERFACE_LINK_TRAIN_MASK;
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data |= 0x1 << HPIPE_INTERFACE_LINK_TRAIN_OFFSET;
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reg_set(hpipe_addr + HPIPE_INTERFACE_REG, data, mask);
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/* Set Idle_sync enable */
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mask = HPIPE_PCIE_IDLE_SYNC_MASK;
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data = 0x1 << HPIPE_PCIE_IDLE_SYNC_OFFSET;
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/* Select bits for PCIE Gen3(32bit) */
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mask |= HPIPE_PCIE_SEL_BITS_MASK;
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data |= 0x2 << HPIPE_PCIE_SEL_BITS_OFFSET;
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reg_set(hpipe_addr + HPIPE_PCIE_REG0, data, mask);
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/* Enable Tx_adapt_g1 */
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mask = HPIPE_TX_TRAIN_CTRL_G1_MASK;
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data = 0x1 << HPIPE_TX_TRAIN_CTRL_G1_OFFSET;
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/* Enable Tx_adapt_gn1 */
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mask |= HPIPE_TX_TRAIN_CTRL_GN1_MASK;
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data |= 0x1 << HPIPE_TX_TRAIN_CTRL_GN1_OFFSET;
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/* Disable Tx_adapt_g0 */
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mask |= HPIPE_TX_TRAIN_CTRL_G0_MASK;
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data |= 0x0 << HPIPE_TX_TRAIN_CTRL_G0_OFFSET;
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reg_set(hpipe_addr + HPIPE_TX_TRAIN_CTRL_REG, data, mask);
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/* Set reg_tx_train_chk_init */
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mask = HPIPE_TX_TRAIN_CHK_INIT_MASK;
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data = 0x0 << HPIPE_TX_TRAIN_CHK_INIT_OFFSET;
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/* Enable TX_COE_FM_PIN_PCIE3_EN */
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mask |= HPIPE_TX_TRAIN_COE_FM_PIN_PCIE3_MASK;
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data |= 0x1 << HPIPE_TX_TRAIN_COE_FM_PIN_PCIE3_OFFSET;
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reg_set(hpipe_addr + HPIPE_TX_TRAIN_REG, data, mask);
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debug("stage: TRx training parameters\n");
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/* Set Preset sweep configurations */
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mask = HPIPE_TX_TX_STATUS_CHECK_MODE_MASK;
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data = 0x1 << HPIPE_TX_STATUS_CHECK_MODE_OFFSET;
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mask |= HPIPE_TX_NUM_OF_PRESET_MASK;
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data |= 0x7 << HPIPE_TX_NUM_OF_PRESET_OFFSET;
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mask |= HPIPE_TX_SWEEP_PRESET_EN_MASK;
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data |= 0x1 << HPIPE_TX_SWEEP_PRESET_EN_OFFSET;
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reg_set(hpipe_addr + HPIPE_TX_TRAIN_CTRL_11_REG, data, mask);
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/* Tx train start configuration */
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mask = HPIPE_TX_TRAIN_START_SQ_EN_MASK;
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data = 0x1 << HPIPE_TX_TRAIN_START_SQ_EN_OFFSET;
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mask |= HPIPE_TX_TRAIN_START_FRM_DET_EN_MASK;
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data |= 0x0 << HPIPE_TX_TRAIN_START_FRM_DET_EN_OFFSET;
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mask |= HPIPE_TX_TRAIN_START_FRM_LOCK_EN_MASK;
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data |= 0x0 << HPIPE_TX_TRAIN_START_FRM_LOCK_EN_OFFSET;
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mask |= HPIPE_TX_TRAIN_WAIT_TIME_EN_MASK;
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data |= 0x1 << HPIPE_TX_TRAIN_WAIT_TIME_EN_OFFSET;
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reg_set(hpipe_addr + HPIPE_TX_TRAIN_CTRL_5_REG, data, mask);
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/* Enable Tx train P2P */
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mask = HPIPE_TX_TRAIN_P2P_HOLD_MASK;
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data = 0x1 << HPIPE_TX_TRAIN_P2P_HOLD_OFFSET;
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reg_set(hpipe_addr + HPIPE_TX_TRAIN_CTRL_0_REG, data, mask);
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/* Configure Tx train timeout */
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mask = HPIPE_TRX_TRAIN_TIMER_MASK;
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data = 0x17 << HPIPE_TRX_TRAIN_TIMER_OFFSET;
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reg_set(hpipe_addr + HPIPE_TX_TRAIN_CTRL_4_REG, data, mask);
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/* Disable G0/G1/GN1 adaptation */
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mask = HPIPE_TX_TRAIN_CTRL_G1_MASK | HPIPE_TX_TRAIN_CTRL_GN1_MASK
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| HPIPE_TX_TRAIN_CTRL_G0_OFFSET;
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data = 0;
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reg_set(hpipe_addr + HPIPE_TX_TRAIN_CTRL_REG, data, mask);
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/* Disable DTL frequency loop */
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mask = HPIPE_PWR_CTR_DTL_FLOOP_EN_MASK;
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data = 0x0 << HPIPE_PWR_CTR_DTL_FLOOP_EN_OFFSET;
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reg_set(hpipe_addr + HPIPE_PWR_CTR_DTL_REG, data, mask);
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/* Configure G3 DFE */
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mask = HPIPE_G3_DFE_RES_MASK;
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data = 0x3 << HPIPE_G3_DFE_RES_OFFSET;
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reg_set(hpipe_addr + HPIPE_G3_SETTING_4_REG, data, mask);
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/* Use TX/RX training result for DFE */
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mask = HPIPE_DFE_RES_FORCE_MASK;
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data = 0x0 << HPIPE_DFE_RES_FORCE_OFFSET;
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reg_set(hpipe_addr + HPIPE_DFE_REG0, data, mask);
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/* Configure initial and final coefficient value for receiver */
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mask = HPIPE_G3_SET_1_G3_RX_SELMUPI_MASK;
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data = 0x1 << HPIPE_G3_SET_1_G3_RX_SELMUPI_OFFSET;
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mask |= HPIPE_G3_SET_1_G3_RX_SELMUPF_MASK;
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data |= 0x1 << HPIPE_G3_SET_1_G3_RX_SELMUPF_OFFSET;
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mask |= HPIPE_G3_SET_1_G3_SAMPLER_INPAIRX2_EN_MASK;
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data |= 0x0 << HPIPE_G3_SET_1_G3_SAMPLER_INPAIRX2_EN_OFFSET;
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reg_set(hpipe_addr + HPIPE_G3_SET_1_REG, data, mask);
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/* Trigger sampler enable pulse */
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mask = HPIPE_SMAPLER_MASK;
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data = 0x1 << HPIPE_SMAPLER_OFFSET;
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reg_set(hpipe_addr + HPIPE_SAMPLER_N_PROC_CALIB_CTRL_REG, data, mask);
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udelay(5);
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reg_set(hpipe_addr + HPIPE_SAMPLER_N_PROC_CALIB_CTRL_REG, 0, mask);
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/* FFE resistor tuning for different bandwidth */
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mask = HPIPE_G3_FFE_DEG_RES_LEVEL_MASK;
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data = 0x1 << HPIPE_G3_FFE_DEG_RES_LEVEL_OFFSET;
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mask |= HPIPE_G3_FFE_LOAD_RES_LEVEL_MASK;
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data |= 0x3 << HPIPE_G3_FFE_LOAD_RES_LEVEL_OFFSET;
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reg_set(hpipe_addr + HPIPE_G3_SETTING_3_REG, data, mask);
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/* Pattern lock lost timeout disable */
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mask = HPIPE_PATTERN_LOCK_LOST_TIMEOUT_EN_MASK;
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data = 0x0 << HPIPE_PATTERN_LOCK_LOST_TIMEOUT_EN_OFFSET;
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reg_set(hpipe_addr + HPIPE_FRAME_DETECT_CTRL_3_REG, data, mask);
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/* Configure DFE adaptations */
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mask = HPIPE_CDR_MAX_DFE_ADAPT_1_MASK;
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data = 0x1 << HPIPE_CDR_MAX_DFE_ADAPT_1_OFFSET;
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mask |= HPIPE_CDR_MAX_DFE_ADAPT_0_MASK;
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data |= 0x0 << HPIPE_CDR_MAX_DFE_ADAPT_0_OFFSET;
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mask |= HPIPE_CDR_RX_MAX_DFE_ADAPT_1_MASK;
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data |= 0x0 << HPIPE_CDR_RX_MAX_DFE_ADAPT_1_OFFSET;
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reg_set(hpipe_addr + HPIPE_CDR_CONTROL_REG, data, mask);
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mask = HPIPE_DFE_TX_MAX_DFE_ADAPT_MASK;
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data = 0x0 << HPIPE_DFE_TX_MAX_DFE_ADAPT_OFFSET;
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reg_set(hpipe_addr + HPIPE_DFE_CONTROL_REG, data, mask);
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/* Genration 2 setting 1*/
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mask = HPIPE_G2_SET_1_G2_RX_SELMUPI_MASK;
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data = 0x0 << HPIPE_G2_SET_1_G2_RX_SELMUPI_OFFSET;
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mask |= HPIPE_G2_SET_1_G2_RX_SELMUPP_MASK;
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data |= 0x1 << HPIPE_G2_SET_1_G2_RX_SELMUPP_OFFSET;
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mask |= HPIPE_G2_SET_1_G2_RX_SELMUFI_MASK;
|
||||
data |= 0x0 << HPIPE_G2_SET_1_G2_RX_SELMUFI_OFFSET;
|
||||
reg_set(hpipe_addr + HPIPE_G2_SET_1_REG, data, mask);
|
||||
|
||||
/* DFE enable */
|
||||
mask = HPIPE_G2_DFE_RES_MASK;
|
||||
data = 0x3 << HPIPE_G2_DFE_RES_OFFSET;
|
||||
reg_set(hpipe_addr + HPIPE_G2_SETTINGS_4_REG, data, mask);
|
||||
|
||||
/* Configure DFE Resolution */
|
||||
mask = HPIPE_LANE_CFG4_DFE_EN_SEL_MASK;
|
||||
data = 0x1 << HPIPE_LANE_CFG4_DFE_EN_SEL_OFFSET;
|
||||
reg_set(hpipe_addr + HPIPE_LANE_CFG4_REG, data, mask);
|
||||
|
||||
/* VDD calibration control */
|
||||
mask = HPIPE_EXT_SELLV_RXSAMPL_MASK;
|
||||
data = 0x16 << HPIPE_EXT_SELLV_RXSAMPL_OFFSET;
|
||||
reg_set(hpipe_addr + HPIPE_VDD_CAL_CTRL_REG, data, mask);
|
||||
|
||||
/* Set PLL Charge-pump Current Control */
|
||||
mask = HPIPE_G3_SETTING_5_G3_ICP_MASK;
|
||||
data = 0x4 << HPIPE_G3_SETTING_5_G3_ICP_OFFSET;
|
||||
reg_set(hpipe_addr + HPIPE_G3_SETTING_5_REG, data, mask);
|
||||
|
||||
/* Set lane rqualization remote setting */
|
||||
mask = HPIPE_LANE_CFG_FOM_DIRN_OVERRIDE_MASK;
|
||||
data = 0x1 << HPIPE_LANE_CFG_FOM_DIRN_OVERRIDE_OFFSET;
|
||||
mask |= HPIPE_LANE_CFG_FOM_ONLY_MODE_MASK;
|
||||
data |= 0x1 << HPIPE_LANE_CFG_FOM_ONLY_MODE_OFFFSET;
|
||||
mask |= HPIPE_LANE_CFG_FOM_PRESET_VECTOR_MASK;
|
||||
data |= 0x2 << HPIPE_LANE_CFG_FOM_PRESET_VECTOR_OFFSET;
|
||||
reg_set(hpipe_addr + HPIPE_LANE_EQ_REMOTE_SETTING_REG, data, mask);
|
||||
|
||||
if (!is_end_point) {
|
||||
/* Set phy in root complex mode */
|
||||
mask = HPIPE_CFG_PHY_RC_EP_MASK;
|
||||
data = 0x1 << HPIPE_CFG_PHY_RC_EP_OFFSET;
|
||||
reg_set(hpipe_addr + HPIPE_LANE_EQU_CONFIG_0_REG, data, mask);
|
||||
}
|
||||
|
||||
debug("stage: Comphy power up\n");
|
||||
|
||||
/*
|
||||
* For PCIe by4 or by2 - release from reset only after finish to
|
||||
* configure all lanes
|
||||
*/
|
||||
if ((pcie_width == 1) || (lane == (pcie_width - 1))) {
|
||||
u32 i, start_lane, end_lane;
|
||||
|
||||
if (pcie_width != 1) {
|
||||
/* allows writing to all lanes in one write */
|
||||
reg_set(comphy_base + COMMON_PHY_SD_CTRL1,
|
||||
0x0 <<
|
||||
COMMON_PHY_SD_CTRL1_COMPHY_0_4_PORT_OFFSET,
|
||||
COMMON_PHY_SD_CTRL1_COMPHY_0_4_PORT_MASK);
|
||||
start_lane = 0;
|
||||
end_lane = pcie_width;
|
||||
|
||||
/*
|
||||
* Release from PIPE soft reset
|
||||
* for PCIe by4 or by2 - release from soft reset
|
||||
* all lanes - can't use read modify write
|
||||
*/
|
||||
reg_set(HPIPE_ADDR(hpipe_base, 0) +
|
||||
HPIPE_RST_CLK_CTRL_REG, 0x24, 0xffffffff);
|
||||
} else {
|
||||
start_lane = lane;
|
||||
end_lane = lane + 1;
|
||||
|
||||
/*
|
||||
* Release from PIPE soft reset
|
||||
* for PCIe by4 or by2 - release from soft reset
|
||||
* all lanes
|
||||
*/
|
||||
reg_set(hpipe_addr + HPIPE_RST_CLK_CTRL_REG,
|
||||
0x0 << HPIPE_RST_CLK_CTRL_PIPE_RST_OFFSET,
|
||||
HPIPE_RST_CLK_CTRL_PIPE_RST_MASK);
|
||||
}
|
||||
|
||||
|
||||
if (pcie_width != 1) {
|
||||
/* disable writing to all lanes with one write */
|
||||
reg_set(comphy_base + COMMON_PHY_SD_CTRL1,
|
||||
0x3210 <<
|
||||
COMMON_PHY_SD_CTRL1_COMPHY_0_4_PORT_OFFSET,
|
||||
COMMON_PHY_SD_CTRL1_COMPHY_0_4_PORT_MASK);
|
||||
}
|
||||
|
||||
debug("stage: Check PLL\n");
|
||||
/* Read lane status */
|
||||
for (i = start_lane; i < end_lane; i++) {
|
||||
addr = HPIPE_ADDR(hpipe_base, i) +
|
||||
HPIPE_LANE_STATUS1_REG;
|
||||
data = HPIPE_LANE_STATUS1_PCLK_EN_MASK;
|
||||
mask = data;
|
||||
data = polling_with_timeout(addr, data, mask, 15000);
|
||||
if (data != 0) {
|
||||
debug("Read from reg = %p - value = 0x%x\n",
|
||||
hpipe_addr + HPIPE_LANE_STATUS1_REG,
|
||||
data);
|
||||
pr_err("HPIPE_LANE_STATUS1_PCLK_EN_MASK is 0\n");
|
||||
ret = 0;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
debug_exit();
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int comphy_usb3_power_up(u32 lane, void __iomem *hpipe_base,
|
||||
void __iomem *comphy_base)
|
||||
{
|
||||
|
|
@ -1346,10 +916,13 @@ int comphy_cp110_init(struct chip_serdes_phy_config *ptr_chip_cfg,
|
|||
case PHY_TYPE_PEX1:
|
||||
case PHY_TYPE_PEX2:
|
||||
case PHY_TYPE_PEX3:
|
||||
ret = comphy_pcie_power_up(
|
||||
lane, pcie_width, ptr_comphy_map->clk_src,
|
||||
serdes_map->end_point,
|
||||
hpipe_base_addr, comphy_base_addr);
|
||||
mode = COMPHY_FW_PCIE_FORMAT(pcie_width,
|
||||
ptr_comphy_map->clk_src,
|
||||
COMPHY_PCIE_MODE,
|
||||
ptr_comphy_map->speed);
|
||||
ret = comphy_smc(MV_SIP_COMPHY_POWER_ON,
|
||||
ptr_chip_cfg->comphy_base_addr, lane,
|
||||
mode);
|
||||
break;
|
||||
case PHY_TYPE_SATA0:
|
||||
case PHY_TYPE_SATA1:
|
||||
|
|
|
|||
Loading…
Reference in New Issue
Block a user