mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-10-05 02:50:44 +09:00
Blackfin: use on-chip syscontrol() rom function when available
Newer Blackfin's have an on-chip rom with a syscontrol() function that needs to be used to properly program the memory and voltage settings as it will include (possibly critical) factory tested bias values. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
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@ -216,7 +216,7 @@ static inline void serial_putc(char c)
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# define CONFIG_VR_CTL_VAL (CONFIG_VR_CTL_CLKBUF | CONFIG_VR_CTL_VLEV | CONFIG_VR_CTL_FREQ)
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#endif
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__attribute__((saveall))
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BOOTROM_CALLED_FUNC_ATTR
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void initcode(ADI_BOOT_DATA *bootstruct)
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{
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uint32_t old_baud = serial_init();
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@ -267,34 +267,50 @@ void initcode(ADI_BOOT_DATA *bootstruct)
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bfin_write_SIC_IWR(1);
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#endif
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serial_putc('L');
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bfin_write_PLL_LOCKCNT(CONFIG_PLL_LOCKCNT_VAL);
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serial_putc('A');
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/* Only reprogram when needed to avoid triggering unnecessary
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* PLL relock sequences.
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/* With newer bootroms, we use the helper function to set up
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* the memory controller. Older bootroms lacks such helpers
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* so we do it ourselves.
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*/
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if (bfin_read_VR_CTL() != CONFIG_VR_CTL_VAL) {
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serial_putc('!');
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bfin_write_VR_CTL(CONFIG_VR_CTL_VAL);
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asm("idle;");
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}
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if (BOOTROM_CAPS_SYSCONTROL) {
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serial_putc('S');
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serial_putc('C');
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ADI_SYSCTRL_VALUES memory_settings;
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memory_settings.uwVrCtl = CONFIG_VR_CTL_VAL;
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memory_settings.uwPllCtl = CONFIG_PLL_CTL_VAL;
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memory_settings.uwPllDiv = CONFIG_PLL_DIV_VAL;
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memory_settings.uwPllLockCnt = CONFIG_PLL_LOCKCNT_VAL;
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syscontrol(SYSCTRL_WRITE | SYSCTRL_VRCTL | SYSCTRL_PLLCTL | SYSCTRL_PLLDIV | SYSCTRL_LOCKCNT |
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(CONFIG_VR_CTL_VAL & FREQ_MASK ? SYSCTRL_INTVOLTAGE : SYSCTRL_EXTVOLTAGE), &memory_settings, NULL);
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} else {
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serial_putc('L');
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bfin_write_PLL_DIV(CONFIG_PLL_DIV_VAL);
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bfin_write_PLL_LOCKCNT(CONFIG_PLL_LOCKCNT_VAL);
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serial_putc('K');
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serial_putc('A');
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/* Only reprogram when needed to avoid triggering unnecessary
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* PLL relock sequences.
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*/
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if (bfin_read_PLL_CTL() != CONFIG_PLL_CTL_VAL) {
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serial_putc('!');
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bfin_write_PLL_CTL(CONFIG_PLL_CTL_VAL);
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asm("idle;");
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/* Only reprogram when needed to avoid triggering unnecessary
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* PLL relock sequences.
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*/
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if (bfin_read_VR_CTL() != CONFIG_VR_CTL_VAL) {
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serial_putc('!');
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bfin_write_VR_CTL(CONFIG_VR_CTL_VAL);
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asm("idle;");
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}
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serial_putc('C');
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bfin_write_PLL_DIV(CONFIG_PLL_DIV_VAL);
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serial_putc('K');
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/* Only reprogram when needed to avoid triggering unnecessary
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* PLL relock sequences.
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*/
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if (bfin_read_PLL_CTL() != CONFIG_PLL_CTL_VAL) {
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serial_putc('!');
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bfin_write_PLL_CTL(CONFIG_PLL_CTL_VAL);
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asm("idle;");
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}
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}
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/* Since we've changed the SCLK above, we may need to update
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