brain-hackers_pepepper-mirror/u-boot-brain
1
0
Fork 0
mirror of https://github.com/brain-hackers/u-boot-brain synced 2024-06-09 23:36:03 +09:00
Code Issues Projects Releases Wiki Activity

arm nomadik: use 1000 as HZ value and rewrite timer code

Browse Source 
This sets CONFIG_SYS_HZ to 1000 as required, and completely rewrites
timer code, which is now both correct and much smaller.  Unused
functions like udelay_masked() have been removed as no driver uses
them, even the ones that are not currently active for this board.
mtu.h is copied literally from the kernel sources.

Signed-off-by: Alessandro Rubini <rubini@unipv.it>
Acked-by: Andrea Gallo <andrea.gallo@stericsson.com>
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
This commit is contained in:
Alessandro Rubini 2009-06-29 10:52:37 +02:00 committed by Jean-Christophe PLAGNIOL-VILLARD
parent f7aa59b29a
commit 095a460b49
3 changed files with 94 additions and 140 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

166
cpu/arm926ejs/nomadik/timer.c
View File

@ -1,20 +1,5 @@
/*
* (C) Copyright 2003
* Texas Instruments <www.ti.com>
*
* (C) Copyright 2002
* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
* Marius Groeger <mgroeger@sysgo.de>
*
* (C) Copyright 2002
* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
* Alex Zuepke <azu@sysgo.de>
*
* (C) Copyright 2002-2004
* Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
*
* (C) Copyright 2004
* Philippe Robin, ARM Ltd. <philippe.robin@arm.com>
* (C) Copyright 2009 Alessandro Rubini
*
* See file CREDITS for list of people who contributed to this
* project.
@ -37,146 +22,49 @@
#include <common.h>
#include <asm/io.h>
#include <asm/arch/mtu.h>
#define TIMER_LOAD_VAL 0xffffffff
/*
* The timer is a decrementer, we'll left it free running at 2.4MHz.
* We have 2.4 ticks per microsecond and an overflow in almost 30min
*/
#define TIMER_CLOCK (24 * 100 * 1000)
#define COUNT_TO_USEC(x) ((x) * 5 / 12) /* overflows at 6min */
#define USEC_TO_COUNT(x) ((x) * 12 / 5) /* overflows at 6min */
#define TICKS_PER_HZ (TIMER_CLOCK / CONFIG_SYS_HZ)
#define TICKS_TO_HZ(x) ((x) / TICKS_PER_HZ)
/* macro to read the 32 bit timer */
#define READ_TIMER readl(CONFIG_SYS_TIMERBASE + 20)
/* macro to read the 32 bit timer: since it decrements, we invert read value */
#define READ_TIMER() (~readl(CONFIG_SYS_TIMERBASE + MTU_VAL(0)))
static ulong timestamp;
static ulong lastdec;
/* nothing really to do with interrupts, just starts up a counter. */
/* Configure a free-running, auto-wrap counter with no prescaler */
int timer_init(void)
{
/* Load timer with initial value */
writel(TIMER_LOAD_VAL, CONFIG_SYS_TIMERBASE + 16);
/*
* Set timer to be enabled, free-running, no interrupts, 256 divider,
* 32-bit, wrap-mode
*/
writel(0x8a, CONFIG_SYS_TIMERBASE + 24);
/* init the timestamp and lastdec value */
reset_timer_masked();
writel(MTU_CRn_ENA | MTU_CRn_PRESCALE_1 | MTU_CRn_32BITS,
CONFIG_SYS_TIMERBASE + MTU_CR(0));
reset_timer();
return 0;
}
/*
* timer without interrupts
*/
/* Restart counting from 0 */
void reset_timer(void)
{
reset_timer_masked();
writel(0, CONFIG_SYS_TIMERBASE + MTU_LR(0)); /* Immediate effect */
}
/* Return how many HZ passed since "base" */
ulong get_timer(ulong base)
{
return get_timer_masked() - base;
return TICKS_TO_HZ(READ_TIMER()) - base;
}
void set_timer(ulong t)
{
timestamp = t;
}
/* delay x useconds AND perserve advance timstamp value */
/* Delay x useconds */
void udelay(unsigned long usec)
{
ulong tmo, tmp;
ulong ini, end;
if (usec >= 1000) {
/* if "big" number, spread normalization to seconds */
tmo = usec / 1000; /* start to normalize */
tmo *= CONFIG_SYS_HZ; /* find number of "ticks" */
tmo /= 1000; /* finish normalize. */
} else {
/* small number, don't kill it prior to HZ multiply */
tmo = usec * CONFIG_SYS_HZ;
tmo /= (1000 * 1000);
}
tmp = get_timer(0); /* get current timestamp */
if ((tmo + tmp + 1) < tmp) /* will roll time stamp? */
reset_timer_masked(); /* reset to 0, set lastdec value */
else
tmo += tmp;
while (get_timer_masked() < tmo)
/* nothing */ ;
}
void reset_timer_masked(void)
{
/* reset time */
lastdec = READ_TIMER; /* capure current decrementer value time */
timestamp = 0; /* start "advancing" time stamp from 0 */
}
ulong get_timer_masked(void)
{
ulong now = READ_TIMER; /* current tick value */
if (lastdec >= now) { /* normal mode (non roll) */
/* move stamp fordward */
timestamp += lastdec - now;
} else {
/*
* An overflow is expected.
* nts = ts + ld + (TLV - now)
* ts=old stamp, ld=time that passed before passing through -1
* (TLV-now) amount of time after passing though -1
* nts = new "advancing time stamp"...it could also roll
*/
timestamp += lastdec + TIMER_LOAD_VAL - now;
}
lastdec = now;
return timestamp;
}
/* waits specified delay value and resets timestamp */
void udelay_masked(unsigned long usec)
{
ulong tmo;
if (usec >= 1000) {
/* if "big" number, spread normalization to seconds */
tmo = usec / 1000; /* start to normalize */
tmo *= CONFIG_SYS_HZ; /* find number of "ticks" */
tmo /= 1000; /* finish normalize. */
} else {
/* else small number, don't kill it prior to HZ multiply */
tmo = usec * CONFIG_SYS_HZ;
tmo /= (1000*1000);
}
reset_timer_masked();
/* set "advancing" timestamp to 0, set lastdec vaule */
while (get_timer_masked() < tmo)
/* nothing */ ;
}
/*
* This function is derived from PowerPC code (read timebase as long long).
* On ARM it just returns the timer value.
*/
unsigned long long get_ticks(void)
{
return get_timer(0);
}
/*
* This function is derived from PowerPC code (timebase clock frequency).
* On ARM it returns the number of timer ticks per second.
*/
ulong get_tbclk(void)
{
ulong tbclk;
tbclk = CONFIG_SYS_HZ;
return tbclk;
ini = READ_TIMER();
end = ini + USEC_TO_COUNT(usec);
while ((signed)(end - READ_TIMER()) > 0)
;
}

66
include/asm-arm/arch-nomadik/mtu.h Normal file
View File

@ -0,0 +1,66 @@
/*
* (C) Copyright 2009 Alessandro Rubini
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef __ASM_ARCH_MTU_H
#define __ASM_ARCH_MTU_H
/*
* The MTU device hosts four different counters, with 4 set of
* registers. These are register names.
*/
#define MTU_IMSC 0x00 /* Interrupt mask set/clear */
#define MTU_RIS 0x04 /* Raw interrupt status */
#define MTU_MIS 0x08 /* Masked interrupt status */
#define MTU_ICR 0x0C /* Interrupt clear register */
/* per-timer registers take 0..3 as argument */
#define MTU_LR(x) (0x10 + 0x10 * (x) + 0x00) /* Load value */
#define MTU_VAL(x) (0x10 + 0x10 * (x) + 0x04) /* Current value */
#define MTU_CR(x) (0x10 + 0x10 * (x) + 0x08) /* Control reg */
#define MTU_BGLR(x) (0x10 + 0x10 * (x) + 0x0c) /* At next overflow */
/* bits for the control register */
#define MTU_CRn_ENA 0x80
#define MTU_CRn_PERIODIC 0x40 /* if 0 = free-running */
#define MTU_CRn_PRESCALE_MASK 0x0c
#define MTU_CRn_PRESCALE_1 0x00
#define MTU_CRn_PRESCALE_16 0x04
#define MTU_CRn_PRESCALE_256 0x08
#define MTU_CRn_32BITS 0x02
#define MTU_CRn_ONESHOT 0x01 /* if 0 = wraps reloading from BGLR*/
/* Other registers are usual amba/primecell registers, currently not used */
#define MTU_ITCR 0xff0
#define MTU_ITOP 0xff4
#define MTU_PERIPH_ID0 0xfe0
#define MTU_PERIPH_ID1 0xfe4
#define MTU_PERIPH_ID2 0xfe8
#define MTU_PERIPH_ID3 0xfeC
#define MTU_PCELL0 0xff0
#define MTU_PCELL1 0xff4
#define MTU_PCELL2 0xff8
#define MTU_PCELL3 0xffC
#endif /* __ASM_ARCH_MTU_H */

2
include/configs/nhk8815.h
View File

@ -96,7 +96,7 @@
#define CONFIG_MISC_INIT_R /* call misc_init_r during start up */
/* timing informazion */
#define CONFIG_SYS_HZ (2400000 / 256) /* Timer0: 2.4Mhz + divider */
#define CONFIG_SYS_HZ 1000 /* Mandatory... */
#define CONFIG_SYS_TIMERBASE 0x101E2000
/* serial port (PL011) configuration */