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https://github.com/brain-hackers/u-boot-brain
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sh: SH7763 SCIF support
SH7763 has 3 SCIF channels. SCIF0 and 1 are same register constitution, but only SCIF2 is different. This patch work all SCIF channel. Signed-off-by: Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
This commit is contained in:
Nobuhiro Iwamatsu
Nobuhiro Iwamatsu
parent
8155efbd7a
commit
08c5fabe18
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@ -26,6 +26,8 @@
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#define SCIF_BASE SCIF0_BASE
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#elif defined (CONFIG_CONS_SCIF1)
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#define SCIF_BASE SCIF1_BASE
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#elif defined (CONFIG_CONS_SCIF2)
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#define SCIF_BASE SCIF2_BASE
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#else
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#error "Default SCIF doesn't set....."
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#endif
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@ -36,17 +38,17 @@
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#define SCSCR (vu_short *)(SCIF_BASE + 0x8)
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#define SCFCR (vu_short *)(SCIF_BASE + 0x18)
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#define SCFDR (vu_short *)(SCIF_BASE + 0x1C)
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#ifdef CONFIG_CPU_SH7720 /* SH7720 specific */
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# define SCFSR (vu_short *)(SCIF_BASE + 0x14) /* SCSSR */
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#ifdef CONFIG_CPU_SH7720 /* SH7720 specific */
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# define SCFSR (vu_short *)(SCIF_BASE + 0x14) /* SCSSR */
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# define SCFTDR (vu_char *)(SCIF_BASE + 0x20)
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# define SCFRDR (vu_char *)(SCIF_BASE + 0x24)
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#else
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# define SCFTDR (vu_char *)(SCIF_BASE + 0xC)
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# define SCFSR (vu_short *)(SCIF_BASE + 0x10)
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# define SCFSR (vu_short *)(SCIF_BASE + 0x10)
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# define SCFRDR (vu_char *)(SCIF_BASE + 0x14)
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#endif
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#if defined(CONFIG_CPU_SH7780) || \
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#if defined(CONFIG_CPU_SH7780) || \
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defined(CONFIG_CPU_SH7785)
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# define SCRFDR (vu_short *)(SCIF_BASE + 0x20)
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# define SCSPTR (vu_short *)(SCIF_BASE + 0x24)
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@ -54,20 +56,34 @@
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# define SCRER (vu_short *)(SCIF_BASE + 0x2C)
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# define LSR_ORER 1
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# define FIFOLEVEL_MASK 0xFF
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#elif defined(CONFIG_CPU_SH7763)
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# if defined (CONFIG_CONS_SCIF2)
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# define SCSPTR (vu_short *)(SCIF_BASE + 0x20)
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# define SCLSR (vu_short *)(SCIF_BASE + 0x24)
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# define LSR_ORER 1
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# define FIFOLEVEL_MASK 0x1F
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# else
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# define SCRFDR (vu_short *)(SCIF_BASE + 0x20)
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# define SCSPTR (vu_short *)(SCIF_BASE + 0x24)
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# define SCLSR (vu_short *)(SCIF_BASE + 0x28)
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# define SCRER (vu_short *)(SCIF_BASE + 0x2C)
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# define LSR_ORER 1
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# define FIFOLEVEL_MASK 0xFF
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# endif
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#elif defined(CONFIG_CPU_SH7750) || \
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defined(CONFIG_CPU_SH7751) || \
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defined(CONFIG_CPU_SH7722)
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# define SCSPTR (vu_short *)(SCIF_BASE + 0x20)
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# define SCLSR (vu_short *)(SCIF_BASE + 0x24)
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# define SCLSR (vu_short *)(SCIF_BASE + 0x24)
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# define LSR_ORER 1
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# define FIFOLEVEL_MASK 0x1F
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#elif defined(CONFIG_CPU_SH7720)
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# define SCLSR (vu_short *)(SCIF_BASE + 0x24)
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# define SCLSR (vu_short *)(SCIF_BASE + 0x24)
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# define LSR_ORER 0x0200
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# define FIFOLEVEL_MASK 0x1F
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#elif defined(CONFIG_CPU_SH7710)
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#elif defined(CONFIG_CPU_SH7710) || \
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defined(CONFIG_CPU_SH7712)
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# define SCLSR SCFSR /* SCSSR */
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# define SCLSR SCFSR /* SCSSR */
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# define LSR_ORER 1
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# define FIFOLEVEL_MASK 0x1F
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#endif
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@ -75,34 +91,34 @@
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/* SCBRR register value setting */
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#if defined(CONFIG_CPU_SH7720)
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# define SCBRR_VALUE(bps, clk) (((clk*2)+16*bps)/(32*bps)-1)
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#else /* Generic SuperH */
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#else /* Generic SuperH */
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# define SCBRR_VALUE(bps, clk) ((clk+16*bps)/(32*bps)-1)
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#endif
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#define SCR_RE (1 << 4)
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#define SCR_TE (1 << 5)
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#define FCR_RFRST (1 << 1) /* RFCL */
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#define FCR_TFRST (1 << 2) /* TFCL */
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#define FSR_DR (1 << 0)
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#define FSR_RDF (1 << 1)
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#define FSR_FER (1 << 3)
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#define FSR_BRK (1 << 4)
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#define FSR_FER (1 << 3)
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#define FSR_TEND (1 << 6)
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#define FSR_ER (1 << 7)
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#define SCR_RE (1 << 4)
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#define SCR_TE (1 << 5)
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#define FCR_RFRST (1 << 1) /* RFCL */
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#define FCR_TFRST (1 << 2) /* TFCL */
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#define FSR_DR (1 << 0)
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#define FSR_RDF (1 << 1)
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#define FSR_FER (1 << 3)
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#define FSR_BRK (1 << 4)
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#define FSR_FER (1 << 3)
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#define FSR_TEND (1 << 6)
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#define FSR_ER (1 << 7)
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/*----------------------------------------------------------------------*/
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void serial_setbrg (void)
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void serial_setbrg(void)
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{
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DECLARE_GLOBAL_DATA_PTR;
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*SCBRR = SCBRR_VALUE(gd->baudrate,CONFIG_SYS_CLK_FREQ);
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*SCBRR = SCBRR_VALUE(gd->baudrate, CONFIG_SYS_CLK_FREQ);
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}
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int serial_init (void)
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int serial_init(void)
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{
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*SCSCR = (SCR_RE | SCR_TE);
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*SCSMR = 0 ;
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*SCSMR = 0;
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*SCSMR = 0;
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*SCFCR = (FCR_RFRST | FCR_TFRST);
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*SCFCR;
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@ -112,21 +128,21 @@ int serial_init (void)
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return 0;
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}
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static int serial_rx_fifo_level (void)
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static int serial_rx_fifo_level(void)
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{
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#if defined(CONFIG_SH4A)
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#if defined(SCRFDR)
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return (*SCRFDR >> 0) & FIFOLEVEL_MASK;
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#else
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return (*SCFDR >> 0) & FIFOLEVEL_MASK;
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#endif
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}
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void serial_raw_putc (const char c)
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void serial_raw_putc(const char c)
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{
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unsigned int fsr_bits_to_clear;
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while (1) {
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if (*SCFSR & FSR_TEND) { /* Tx fifo is empty */
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if (*SCFSR & FSR_TEND) { /* Tx fifo is empty */
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fsr_bits_to_clear = FSR_TEND;
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break;
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}
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@ -137,65 +153,67 @@ void serial_raw_putc (const char c)
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*SCFSR &= ~fsr_bits_to_clear;
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}
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void serial_putc (const char c)
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void serial_putc(const char c)
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{
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if (c == '\n')
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serial_raw_putc ('\r');
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serial_raw_putc (c);
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serial_raw_putc('\r');
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serial_raw_putc(c);
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}
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void serial_puts (const char *s)
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void serial_puts(const char *s)
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{
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char c;
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while ((c = *s++) != 0)
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serial_putc (c);
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serial_putc(c);
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}
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int serial_tstc (void)
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int serial_tstc(void)
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{
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return serial_rx_fifo_level() ? 1 : 0;
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return serial_rx_fifo_level()? 1 : 0;
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}
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#define FSR_ERR_CLEAR 0x0063
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#define RDRF_CLEAR 0x00fc
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void handle_error( void ){
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#define FSR_ERR_CLEAR 0x0063
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#define RDRF_CLEAR 0x00fc
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void handle_error(void)
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{
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(void)*SCFSR ;
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*SCFSR = FSR_ERR_CLEAR ;
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(void)*SCLSR ;
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*SCLSR = 0x00 ;
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(void)*SCFSR;
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*SCFSR = FSR_ERR_CLEAR;
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(void)*SCLSR;
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*SCLSR = 0x00;
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}
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int serial_getc_check( void ){
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int serial_getc_check(void)
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{
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unsigned short status;
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status = *SCFSR ;
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status = *SCFSR;
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if (status & (FSR_FER | FSR_FER | FSR_ER | FSR_BRK))
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if (status & (FSR_FER | FSR_ER | FSR_BRK))
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handle_error();
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if( *SCLSR & LSR_ORER )
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if (*SCLSR & LSR_ORER)
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handle_error();
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return (status & ( FSR_DR | FSR_RDF ));
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return (status & (FSR_DR | FSR_RDF));
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}
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int serial_getc (void)
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int serial_getc(void)
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{
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unsigned short status ;
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unsigned short status;
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char ch;
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while(!serial_getc_check());
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while (!serial_getc_check()) ;
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ch = *SCFRDR;
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status = *SCFSR ;
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status = *SCFSR;
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*SCFSR = RDRF_CLEAR ;
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*SCFSR = RDRF_CLEAR;
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if (status & (FSR_FER | FSR_FER | FSR_ER | FSR_BRK))
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handle_error();
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if( *SCLSR & LSR_ORER )
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if (*SCLSR & LSR_ORER)
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handle_error();
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return ch ;
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return ch;
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}
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#endif /* CFG_SCIF_CONSOLE */
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#endif /* CFG_SCIF_CONSOLE */
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