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ARM: imx: Add support for the primary/secondary bmode to MX53 

Implement the 'getprisec' subcommand of 'bmode' command for i.MX53 and
also the primary/secondary bootmode switching.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: NXP i.MX U-Boot Team <uboot-imx@nxp.com>
Cc: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
This commit is contained in:
Marek Vasut 2020-09-05 00:53:01 +02:00 committed by Stefano Babic
parent 95b3d6a419
commit 08945cceff
1 changed files with 20 additions and 1 deletions
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21
arch/arm/mach-imx/mx5/soc.c
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@ -87,10 +87,27 @@ void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
#endif
#ifdef CONFIG_MX53
#define IMX53_SRTC_LPGR_PERSIST_SECONDARY_BOOT BIT(30)
void boot_mode_apply(unsigned cfg_val)
{
writel(cfg_val, &((struct srtc_regs *)SRTC_BASE_ADDR)->lpgr);
void *lpgr = &((struct srtc_regs *)SRTC_BASE_ADDR)->lpgr;
if (cfg_val == MAKE_CFGVAL_PRIMARY_BOOT)
clrbits_le32(lpgr, IMX53_SRTC_LPGR_PERSIST_SECONDARY_BOOT);
else if (cfg_val == MAKE_CFGVAL_SECONDARY_BOOT)
setbits_le32(lpgr, IMX53_SRTC_LPGR_PERSIST_SECONDARY_BOOT);
else
writel(cfg_val, lpgr);
}
int boot_mode_getprisec(void)
{
void *lpgr = &((struct srtc_regs *)SRTC_BASE_ADDR)->lpgr;
return !!(readl(lpgr) & IMX53_SRTC_LPGR_PERSIST_SECONDARY_BOOT);
}
/*
* cfg_val will be used for
* Boot_cfg3[7:0]:Boot_cfg2[7:0]:Boot_cfg1[7:0]
@ -112,6 +129,8 @@ const struct boot_mode soc_boot_modes[] = {
{"esdhc2", MAKE_CFGVAL(0x40, 0x20, 0x08, 0x12)},
{"esdhc3", MAKE_CFGVAL(0x40, 0x20, 0x10, 0x12)},
{"esdhc4", MAKE_CFGVAL(0x40, 0x20, 0x18, 0x12)},
{"primary", MAKE_CFGVAL_PRIMARY_BOOT},
{"secondary", MAKE_CFGVAL_SECONDARY_BOOT},
{NULL, 0},
};
#endif